Hi @2dom and contributors @xsrf @opticron @witnessmenow @Rasmusfk @sovcik @per1234 ,
We’re currently trying to integrate HUB75 LED panels with the PxMatrix library as part of an ongoing project.
We initially attempted to interface an ABC-type P2.5 panel that uses the following ICs:
Given this blocker, we need to purchase a new compatible panel, but the documentation on exact supported configurations is limited.
Could you provide guidance on:
- Known working HUB75 / HUB75E panel types
- Recommended IC combinations (e.g., ICND2037, ICND2038 etc.)
- Any specific models or vendors that are known to work out-of-the-box
- Whether ABC addressing causes any limitations or if ABC/ABCD differences are automatically handled by the library
We want to ensure the next panel we purchase is fully compatible with the library.
Determining the Maximum Possible Frame Rate
the theoretical refresh/frame rate depends on:
- Panel width × height
- Color depth
- ESP32’s DMA output capability
- Panel’s max input clock (typically 20–25 MHz)
- Number of panels chained (affects doubled data size)
To plan our system properly:
Is it possible to compute the theoretical maximum frame rate from these variables?
For example, if we know:
- Width × Height
- Color depth (e.g., 24 bpp or library bit-plane depth)
- Scan type (1/16, 1/32)
- Panel clock limit
- Library’s bit-plane implementation
- ESP32’s DMA throughput
…can we derive an approximate formula to estimate the upper bound (e.g., “You cannot exceed 150–200 Hz for a 128×64 panel at 24 bpp”)?
A formula or even a code reference explaining the limiting steps in the DMA pipeline would help us determine whether 240 Hz is realistically achievable.
Does Any Part of the Panel Hardware Limit the Frame Rate?
Specifically:
- Do multiplexers/buffers (like HX6158HS, DP245D) impose frame-rate limits?
- Or is the bottleneck always the data size × clock speed × bit-plane algorithm?
Hi @2dom and contributors @xsrf @opticron @witnessmenow @Rasmusfk @sovcik @per1234 ,
We’re currently trying to integrate HUB75 LED panels with the PxMatrix library as part of an ongoing project.
We initially attempted to interface an ABC-type P2.5 panel that uses the following ICs:
ICND1065A × 48
HX6158HS × 8
DP245D × 3
ICND1065A is a PWM-type driver and is not supported by DIY library .
No widely used DIY libraries support ICND1065-based panels.
Given this blocker, we need to purchase a new compatible panel, but the documentation on exact supported configurations is limited.
Could you provide guidance on:
We want to ensure the next panel we purchase is fully compatible with the library.
Determining the Maximum Possible Frame Rate
the theoretical refresh/frame rate depends on:
To plan our system properly:
Is it possible to compute the theoretical maximum frame rate from these variables?
For example, if we know:
…can we derive an approximate formula to estimate the upper bound (e.g., “You cannot exceed 150–200 Hz for a 128×64 panel at 24 bpp”)?
A formula or even a code reference explaining the limiting steps in the DMA pipeline would help us determine whether 240 Hz is realistically achievable.
Does Any Part of the Panel Hardware Limit the Frame Rate?
Specifically: