add hardfloat

Author: CodingPlatelets

.gitmodules

@@ -1,3 +1,6 @@
-[submodule "fputil"]
-	path = fputil
+[submodule "depencies/fputil"]
+	path = depencies/fputil
 	url = git@github.com:CodingPlatelets/fp-division-pipelined.git
+[submodule "depencies/hardfloat"]
+	path = depencies/hardfloat
+	url = git@github.com:CodingPlatelets/berkeley-hardfloat.git

build.sbt

@@ -8,7 +8,8 @@ val chiselVersion = "6.2.0"
 lazy val commonChiselSettings = Seq(
   libraryDependencies ++= Seq(
     "org.chipsalliance" %% "chisel" % chiselVersion,
-    "edu.berkeley.cs" %% "chiseltest" % "6.0.0"
+    "edu.berkeley.cs" %% "chiseltest" % "6.0.0",
+    // "edu.berkeley.cs" %% "hardfloat" % "1.5.1-SNAPSHOT"
   ),
   resolvers += "aliyun".at("https://maven.aliyun.com/repository/public"),
   scalacOptions ++= Seq(
@@ -30,7 +31,12 @@ lazy val root = (project in file("."))
     commonChiselSettings
   )
 
-lazy val fputil = (project in file("fputil/src/main/scala")).settings(
-  name := "fputil",
-  commonChiselSettings
-)
+lazy val fputil = Project("fputil", file("depencies/fputil/src"))
+  .settings(
+    name := "fputil",
+    commonChiselSettings
+  )
+  .settings(
+    Compile / scalaSource := baseDirectory.value / "main" / "scala",
+    Compile / resourceDirectory := baseDirectory.value / "main" / "resources"
+  )

build.sc

@@ -14,6 +14,10 @@ def defaultVersions = Map(
   "chiseltest" -> ivy"edu.berkeley.cs::chiseltest:6.0.0"
 )
 
+def extendDependencies = Map(
+  "hardfloat" -> ivy"edu.berkeley.cs::hardfloat:1.5-SNAPSHOT"
+)
+
 trait HasChisel extends SbtModule {
   def chiselModule: Option[ScalaModule] = None
 
@@ -34,7 +38,7 @@ trait HasChisel extends SbtModule {
 }
 
 object fputil extends HasChisel {
-  override def millSourcePath = os.pwd / "fputil"
+  override def millSourcePath = os.pwd / "depencies" / "fputil" 
 }
 
 trait transformer_MMModule extends ScalaModule {
@@ -66,7 +70,8 @@ object trans extends transformer_MMModule with HasChisel { m =>
   // def mainClass = Some("vitiskernel.VitisRTLKernelVerilog")
   def mainClass = Some("kernel.NewFeatureTest")
   override def ivyDeps = super.ivyDeps() ++ Agg(
-    defaultVersions("chiseltest")
+    defaultVersions("chiseltest"),
+    extendDependencies("hardfloat")
   )
 
   object test extends SbtTests with TestModule.ScalaTest {

fputil depencies/fputilfputil renamed to depencies/fputil

@@ -0,0 +1,55 @@
+package kernel.alu
+
+import chisel3._
+import chisel3.util._
+import hardfloat._
+object FPU {
+  def equivRecFN(expWidth: Int, sigWidth: Int, a: UInt, b: UInt) = {
+    val top4A = a(expWidth + sigWidth, expWidth + sigWidth - 3)
+    val top4B = b(expWidth + sigWidth, expWidth + sigWidth - 3)
+    Mux(
+      (top4A(2, 0) === 0.U) || (top4A(2, 0) === 7.U),
+      (top4A === top4B) && (a(sigWidth - 2, 0) === b(sigWidth - 2, 0)),
+      Mux((top4A(2, 0) === 6.U), (top4A === top4B), (a === b))
+    )
+  }
+}
+
+class ValExec_MulRecFN(expWidth: Int, sigWidth: Int) extends Module {
+  val io = IO(new Bundle {
+    val a = Input(Bits((expWidth + sigWidth).W))
+    val b = Input(Bits((expWidth + sigWidth).W))
+    val roundingMode = Input(UInt(3.W))
+    val detectTininess = Input(UInt(1.W))
+
+    val expected = new Bundle {
+      val out = Input(Bits((expWidth + sigWidth).W))
+      val exceptionFlags = Input(Bits(5.W))
+      val recOut = Output(Bits((expWidth + sigWidth + 1).W))
+    }
+
+    val actual = new Bundle {
+      val out = Output(Bits((expWidth + sigWidth + 1).W))
+      val exceptionFlags = Output(Bits(5.W))
+    }
+
+    val check = Output(Bool())
+    val pass = Output(Bool())
+  })
+
+  val mulRecFN = Module(new MulRecFN(expWidth, sigWidth))
+  mulRecFN.io.a := recFNFromFN(expWidth, sigWidth, io.a)
+  mulRecFN.io.b := recFNFromFN(expWidth, sigWidth, io.b)
+  mulRecFN.io.roundingMode := io.roundingMode
+  mulRecFN.io.detectTininess := io.detectTininess
+
+  io.expected.recOut := recFNFromFN(expWidth, sigWidth, io.expected.out)
+
+  io.actual.out := mulRecFN.io.out
+  io.actual.exceptionFlags := mulRecFN.io.exceptionFlags
+
+  io.check := true.B
+  io.pass :=
+    FPU.equivRecFN(expWidth, sigWidth, io.actual.out, io.expected.recOut) &&
+      (io.actual.exceptionFlags === io.expected.exceptionFlags)
+}

depencies/hardfloat

@@ -0,0 +1,27 @@
+package kernel.alu
+
+import chisel3._
+
+class FXP(val IntWidth: Int, val FractionalWidth: Int) extends Bundle {
+  def signWidth = IntWidth + FractionalWidth - 1
+}
+
+object FXP {
+  def hex2SignedInt(hex: String, width: Int) = {
+    val maxUnsignedValue = BigInt(2).pow(width)
+    val maxPositiveValue = BigInt(2).pow(width - 1)
+    val resTmp = BigInt(hex, 16)
+    if (resTmp >= maxPositiveValue) { resTmp - maxUnsignedValue }
+    else { resTmp }
+  }
+
+  def maxUnsignedValue(IntWidth: Int, FractionalWidth: Int) = BigInt(2).pow(IntWidth + FractionalWidth)
+  def maxPositiveValue(IntWidth: Int, FractionalWidth: Int) = BigInt(2).pow(IntWidth + FractionalWidth - 1)
+
+  def bits2RealValue(value: BigInt, IntWidth: Int, FractionalWidth: Int) = {
+    val maxPositiveValue = FXP.maxPositiveValue(IntWidth, FractionalWidth)
+    BigDecimal(if (value >= maxPositiveValue) { value - maxUnsignedValue(IntWidth, FractionalWidth) }
+    else { value }) / (BigDecimal(2).pow(FractionalWidth))
+  }
+
+}

src/main/scala/kernel/alu/FPU.scala

@@ -5,6 +5,8 @@ import chisel3.util._
 import kernel.utils.DebugLog
 import fputil.FPMult
 import fputil.FPAdd
+import hardfloat._
+
 trait GEMMAccuracyConfig {
   val I: Int = 4
   val F: Int = 12
@@ -34,25 +36,6 @@ class PEFxp extends Module with GEMMAccuracyConfig with DebugLog {
   io.out := res
 }
 
-// a * b + c
-class FMA(width: Int = 32) extends Module with DebugLog {
-  val io = IO(new Bundle {
-    val a = Input(Valid(UInt(width.W)))
-    val b = Input(Valid(UInt(width.W)))
-    val c = Input(Valid(UInt(width.W)))
-    val out = Valid(UInt(width.W))
-  })
-
-  // one cycle latency
-  val tmp = FPMult(width)(io.a.bits, io.b.bits, io.a.valid && io.b.valid)
-
-  // three cycle latency
-  val tmpRes = FPAdd(width)(io.c.bits, tmp.bits, io.c.valid && tmp.valid)
-
-  io.out.bits := Mux(tmpRes.valid, tmpRes.bits, io.c.bits)
-  io.out.valid := tmpRes.valid
-}
-
 class PEFp(width: Int = 32, size: Int = 4) extends Module with DebugLog {
   val io = IO(new Bundle {
     val in_h = Input(Valid(UInt(width.W)))

src/main/scala/kernel/alu/FXP.scala

@@ -1,3 +1,26 @@
+/***************************************************************************************
+* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
+* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
+* Copyright (c) 2020-2021 Peng Cheng Laboratory
+*
+* XiangShan is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*          http://license.coscl.org.cn/MulanPSL2
+*
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+*
+* See the Mulan PSL v2 for more details.
+*
+*
+* Acknowledgement
+*
+* This implementation is inspired by several key papers:
+* [1] Elisardo Antelo, Tomas Lang, Paolo Montuschi, and Alberto Nannarelli. "[Digit-recurrence dividers with reduced
+* logical depth.](https://doi.org/10.1109/TC.2005.115)" IEEE Transactions on Computers 54.7: 837-851. 2005.
+***************************************************************************************/
 package kernel.alu
 
 import chisel3._