diff --git a/hw1.t.v b/hw1.t.v
new file mode 100644
index 0000000..53917bd
--- /dev/null
+++ b/hw1.t.v
@@ -0,0 +1,84 @@
+`include "hw1.v"
+
+module demorgan_test ();
+
+  // Instantiate device/module under test
+  reg A, B;                // Primary test inputs
+  wire nA, nB, nAnB;    // Test outputs
+
+  demorgan dut(.A (A),.B (B),.nA (nA),.nB (nB),.nAandnB (nAnB));  // Module to be tested
+
+
+  // Run sequence of test stimuli
+  initial begin
+    $display("A B | ~A ~B | ~A~B ");            // Prints header for truth table
+    A=0;B=0; #1                                 // Set A and B, wait for update (#1)
+    $display("%b %b |  %b  %b |    %b  ", A,B, nA, nB, nAnB);
+    A=0;B=1; #1                                 // Set A and B, wait for new update
+    $display("%b %b |  %b  %b |    %b  ", A,B, nA, nB, nAnB);
+    A=1;B=0; #1
+    $display("%b %b |  %b  %b |    %b  ", A,B, nA, nB, nAnB);
+    A=1;B=1; #1
+    $display("%b %b |  %b  %b |    %b  ", A,B, nA, nB, nAnB);
+  end
+endmodule    // End demorgan_test
+
+module nAornB_test ();
+
+  reg A, B;
+  wire nA, nB, nAnB;
+
+  nAornB dut(.A (A),.B (B),.nA (nA),.nB (nB),.nAornB (nAnB));
+
+  initial begin
+    $display("A B | ~A ~B | ~A+~B");
+    A=0;B=0; #1
+    $display("%b %b |  %b  %b |    %b  ", A,B, nA, nB, nAnB);
+    A=0;B=1; #1
+    $display("%b %b |  %b  %b |    %b  ", A,B, nA, nB, nAnB);
+    A=1;B=0; #1
+    $display("%b %b |  %b  %b |    %b  ", A,B, nA, nB, nAnB);
+    A=1;B=1; #1
+    $display("%b %b |  %b  %b |    %b  ", A,B, nA, nB, nAnB);
+  end
+endmodule
+
+module nAorB_test ();
+
+  reg A, B;
+  wire AorB, nAB;
+
+  nAorB dut(.A (A), .B(B), .AorB (AorB), .nAorB (nAB));
+
+  initial begin
+    $display("A B | A+B | ~A+B");
+    A=0;B=0; #1
+    $display("%b %b | %b | %b  ", A,B, AorB, nAB);
+    A=0;B=1; #1
+    $display("%b %b | %b | %b  ", A,B, AorB, nAB);
+    A=1;B=0; #1
+    $display("%b %b | %b | %b  ", A,B, AorB, nAB);
+    A=1;B=1; #1
+    $display("%b %b | %b | %b  ", A,B, AorB, nAB);
+  end
+endmodule
+
+module nAandB_test ();
+
+  reg A, B;
+  wire AB, nAnB;
+
+  nAandB dut(.A (A), .B (B), .AandB (AB), .nAandB (nAnB));
+
+  initial begin
+    $display("A B | AB | ~AB");
+    A=0;B=0; #1
+    $display("%b %b | %b | %b  ", A,B, AB, nAnB);
+    A=0;B=1; #1
+    $display("%b %b | %b | %b  ", A,B, AB, nAnB);
+    A=1;B=0; #1
+    $display("%b %b | %b | %b  ", A,B, AB, nAnB);
+    A=1;B=1; #1
+    $display("%b %b | %b | %b  ", A,B, AB, nAnB);
+  end
+endmodule
\ No newline at end of file
diff --git a/hw1.v b/hw1.v
new file mode 100644
index 0000000..bb693cf
--- /dev/null
+++ b/hw1.v
@@ -0,0 +1,61 @@
+module nAornB(A,B,nA,nB,nAornB);
+
+  input A;
+  input B;
+  output nA;
+  output nB;
+  output nAornB;
+
+  wire nA;
+  wire nB;
+  
+  not Ainv(nA, A);
+  not Binv(nB, B);
+  or orgate(nAornB, nA, nB);
+
+endmodule
+
+module demorgan(A,B,nA,nB,nAandnB);
+
+  input A;
+  input B;
+  output nA;
+  output nB;
+  output nAandnB;
+
+  wire nA;
+  wire nB;
+
+  not Ainv(nA, A);  	// Top inverter is named Ainv, takes signal A as input and produces signal nA
+  not Binv(nB, B);
+  and andgate(nAandnB, nA, nB); 	// AND gate produces nAandnB from nA and nB
+
+endmodule
+
+module nAorB(A,B,AorB,nAorB);
+
+  input A;
+  input B;
+  output AorB;
+  output nAorB;
+
+  wire AorB;
+
+  or orgate(AorB, A, B);
+  not AorBinv(nAorB, AorB);
+
+endmodule
+
+module nAandB(A,B,AandB,nAandB);
+
+  input A;
+  input B;
+  output AandB;
+  output nAandB;
+
+  wire AandB;
+
+  and andgate(AandB, A, B);
+  not inverter(nAandB, AandB);
+
+endmodule
\ No newline at end of file
diff --git a/results.txt b/results.txt
new file mode 100644
index 0000000..aa58a91
--- /dev/null
+++ b/results.txt
@@ -0,0 +1,25 @@
+# nAornB
+# A B | ~A ~B | ~A+~B
+# 0 0 |  1  1 |    1  
+# 0 1 |  1  0 |    1  
+# 1 0 |  0  1 |    1  
+# 1 1 |  0  0 |    0  
+# nAorB
+# A B | A+B | ~A+B
+# 0 0 | 0 | 1  
+# 0 1 | 1 | 0  
+# 1 0 | 1 | 0  
+# 1 1 | 1 | 0 
+# nAandB
+# A B | AB | ~AB
+# 0 0 | 0 | 1  
+# 0 1 | 0 | 1  
+# 1 0 | 0 | 1  
+# 1 1 | 1 | 0  
+# nAandnB
+# A B | ~A ~B | ~A~B 
+# 0 0 |  1  1 |    1  
+# 0 1 |  1  0 |    0  
+# 1 0 |  0  1 |    0  
+# 1 1 |  0  0 |    0  
+