diff --git a/hw1.t.v b/hw1.t.v new file mode 100644 index 0000000..1563f12 --- /dev/null +++ b/hw1.t.v @@ -0,0 +1,24 @@ +`include "hw1.v" + +module demorgan_test (); + + // Instantiate device/module under test + reg A, B; // Primary test inputs + wire nA, nB, nAandnB, AnandB, nAornB, AnorB; // Test outputs + + demorgan dut(A, B, nA, nB, nAandnB, AnandB, nAornB, AnorB); // Module to be tested + + + // Run sequence of test stimuli + initial begin + $display("A B | ~A ~B | ~A~B | ~(AB) | ~A+~B | ~(A+B) |"); // Prints header for truth table + A=0;B=0; #1 // Set A and B, wait for update (#1) + $display("%b %b | %b %b | %b | %b | %b | %b |", A,B, nA, nB, nAandnB, AnandB, nAornB, AnorB); + A=0;B=1; #1 // Set A and B, wait for new update + $display("%b %b | %b %b | %b | %b | %b | %b |", A,B, nA, nB, nAandnB, AnandB, nAornB, AnorB); + A=1;B=0; #1 + $display("%b %b | %b %b | %b | %b | %b | %b |", A,B, nA, nB, nAandnB, AnandB, nAornB, AnorB); + A=1;B=1; #1 + $display("%b %b | %b %b | %b | %b | %b | %b |", A,B, nA, nB, nAandnB, AnandB, nAornB, AnorB); + end +endmodule // End demorgan_test diff --git a/hw1.v b/hw1.v new file mode 100644 index 0000000..7b9775b --- /dev/null +++ b/hw1.v @@ -0,0 +1,25 @@ +module demorgan +( + input A, // Single bit inputs + input B, + output nA, // Output intermediate complemented inputs + output nB, + output nAandnB, // Single bit output, (~A)*(~B) + output AnandB, + output nAornB, + output AnorB +); + + wire nA; + wire nB; + not Ainv(nA, A); // Top inverter is named Ainv, takes signal A as input and produces signal nA + not Binv(nB, B); + and andgate(nAandnB, nA, nB); // AND gate produces nAandnB from nA and nB + nand nandgate(AnandB, A, B); + or orgate(nAornB, nA, nB); + nor norgate(AnorB, A, B); + + + + +endmodule diff --git a/results.txt b/results.txt new file mode 100644 index 0000000..adc2c0d --- /dev/null +++ b/results.txt @@ -0,0 +1,5 @@ +A B | ~A ~B | ~A~B | ~(AB) | ~A+~B | ~(A+B) | +0 0 | 1 1 | 1 | 1 | 1 | 1 | +0 1 | 1 0 | 0 | 1 | 1 | 0 | +1 0 | 0 1 | 0 | 1 | 1 | 0 | +1 1 | 0 0 | 0 | 0 | 0 | 0 |