diff --git a/hw1 b/hw1
new file mode 100755
index 0000000..625d7dd
--- /dev/null
+++ b/hw1
@@ -0,0 +1,85 @@
+#! /usr/local/bin/vvp
+:ivl_version "0.10.0 (devel)" "(s20150513)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x1f030d0 .scope module, "demorgan_test" "demorgan_test" 2 3;
+ .timescale 0 0;
+v0x1f2a890_0 .var "A", 0 0;
+v0x1f2a950_0 .net "AB", 0 0, L_0x1f2b3c0;  1 drivers
+v0x1f2aa20_0 .net "AorB", 0 0, L_0x1f2b480;  1 drivers
+v0x1f2ab20_0 .var "B", 0 0;
+v0x1f2abf0_0 .net "nA", 0 0, L_0x1f2b130;  1 drivers
+v0x1f2ac90_0 .net "nAB", 0 0, L_0x1f2b710;  1 drivers
+v0x1f2ad60_0 .net "nAandnB", 0 0, L_0x1f2b300;  1 drivers
+v0x1f2ae30_0 .net "nAorB", 0 0, L_0x1f2b660;  1 drivers
+v0x1f2af00_0 .net "nAornB", 0 0, L_0x1f2b780;  1 drivers
+v0x1f2b060_0 .net "nB", 0 0, L_0x1f2b1f0;  1 drivers
+S_0x1f03250 .scope module, "dut" "demorgan" 2 9, 3 1 0, S_0x1f030d0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A"
+    .port_info 1 /INPUT 1 "B"
+    .port_info 2 /OUTPUT 1 "nA"
+    .port_info 3 /OUTPUT 1 "nB"
+    .port_info 4 /OUTPUT 1 "AB"
+    .port_info 5 /OUTPUT 1 "AorB"
+    .port_info 6 /OUTPUT 1 "nAandnB"
+    .port_info 7 /OUTPUT 1 "nAorB"
+    .port_info 8 /OUTPUT 1 "nAornB"
+    .port_info 9 /OUTPUT 1 "nAB"
+L_0x1f2b130 .functor NOT 1, v0x1f2a890_0, C4<0>, C4<0>, C4<0>;
+L_0x1f2b1f0 .functor NOT 1, v0x1f2ab20_0, C4<0>, C4<0>, C4<0>;
+L_0x1f2b300 .functor AND 1, L_0x1f2b130, L_0x1f2b1f0, C4<1>, C4<1>;
+L_0x1f2b3c0 .functor AND 1, v0x1f2a890_0, v0x1f2ab20_0, C4<1>, C4<1>;
+L_0x1f2b480 .functor OR 1, v0x1f2a890_0, v0x1f2ab20_0, C4<0>, C4<0>;
+L_0x1f2b660 .functor NOT 1, L_0x1f2b480, C4<0>, C4<0>, C4<0>;
+L_0x1f2b710 .functor NOT 1, L_0x1f2b3c0, C4<0>, C4<0>, C4<0>;
+L_0x1f2b780 .functor OR 1, L_0x1f2b130, L_0x1f2b1f0, C4<0>, C4<0>;
+v0x1f0f6b0_0 .net "A", 0 0, v0x1f2a890_0;  1 drivers
+v0x1f29f40_0 .net "AB", 0 0, L_0x1f2b3c0;  alias, 1 drivers
+v0x1f2a000_0 .net "AorB", 0 0, L_0x1f2b480;  alias, 1 drivers
+v0x1f2a0d0_0 .net "B", 0 0, v0x1f2ab20_0;  1 drivers
+v0x1f2a190_0 .net "nA", 0 0, L_0x1f2b130;  alias, 1 drivers
+v0x1f2a2a0_0 .net "nAB", 0 0, L_0x1f2b710;  alias, 1 drivers
+v0x1f2a360_0 .net "nAandnB", 0 0, L_0x1f2b300;  alias, 1 drivers
+v0x1f2a420_0 .net "nAorB", 0 0, L_0x1f2b660;  alias, 1 drivers
+v0x1f2a4e0_0 .net "nAornB", 0 0, L_0x1f2b780;  alias, 1 drivers
+v0x1f2a630_0 .net "nB", 0 0, L_0x1f2b1f0;  alias, 1 drivers
+    .scope S_0x1f030d0;
+T_0 ;
+    %vpi_call 2 14 "$display", "A B | AB | A+B | ~A ~B | ~A~B | ~(A+B) | ~A+~B | ~(AB)" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1f2a890_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1f2ab20_0, 0, 1;
+    %delay 1, 0;
+    %vpi_call 2 16 "$display", "%b %b |  %b |   %b |  %b  %b |    %b |      %b |     %d |     %d", v0x1f2a890_0, v0x1f2ab20_0, v0x1f2a950_0, v0x1f2aa20_0, v0x1f2abf0_0, v0x1f2b060_0, v0x1f2ad60_0, v0x1f2ae30_0, v0x1f2af00_0, v0x1f2ac90_0 {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1f2a890_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1f2ab20_0, 0, 1;
+    %delay 1, 0;
+    %vpi_call 2 18 "$display", "%b %b |  %b |   %b |  %b  %b |    %b |      %b |     %d |     %d", v0x1f2a890_0, v0x1f2ab20_0, v0x1f2a950_0, v0x1f2aa20_0, v0x1f2abf0_0, v0x1f2b060_0, v0x1f2ad60_0, v0x1f2ae30_0, v0x1f2af00_0, v0x1f2ac90_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1f2a890_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1f2ab20_0, 0, 1;
+    %delay 1, 0;
+    %vpi_call 2 20 "$display", "%b %b |  %b |   %b |  %b  %b |    %b |      %b |     %d |     %d", v0x1f2a890_0, v0x1f2ab20_0, v0x1f2a950_0, v0x1f2aa20_0, v0x1f2abf0_0, v0x1f2b060_0, v0x1f2ad60_0, v0x1f2ae30_0, v0x1f2af00_0, v0x1f2ac90_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1f2a890_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1f2ab20_0, 0, 1;
+    %delay 1, 0;
+    %vpi_call 2 22 "$display", "%b %b |  %b |   %b |  %b  %b |    %b |      %b |     %d |     %d", v0x1f2a890_0, v0x1f2ab20_0, v0x1f2a950_0, v0x1f2aa20_0, v0x1f2abf0_0, v0x1f2b060_0, v0x1f2ad60_0, v0x1f2ae30_0, v0x1f2af00_0, v0x1f2ac90_0 {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "hw1.t.v";
+    "./hw1.v";
diff --git a/hw1.t.v b/hw1.t.v
new file mode 100644
index 0000000..e784692
--- /dev/null
+++ b/hw1.t.v
@@ -0,0 +1,24 @@
+`include "hw1.v"
+
+module demorgan_test ();
+
+  // Instantiate device/module under test
+  reg A, B;                // Primary test inputs
+  wire nA, nB, nAandnB, AB, AorB;    // Test outputs
+
+  demorgan dut(A, B, nA, nB, AB, AorB, nAandnB, nAorB, nAornB, nAB);  // Module to be tested
+
+
+  // Run sequence of test stimuli
+  initial begin
+    $display("A B | AB | A+B | ~A ~B | ~A~B | ~(A+B) | ~A+~B | ~(AB)");            // Prints header for truth table
+    A=0;B=0; #1
+    $display("%b %b |  %b |   %b |  %b  %b |    %b |      %b |     %d |     %d", A,B, AB, AorB, nA, nB, nAandnB, nAorB, nAornB, nAB);
+    A=0;B=1; #1
+    $display("%b %b |  %b |   %b |  %b  %b |    %b |      %b |     %d |     %d", A,B, AB, AorB, nA, nB, nAandnB, nAorB, nAornB, nAB);
+    A=1;B=0; #1
+    $display("%b %b |  %b |   %b |  %b  %b |    %b |      %b |     %d |     %d", A,B, AB, AorB, nA, nB, nAandnB, nAorB, nAornB, nAB);
+    A=1;B=1; #1
+    $display("%b %b |  %b |   %b |  %b  %b |    %b |      %b |     %d |     %d", A,B, AB, AorB, nA, nB, nAandnB, nAorB, nAornB, nAB);
+  end
+endmodule    // End demorgan_test
diff --git a/hw1.v b/hw1.v
new file mode 100644
index 0000000..6f69a9d
--- /dev/null
+++ b/hw1.v
@@ -0,0 +1,28 @@
+module demorgan
+(
+  input  A,          // Single bit inputs
+  input  B,
+  output nA,         // Output intermediate complemented inputs
+  output nB,
+  output AB,
+  output AorB,
+  output nAandnB,     // Single bit output, (~A)*(~B)
+  output nAorB,
+  output nAornB,
+  output nAB
+);
+
+  wire nA;
+  wire nB;
+  wire AorB;
+  wire AB;
+  not Ainv(nA, A);  	// Top inverter is named Ainv, takes signal A as input and produces signal nA
+  not Binv(nB, B);
+  and andgate(nAandnB, nA, nB); 	// AND gate produces nAandnB from nA and nB
+  and andgate2(AB,A,B);
+  or  orgate(AorB,A,B);
+  not AorBinv(nAorB,AorB);
+  not ABinv(nAB,AB);
+  or  orgate2(nAornB, nA, nB);
+
+endmodule
diff --git a/results.txt b/results.txt
new file mode 100644
index 0000000..a451b73
--- /dev/null
+++ b/results.txt
@@ -0,0 +1,5 @@
+A B | AB | A+B | ~A ~B | ~A~B | ~(A+B) | ~A+~B | ~(AB)
+0 0 |  0 |   0 |  1  1 |    1 |      1 |     1 |     1
+0 1 |  0 |   1 |  1  0 |    0 |      0 |     1 |     1
+1 0 |  0 |   1 |  0  1 |    0 |      0 |     1 |     1
+1 1 |  1 |   1 |  0  0 |    0 |      0 |     0 |     0