From 8eaa07ffd6e2a70b0a3921978215fa4b25400268 Mon Sep 17 00:00:00 2001
From: juicyslew <william.derksen@students.olin.edu>
Date: Thu, 21 Sep 2017 23:31:00 -0400
Subject: [PATCH] The sweet release of finished homework

---
 Adder.pdf       | Bin 0 -> 4034 bytes
 Decoder.pdf     | Bin 0 -> 4351 bytes
 Multiplexer.pdf | Bin 0 -> 4592 bytes
 Output.pdf      | Bin 0 -> 27064 bytes
 TurnInDoc.pdf   | Bin 0 -> 34346 bytes
 adder           | 154 ++++++++++++++++++++++++++++++++++
 adder.t.v       |  31 ++++++-
 adder.v         |  36 ++++++--
 adder.vcd       |  70 ++++++++++++++++
 decoder         | 168 +++++++++++++++++++++++++++++++++++++
 decoder.t.v     |  22 ++---
 decoder.v       |  22 ++++-
 decoder.vcd     |  83 +++++++++++++++++++
 multiplexer     | 216 ++++++++++++++++++++++++++++++++++++++++++++++++
 multiplexer.t.v |  42 +++++++++-
 multiplexer.v   |  24 +++++-
 multiplexer.vcd |  87 +++++++++++++++++++
 17 files changed, 927 insertions(+), 28 deletions(-)
 create mode 100644 Adder.pdf
 create mode 100644 Decoder.pdf
 create mode 100644 Multiplexer.pdf
 create mode 100644 Output.pdf
 create mode 100644 TurnInDoc.pdf
 create mode 100755 adder
 create mode 100644 adder.vcd
 create mode 100755 decoder
 create mode 100644 decoder.vcd
 create mode 100755 multiplexer
 create mode 100644 multiplexer.vcd

diff --git a/Adder.pdf b/Adder.pdf
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literal 0
HcmV?d00001

diff --git a/adder b/adder
new file mode 100755
index 0000000..a2a1257
--- /dev/null
+++ b/adder
@@ -0,0 +1,154 @@
+#! /usr/local/bin/vvp
+:ivl_version "11.0 (devel)" "(s20150603-477-gc855b89)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 12;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "vhdl_textio";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x1c63890 .scope module, "behavioralFullAdder" "behavioralFullAdder" 2 9;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "sum"
+    .port_info 1 /OUTPUT 1 "carryout"
+    .port_info 2 /INPUT 1 "a"
+    .port_info 3 /INPUT 1 "b"
+    .port_info 4 /INPUT 1 "carryin"
+L_0x7f87581bf060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x1c6e660_0 .net *"_s10", 0 0, L_0x7f87581bf060;  1 drivers
+v0x1c97040_0 .net *"_s11", 1 0, L_0x1c98f40;  1 drivers
+v0x1c97120_0 .net *"_s13", 1 0, L_0x1c990f0;  1 drivers
+L_0x7f87581bf0a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x1c97210_0 .net *"_s16", 0 0, L_0x7f87581bf0a8;  1 drivers
+v0x1c972f0_0 .net *"_s17", 1 0, L_0x1c99250;  1 drivers
+v0x1c97420_0 .net *"_s3", 1 0, L_0x1c98c70;  1 drivers
+L_0x7f87581bf018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x1c97500_0 .net *"_s6", 0 0, L_0x7f87581bf018;  1 drivers
+v0x1c975e0_0 .net *"_s7", 1 0, L_0x1c98dc0;  1 drivers
+o0x7f8758225198 .functor BUFZ 1, C4<z>; HiZ drive
+v0x1c976c0_0 .net "a", 0 0, o0x7f8758225198;  0 drivers
+o0x7f87582251c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0x1c97810_0 .net "b", 0 0, o0x7f87582251c8;  0 drivers
+o0x7f87582251f8 .functor BUFZ 1, C4<z>; HiZ drive
+v0x1c978d0_0 .net "carryin", 0 0, o0x7f87582251f8;  0 drivers
+v0x1c97990_0 .net "carryout", 0 0, L_0x1c98a50;  1 drivers
+v0x1c97a50_0 .net "sum", 0 0, L_0x1c98b50;  1 drivers
+L_0x1c98a50 .part L_0x1c99250, 1, 1;
+L_0x1c98b50 .part L_0x1c99250, 0, 1;
+L_0x1c98c70 .concat [ 1 1 0 0], o0x7f8758225198, L_0x7f87581bf018;
+L_0x1c98dc0 .concat [ 1 1 0 0], o0x7f87582251c8, L_0x7f87581bf060;
+L_0x1c98f40 .arith/sum 2, L_0x1c98c70, L_0x1c98dc0;
+L_0x1c990f0 .concat [ 1 1 0 0], o0x7f87582251f8, L_0x7f87581bf0a8;
+L_0x1c99250 .arith/sum 2, L_0x1c98f40, L_0x1c990f0;
+S_0x1c63aa0 .scope module, "testFullAdder" "testFullAdder" 3 5;
+ .timescale -9 -12;
+v0x1c98650_0 .var "a", 0 0;
+v0x1c98710_0 .var "b", 0 0;
+v0x1c987e0_0 .var "carryin", 0 0;
+v0x1c988e0_0 .net "carryout", 0 0, L_0x1c996f0;  1 drivers
+v0x1c989b0_0 .net "sum", 0 0, L_0x1c99ae0;  1 drivers
+S_0x1c97bb0 .scope module, "adder" "structuralFullAdder" 3 10, 2 23 0, S_0x1c63aa0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "sum"
+    .port_info 1 /OUTPUT 1 "cout"
+    .port_info 2 /INPUT 1 "a"
+    .port_info 3 /INPUT 1 "b"
+    .port_info 4 /INPUT 1 "cin"
+L_0x1c98fe0/d .functor AND 1, v0x1c98650_0, v0x1c98710_0, C4<1>, C4<1>;
+L_0x1c98fe0 .delay 1 (50000,50000,50000) L_0x1c98fe0/d;
+L_0x1c99480/d .functor OR 1, v0x1c98650_0, v0x1c98710_0, C4<0>, C4<0>;
+L_0x1c99480 .delay 1 (50000,50000,50000) L_0x1c99480/d;
+L_0x1c995e0/d .functor AND 1, v0x1c987e0_0, L_0x1c99480, C4<1>, C4<1>;
+L_0x1c995e0 .delay 1 (50000,50000,50000) L_0x1c995e0/d;
+L_0x1c996f0/d .functor OR 1, L_0x1c995e0, L_0x1c98fe0, C4<0>, C4<0>;
+L_0x1c996f0 .delay 1 (50000,50000,50000) L_0x1c996f0/d;
+L_0x1c998f0/d .functor XOR 1, v0x1c98650_0, v0x1c98710_0, C4<0>, C4<0>;
+L_0x1c998f0 .delay 1 (50000,50000,50000) L_0x1c998f0/d;
+L_0x1c99ae0/d .functor XOR 1, v0x1c987e0_0, L_0x1c998f0, C4<0>, C4<0>;
+L_0x1c99ae0 .delay 1 (50000,50000,50000) L_0x1c99ae0/d;
+v0x1c97de0_0 .net "a", 0 0, v0x1c98650_0;  1 drivers
+v0x1c97ec0_0 .net "aOb", 0 0, L_0x1c99480;  1 drivers
+v0x1c97f80_0 .net "ab", 0 0, L_0x1c98fe0;  1 drivers
+v0x1c98050_0 .net "axb", 0 0, L_0x1c998f0;  1 drivers
+v0x1c98110_0 .net "b", 0 0, v0x1c98710_0;  1 drivers
+v0x1c98220_0 .net "cin", 0 0, v0x1c987e0_0;  1 drivers
+v0x1c982e0_0 .net "cin_aOb", 0 0, L_0x1c995e0;  1 drivers
+v0x1c983a0_0 .net "cout", 0 0, L_0x1c996f0;  alias, 1 drivers
+v0x1c98460_0 .net "sum", 0 0, L_0x1c99ae0;  alias, 1 drivers
+    .scope S_0x1c63aa0;
+T_0 ;
+    %vpi_call 3 13 "$dumpfile", "adder.vcd" {0 0 0};
+    %vpi_call 3 14 "$dumpvars", 32'sb00000000000000000000000000000000, v0x1c98650_0, v0x1c98710_0, v0x1c987e0_0, v0x1c988e0_0, v0x1c989b0_0 {0 0 0};
+    %vpi_call 3 15 "$display", " A  B  Cin |  S Cout " {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1c98650_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1c98710_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1c987e0_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 18 "$display", " %b  %b    %b |  %b    %b ", v0x1c98650_0, v0x1c98710_0, v0x1c987e0_0, v0x1c989b0_0, v0x1c988e0_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1c98650_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1c98710_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1c987e0_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 21 "$display", " %b  %b    %b |  %b    %b ", v0x1c98650_0, v0x1c98710_0, v0x1c987e0_0, v0x1c989b0_0, v0x1c988e0_0 {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1c98650_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1c98710_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1c987e0_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 24 "$display", " %b  %b    %b |  %b    %b ", v0x1c98650_0, v0x1c98710_0, v0x1c987e0_0, v0x1c989b0_0, v0x1c988e0_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1c98650_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1c98710_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1c987e0_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 27 "$display", " %b  %b    %b |  %b    %b ", v0x1c98650_0, v0x1c98710_0, v0x1c987e0_0, v0x1c989b0_0, v0x1c988e0_0 {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1c98650_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1c98710_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1c987e0_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 30 "$display", " %b  %b    %b |  %b    %b ", v0x1c98650_0, v0x1c98710_0, v0x1c987e0_0, v0x1c989b0_0, v0x1c988e0_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1c98650_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1c98710_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1c987e0_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 33 "$display", " %b  %b    %b |  %b    %b ", v0x1c98650_0, v0x1c98710_0, v0x1c987e0_0, v0x1c989b0_0, v0x1c988e0_0 {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1c98650_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1c98710_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1c987e0_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 36 "$display", " %b  %b    %b |  %b    %b ", v0x1c98650_0, v0x1c98710_0, v0x1c987e0_0, v0x1c989b0_0, v0x1c988e0_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1c98650_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1c98710_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1c987e0_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 39 "$display", " %b  %b    %b |  %b    %b ", v0x1c98650_0, v0x1c98710_0, v0x1c987e0_0, v0x1c989b0_0, v0x1c988e0_0 {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "./adder.v";
+    "adder.t.v";
diff --git a/adder.t.v b/adder.t.v
index 76109ed..7f36e1f 100644
--- a/adder.t.v
+++ b/adder.t.v
@@ -6,9 +6,36 @@ module testFullAdder();
     reg a, b, carryin;
     wire sum, carryout;
 
-    behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    //behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    structuralFullAdder adder (sum, carryout, a, b, carryin);
 
     initial begin
-        // Your test code here
+    $dumpfile("adder.vcd");
+    $dumpvars(0, a, b, carryin, carryout, sum);
+    $display(" A  B  Cin |  S Cout ");
+    a = 0; b = 0; carryin = 0;
+    #1000
+    $display(" %b  %b    %b |  %b    %b ", a, b, carryin, sum, carryout);
+    a = 1; b = 0; carryin = 0;
+    #1000
+    $display(" %b  %b    %b |  %b    %b ", a, b, carryin, sum, carryout);
+    a = 0; b = 1; carryin = 0;
+    #1000
+    $display(" %b  %b    %b |  %b    %b ", a, b, carryin, sum, carryout);
+    a = 1; b = 1; carryin = 0;
+    #1000
+    $display(" %b  %b    %b |  %b    %b ", a, b, carryin, sum, carryout);
+    a = 0; b = 0; carryin = 1;
+    #1000
+    $display(" %b  %b    %b |  %b    %b ", a, b, carryin, sum, carryout);
+    a = 1; b = 0; carryin = 1;
+    #1000
+    $display(" %b  %b    %b |  %b    %b ", a, b, carryin, sum, carryout);
+    a = 0; b = 1; carryin = 1;
+    #1000
+    $display(" %b  %b    %b |  %b    %b ", a, b, carryin, sum, carryout);
+    a = 1; b = 1; carryin = 1;
+    #1000
+    $display(" %b  %b    %b |  %b    %b ", a, b, carryin, sum, carryout);
     end
 endmodule
diff --git a/adder.v b/adder.v
index d21f7e4..0728f9c 100644
--- a/adder.v
+++ b/adder.v
@@ -1,24 +1,42 @@
 // Adder circuit
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+`define NAND nand #50
+`define NOR nor #50
+`define XOR xor #50
 
 module behavioralFullAdder
 (
-    output sum, 
+    output sum,
     output carryout,
-    input a, 
-    input b, 
+    input a,
+    input b,
     input carryin
 );
     // Uses concatenation operator and built-in '+'
     assign {carryout, sum}=a+b+carryin;
 endmodule
 
+
+
 module structuralFullAdder
 (
-    output sum, 
-    output carryout,
-    input a, 
-    input b, 
-    input carryin
+    output sum,
+    output cout,
+    input a,
+    input b,
+    input cin
 );
-    // Your adder code here
+
+    wire axb, ab, aorb, cin_aOb;
+    //cin
+    `AND cand0(ab, a, b);
+    `OR cor0(aOb, a, b);
+    `AND cand1(cin_aOb, cin, aOb);
+    `OR cor1(cout, cin_aOb, ab);
+
+    //s
+    `XOR sxor0(axb, a, b);
+    `XOR sxor1(sum, cin, axb);
 endmodule
diff --git a/adder.vcd b/adder.vcd
new file mode 100644
index 0000000..bd0d83e
--- /dev/null
+++ b/adder.vcd
@@ -0,0 +1,70 @@
+$date
+	Thu Sep 21 23:09:26 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module testFullAdder $end
+$var reg 1 ! a $end
+$upscope $end
+$scope module testFullAdder $end
+$var reg 1 " b $end
+$upscope $end
+$scope module testFullAdder $end
+$var reg 1 # carryin $end
+$upscope $end
+$scope module testFullAdder $end
+$var wire 1 $ carryout $end
+$upscope $end
+$scope module testFullAdder $end
+$var wire 1 % sum $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+x%
+x$
+0#
+0"
+0!
+$end
+#100000
+0%
+0$
+#1000000
+1!
+#1100000
+1%
+#2000000
+1"
+0!
+#3000000
+1!
+#3100000
+1$
+0%
+#4000000
+1#
+0"
+0!
+#4050000
+1%
+#4150000
+0$
+#5000000
+1!
+#5100000
+0%
+#5150000
+1$
+#6000000
+1"
+0!
+#7000000
+1!
+#7100000
+1%
+#8000000
diff --git a/decoder b/decoder
new file mode 100755
index 0000000..e30ef59
--- /dev/null
+++ b/decoder
@@ -0,0 +1,168 @@
+#! /usr/local/bin/vvp
+:ivl_version "11.0 (devel)" "(s20150603-477-gc855b89)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 12;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "vhdl_textio";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0xacbe60 .scope module, "behavioralDecoder" "behavioralDecoder" 2 8;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "out0"
+    .port_info 1 /OUTPUT 1 "out1"
+    .port_info 2 /OUTPUT 1 "out2"
+    .port_info 3 /OUTPUT 1 "out3"
+    .port_info 4 /INPUT 1 "address0"
+    .port_info 5 /INPUT 1 "address1"
+    .port_info 6 /INPUT 1 "enable"
+v0xacfbf0_0 .net *"_s11", 3 0, L_0xb05c80;  1 drivers
+v0xb03870_0 .net *"_s5", 3 0, L_0xb05a70;  1 drivers
+L_0x7f73a8d15018 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>;
+v0xb03950_0 .net *"_s8", 2 0, L_0x7f73a8d15018;  1 drivers
+v0xb03a40_0 .net *"_s9", 1 0, L_0xb05ba0;  1 drivers
+o0x7f73a8d7b0d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0xb03b20_0 .net "address0", 0 0, o0x7f73a8d7b0d8;  0 drivers
+o0x7f73a8d7b108 .functor BUFZ 1, C4<z>; HiZ drive
+v0xb03c30_0 .net "address1", 0 0, o0x7f73a8d7b108;  0 drivers
+o0x7f73a8d7b138 .functor BUFZ 1, C4<z>; HiZ drive
+v0xb03cf0_0 .net "enable", 0 0, o0x7f73a8d7b138;  0 drivers
+v0xb03db0_0 .net "out0", 0 0, L_0xb058e0;  1 drivers
+v0xb03e70_0 .net "out1", 0 0, L_0xb05840;  1 drivers
+v0xb03fc0_0 .net "out2", 0 0, L_0xb05720;  1 drivers
+v0xb04080_0 .net "out3", 0 0, L_0xb05620;  1 drivers
+L_0xb05620 .part L_0xb05c80, 3, 1;
+L_0xb05720 .part L_0xb05c80, 2, 1;
+L_0xb05840 .part L_0xb05c80, 1, 1;
+L_0xb058e0 .part L_0xb05c80, 0, 1;
+L_0xb05a70 .concat [ 1 3 0 0], o0x7f73a8d7b138, L_0x7f73a8d15018;
+L_0xb05ba0 .concat [ 1 1 0 0], o0x7f73a8d7b0d8, o0x7f73a8d7b108;
+L_0xb05c80 .shift/l 4, L_0xb05a70, L_0xb05ba0;
+S_0xacc0a0 .scope module, "testDecoder" "testDecoder" 3 5;
+ .timescale -9 -12;
+v0xb05080_0 .var "addr0", 0 0;
+v0xb05140_0 .var "addr1", 0 0;
+v0xb05210_0 .var "enable", 0 0;
+v0xb05310_0 .net "out0", 0 0, L_0xb06630;  1 drivers
+v0xb053e0_0 .net "out1", 0 0, L_0xb067e0;  1 drivers
+v0xb05480_0 .net "out2", 0 0, L_0xb069e0;  1 drivers
+v0xb05550_0 .net "out3", 0 0, L_0xb06bd0;  1 drivers
+S_0xb04260 .scope module, "decoder" "structuralDecoder" 3 11, 2 19 0, S_0xacc0a0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "out0"
+    .port_info 1 /OUTPUT 1 "out1"
+    .port_info 2 /OUTPUT 1 "out2"
+    .port_info 3 /OUTPUT 1 "out3"
+    .port_info 4 /INPUT 1 "in0"
+    .port_info 5 /INPUT 1 "in1"
+    .port_info 6 /INPUT 1 "enable"
+L_0xb05dc0/d .functor NOT 1, v0xb05080_0, C4<0>, C4<0>, C4<0>;
+L_0xb05dc0 .delay 1 (50000,50000,50000) L_0xb05dc0/d;
+L_0xb05ed0/d .functor NOT 1, v0xb05140_0, C4<0>, C4<0>, C4<0>;
+L_0xb05ed0 .delay 1 (50000,50000,50000) L_0xb05ed0/d;
+L_0xb06030/d .functor AND 1, L_0xb05dc0, L_0xb05ed0, C4<1>, C4<1>;
+L_0xb06030 .delay 1 (50000,50000,50000) L_0xb06030/d;
+L_0xb061e0/d .functor AND 1, L_0xb05ed0, v0xb05080_0, C4<1>, C4<1>;
+L_0xb061e0 .delay 1 (50000,50000,50000) L_0xb061e0/d;
+L_0xb06340/d .functor AND 1, L_0xb05dc0, v0xb05140_0, C4<1>, C4<1>;
+L_0xb06340 .delay 1 (50000,50000,50000) L_0xb06340/d;
+L_0xb06400/d .functor AND 1, v0xb05080_0, v0xb05140_0, C4<1>, C4<1>;
+L_0xb06400 .delay 1 (50000,50000,50000) L_0xb06400/d;
+L_0xb06630/d .functor AND 1, L_0xb06030, v0xb05210_0, C4<1>, C4<1>;
+L_0xb06630 .delay 1 (50000,50000,50000) L_0xb06630/d;
+L_0xb067e0/d .functor AND 1, L_0xb061e0, v0xb05210_0, C4<1>, C4<1>;
+L_0xb067e0 .delay 1 (50000,50000,50000) L_0xb067e0/d;
+L_0xb069e0/d .functor AND 1, L_0xb06340, v0xb05210_0, C4<1>, C4<1>;
+L_0xb069e0 .delay 1 (50000,50000,50000) L_0xb069e0/d;
+L_0xb06bd0/d .functor AND 1, L_0xb06400, v0xb05210_0, C4<1>, C4<1>;
+L_0xb06bd0 .delay 1 (50000,50000,50000) L_0xb06bd0/d;
+v0xb044c0_0 .net "enable", 0 0, v0xb05210_0;  1 drivers
+v0xb045a0_0 .net "in0", 0 0, v0xb05080_0;  1 drivers
+v0xb04660_0 .net "in1", 0 0, v0xb05140_0;  1 drivers
+v0xb04700_0 .net "nin0", 0 0, L_0xb05dc0;  1 drivers
+v0xb047c0_0 .net "nin1", 0 0, L_0xb05ed0;  1 drivers
+v0xb048d0_0 .net "out0", 0 0, L_0xb06630;  alias, 1 drivers
+v0xb04990_0 .net "out1", 0 0, L_0xb067e0;  alias, 1 drivers
+v0xb04a50_0 .net "out2", 0 0, L_0xb069e0;  alias, 1 drivers
+v0xb04b10_0 .net "out3", 0 0, L_0xb06bd0;  alias, 1 drivers
+v0xb04c60_0 .net "preout0", 0 0, L_0xb06030;  1 drivers
+v0xb04d20_0 .net "preout1", 0 0, L_0xb061e0;  1 drivers
+v0xb04de0_0 .net "preout2", 0 0, L_0xb06340;  1 drivers
+v0xb04ea0_0 .net "preout3", 0 0, L_0xb06400;  1 drivers
+    .scope S_0xacc0a0;
+T_0 ;
+    %vpi_call 3 14 "$dumpfile", "decoder.vcd" {0 0 0};
+    %vpi_call 3 15 "$dumpvars", 32'sb00000000000000000000000000000000, v0xb05080_0, v0xb05140_0, v0xb05210_0, v0xb05310_0, v0xb053e0_0, v0xb05480_0, v0xb05550_0 {0 0 0};
+    %vpi_call 3 16 "$display", "En A0 A1| O0 O1 O2 O3 | Expected Output" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xb05210_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xb05080_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xb05140_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 18 "$display", "%b  %b  %b |  %b  %b  %b  %b | All false", v0xb05210_0, v0xb05080_0, v0xb05140_0, v0xb05310_0, v0xb053e0_0, v0xb05480_0, v0xb05550_0 {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xb05210_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xb05080_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xb05140_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 20 "$display", "%b  %b  %b |  %b  %b  %b  %b | All false", v0xb05210_0, v0xb05080_0, v0xb05140_0, v0xb05310_0, v0xb053e0_0, v0xb05480_0, v0xb05550_0 {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xb05210_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xb05080_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xb05140_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 22 "$display", "%b  %b  %b |  %b  %b  %b  %b | All false", v0xb05210_0, v0xb05080_0, v0xb05140_0, v0xb05310_0, v0xb053e0_0, v0xb05480_0, v0xb05550_0 {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xb05210_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xb05080_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xb05140_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 24 "$display", "%b  %b  %b |  %b  %b  %b  %b | All false", v0xb05210_0, v0xb05080_0, v0xb05140_0, v0xb05310_0, v0xb053e0_0, v0xb05480_0, v0xb05550_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xb05210_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xb05080_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xb05140_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 26 "$display", "%b  %b  %b |  %b  %b  %b  %b | O0 Only", v0xb05210_0, v0xb05080_0, v0xb05140_0, v0xb05310_0, v0xb053e0_0, v0xb05480_0, v0xb05550_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xb05210_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xb05080_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xb05140_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 28 "$display", "%b  %b  %b |  %b  %b  %b  %b | O1 Only", v0xb05210_0, v0xb05080_0, v0xb05140_0, v0xb05310_0, v0xb053e0_0, v0xb05480_0, v0xb05550_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xb05210_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xb05080_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xb05140_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 30 "$display", "%b  %b  %b |  %b  %b  %b  %b | O2 Only", v0xb05210_0, v0xb05080_0, v0xb05140_0, v0xb05310_0, v0xb053e0_0, v0xb05480_0, v0xb05550_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xb05210_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xb05080_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xb05140_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 32 "$display", "%b  %b  %b |  %b  %b  %b  %b | O3 Only", v0xb05210_0, v0xb05080_0, v0xb05140_0, v0xb05310_0, v0xb053e0_0, v0xb05480_0, v0xb05550_0 {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "./decoder.v";
+    "decoder.t.v";
diff --git a/decoder.t.v b/decoder.t.v
index e0e925f..da54ec5 100644
--- a/decoder.t.v
+++ b/decoder.t.v
@@ -2,31 +2,33 @@
 `timescale 1 ns / 1 ps
 `include "decoder.v"
 
-module testDecoder (); 
+module testDecoder ();
     reg addr0, addr1;
     reg enable;
     wire out0,out1,out2,out3;
 
-    behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
-    //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
+    //behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
+    structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
 
     initial begin
+    $dumpfile("decoder.vcd");
+    $dumpvars(0, addr0, addr1, enable, out0, out1, out2, out3);
     $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
-    enable=0;addr0=0;addr1=0; #1000 
+    enable=0;addr0=0;addr1=0; #1000
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
     enable=0;addr0=1;addr1=0; #1000
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=0;addr0=0;addr1=1; #1000 
+    enable=0;addr0=0;addr1=1; #1000
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=0;addr0=1;addr1=1; #1000 
+    enable=0;addr0=1;addr1=1; #1000
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=0;addr1=0; #1000 
+    enable=1;addr0=0;addr1=0; #1000
     $display("%b  %b  %b |  %b  %b  %b  %b | O0 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=1;addr1=0; #1000 
+    enable=1;addr0=1;addr1=0; #1000
     $display("%b  %b  %b |  %b  %b  %b  %b | O1 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=0;addr1=1; #1000 
+    enable=1;addr0=0;addr1=1; #1000
     $display("%b  %b  %b |  %b  %b  %b  %b | O2 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=1;addr1=1; #1000 
+    enable=1;addr0=1;addr1=1; #1000
     $display("%b  %b  %b |  %b  %b  %b  %b | O3 Only", enable, addr0, addr1, out0, out1, out2, out3);
     end
 
diff --git a/decoder.v b/decoder.v
index 17836e0..54f5c11 100644
--- a/decoder.v
+++ b/decoder.v
@@ -1,5 +1,10 @@
 // Decoder circuit
-
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+`define NAND nand #50
+`define NOR nor #50
+`define XOR xor #50
 module behavioralDecoder
 (
     output out0, out1, out2, out3,
@@ -14,9 +19,18 @@ endmodule
 module structuralDecoder
 (
     output out0, out1, out2, out3,
-    input address0, address1,
+    input in0, in1,
     input enable
 );
-    // Your decoder code here
+  wire in0, in1;
+  `NOT Nin0(nin0, in0);
+  `NOT Nin1(nin1, in1);
+  `AND preo0(preout0, nin0, nin1);
+  `AND preo1(preout1, nin1, in0);
+  `AND preo2(preout2, nin0, in1);
+  `AND preo3(preout3, in0, in1);
+  `AND o0(out0, preout0, enable);
+  `AND o1(out1, preout1, enable);
+  `AND o2(out2, preout2, enable);
+  `AND o3(out3, preout3, enable);
 endmodule
-
diff --git a/decoder.vcd b/decoder.vcd
new file mode 100644
index 0000000..a39597b
--- /dev/null
+++ b/decoder.vcd
@@ -0,0 +1,83 @@
+$date
+	Thu Sep 21 23:09:14 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module testDecoder $end
+$var reg 1 ! addr0 $end
+$upscope $end
+$scope module testDecoder $end
+$var reg 1 " addr1 $end
+$upscope $end
+$scope module testDecoder $end
+$var reg 1 # enable $end
+$upscope $end
+$scope module testDecoder $end
+$var wire 1 $ out0 $end
+$upscope $end
+$scope module testDecoder $end
+$var wire 1 % out1 $end
+$upscope $end
+$scope module testDecoder $end
+$var wire 1 & out2 $end
+$upscope $end
+$scope module testDecoder $end
+$var wire 1 ' out3 $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+x'
+x&
+x%
+x$
+0#
+0"
+0!
+$end
+#50000
+0'
+0&
+0%
+0$
+#1000000
+1!
+#2000000
+1"
+0!
+#3000000
+1!
+#4000000
+0"
+0!
+1#
+#4050000
+1'
+#4100000
+0'
+#4150000
+1$
+#5000000
+1!
+#5100000
+1%
+#5150000
+0$
+#6000000
+1"
+0!
+#6100000
+0%
+#6150000
+1&
+#7000000
+1!
+#7100000
+1'
+#7150000
+0&
+#8000000
diff --git a/multiplexer b/multiplexer
new file mode 100755
index 0000000..d229025
--- /dev/null
+++ b/multiplexer
@@ -0,0 +1,216 @@
+#! /usr/local/bin/vvp
+:ivl_version "11.0 (devel)" "(s20150603-477-gc855b89)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 12;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "vhdl_textio";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x1c7b8a0 .scope module, "behavioralMultiplexer" "behavioralMultiplexer" 2 9;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "out"
+    .port_info 1 /INPUT 1 "address0"
+    .port_info 2 /INPUT 1 "address1"
+    .port_info 3 /INPUT 1 "in0"
+    .port_info 4 /INPUT 1 "in1"
+    .port_info 5 /INPUT 1 "in2"
+    .port_info 6 /INPUT 1 "in3"
+v0x1c8ed90_0 .net "address", 1 0, L_0x1cba7b0;  1 drivers
+o0x7f6fc1491048 .functor BUFZ 1, C4<z>; HiZ drive
+v0x1cb7350_0 .net "address0", 0 0, o0x7f6fc1491048;  0 drivers
+o0x7f6fc1491078 .functor BUFZ 1, C4<z>; HiZ drive
+v0x1cb7410_0 .net "address1", 0 0, o0x7f6fc1491078;  0 drivers
+o0x7f6fc14910a8 .functor BUFZ 1, C4<z>; HiZ drive
+v0x1cb74e0_0 .net "in0", 0 0, o0x7f6fc14910a8;  0 drivers
+o0x7f6fc14910d8 .functor BUFZ 1, C4<z>; HiZ drive
+v0x1cb75a0_0 .net "in1", 0 0, o0x7f6fc14910d8;  0 drivers
+o0x7f6fc1491108 .functor BUFZ 1, C4<z>; HiZ drive
+v0x1cb76b0_0 .net "in2", 0 0, o0x7f6fc1491108;  0 drivers
+o0x7f6fc1491138 .functor BUFZ 1, C4<z>; HiZ drive
+v0x1cb7770_0 .net "in3", 0 0, o0x7f6fc1491138;  0 drivers
+v0x1cb7830_0 .net "inputs", 3 0, L_0x1cba710;  1 drivers
+v0x1cb7910_0 .net "out", 0 0, L_0x1cba8b0;  1 drivers
+L_0x1cba710 .concat [ 1 1 1 1], o0x7f6fc14910a8, o0x7f6fc14910d8, o0x7f6fc1491108, o0x7f6fc1491138;
+L_0x1cba7b0 .concat [ 1 1 0 0], o0x7f6fc1491048, o0x7f6fc1491078;
+L_0x1cba8b0 .part/v L_0x1cba710, L_0x1cba7b0, 1;
+S_0x1c7bae0 .scope module, "testMultiplexer" "testMultiplexer" 3 5;
+ .timescale -9 -12;
+v0x1cba010_0 .var "addr0", 0 0;
+v0x1cba0b0_0 .var "addr1", 0 0;
+v0x1cba170_0 .var "in0", 0 0;
+v0x1cba260_0 .var "in1", 0 0;
+v0x1cba350_0 .var "in2", 0 0;
+v0x1cba490_0 .var "in3", 0 0;
+v0x1cba580_0 .var "na", 0 0;
+v0x1cba620_0 .net "out", 0 0, L_0x1cbb9b0;  1 drivers
+S_0x1cb7b80 .scope module, "decoder" "structuralMultiplexer" 3 11, 2 34 0, S_0x1c7bae0;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "out"
+    .port_info 1 /INPUT 1 "address0"
+    .port_info 2 /INPUT 1 "address1"
+    .port_info 3 /INPUT 1 "in0"
+    .port_info 4 /INPUT 1 "in1"
+    .port_info 5 /INPUT 1 "in2"
+    .port_info 6 /INPUT 1 "in3"
+v0x1cb9790_0 .net "address0", 0 0, v0x1cba010_0;  1 drivers
+v0x1cb98a0_0 .net "address1", 0 0, v0x1cba0b0_0;  1 drivers
+v0x1cb9960_0 .net "in0", 0 0, v0x1cba170_0;  1 drivers
+v0x1cb9a30_0 .net "in1", 0 0, v0x1cba260_0;  1 drivers
+v0x1cb9b00_0 .net "in2", 0 0, v0x1cba350_0;  1 drivers
+v0x1cb9bf0_0 .net "in3", 0 0, v0x1cba490_0;  1 drivers
+v0x1cb9cc0_0 .net "mux0", 0 0, L_0x1cbade0;  1 drivers
+v0x1cb9db0_0 .net "mux1", 0 0, L_0x1cbb310;  1 drivers
+v0x1cb9ea0_0 .net "out", 0 0, L_0x1cbb9b0;  alias, 1 drivers
+S_0x1cb7de0 .scope module, "mux_0" "bitMultiplexer" 2 41, 2 21 0, S_0x1cb7b80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "out"
+    .port_info 1 /INPUT 1 "addr"
+    .port_info 2 /INPUT 1 "in0"
+    .port_info 3 /INPUT 1 "in1"
+L_0x1cbaa20/d .functor NOT 1, v0x1cba010_0, C4<0>, C4<0>, C4<0>;
+L_0x1cbaa20 .delay 1 (50000,50000,50000) L_0x1cbaa20/d;
+L_0x1cbab20/d .functor AND 1, v0x1cba170_0, L_0x1cbaa20, C4<1>, C4<1>;
+L_0x1cbab20 .delay 1 (50000,50000,50000) L_0x1cbab20/d;
+L_0x1cbac80/d .functor AND 1, v0x1cba260_0, v0x1cba010_0, C4<1>, C4<1>;
+L_0x1cbac80 .delay 1 (50000,50000,50000) L_0x1cbac80/d;
+L_0x1cbade0/d .functor OR 1, L_0x1cbab20, L_0x1cbac80, C4<0>, C4<0>;
+L_0x1cbade0 .delay 1 (50000,50000,50000) L_0x1cbade0/d;
+v0x1cb8050_0 .net "addr", 0 0, v0x1cba010_0;  alias, 1 drivers
+v0x1cb8130_0 .net "in0", 0 0, v0x1cba170_0;  alias, 1 drivers
+v0x1cb81f0_0 .net "in1", 0 0, v0x1cba260_0;  alias, 1 drivers
+v0x1cb82c0_0 .net "naddr", 0 0, L_0x1cbaa20;  1 drivers
+v0x1cb8380_0 .net "o0", 0 0, L_0x1cbab20;  1 drivers
+v0x1cb8490_0 .net "o1", 0 0, L_0x1cbac80;  1 drivers
+v0x1cb8550_0 .net "out", 0 0, L_0x1cbade0;  alias, 1 drivers
+S_0x1cb8690 .scope module, "mux_1" "bitMultiplexer" 2 42, 2 21 0, S_0x1cb7b80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "out"
+    .port_info 1 /INPUT 1 "addr"
+    .port_info 2 /INPUT 1 "in0"
+    .port_info 3 /INPUT 1 "in1"
+L_0x1cbaf40/d .functor NOT 1, v0x1cba010_0, C4<0>, C4<0>, C4<0>;
+L_0x1cbaf40 .delay 1 (50000,50000,50000) L_0x1cbaf40/d;
+L_0x1cbb0a0/d .functor AND 1, v0x1cba350_0, L_0x1cbaf40, C4<1>, C4<1>;
+L_0x1cbb0a0 .delay 1 (50000,50000,50000) L_0x1cbb0a0/d;
+L_0x1cbb1b0/d .functor AND 1, v0x1cba490_0, v0x1cba010_0, C4<1>, C4<1>;
+L_0x1cbb1b0 .delay 1 (50000,50000,50000) L_0x1cbb1b0/d;
+L_0x1cbb310/d .functor OR 1, L_0x1cbb0a0, L_0x1cbb1b0, C4<0>, C4<0>;
+L_0x1cbb310 .delay 1 (50000,50000,50000) L_0x1cbb310/d;
+v0x1cb8900_0 .net "addr", 0 0, v0x1cba010_0;  alias, 1 drivers
+v0x1cb89d0_0 .net "in0", 0 0, v0x1cba350_0;  alias, 1 drivers
+v0x1cb8a70_0 .net "in1", 0 0, v0x1cba490_0;  alias, 1 drivers
+v0x1cb8b40_0 .net "naddr", 0 0, L_0x1cbaf40;  1 drivers
+v0x1cb8c00_0 .net "o0", 0 0, L_0x1cbb0a0;  1 drivers
+v0x1cb8d10_0 .net "o1", 0 0, L_0x1cbb1b0;  1 drivers
+v0x1cb8dd0_0 .net "out", 0 0, L_0x1cbb310;  alias, 1 drivers
+S_0x1cb8f10 .scope module, "mux_out" "bitMultiplexer" 2 43, 2 21 0, S_0x1cb7b80;
+ .timescale -9 -12;
+    .port_info 0 /OUTPUT 1 "out"
+    .port_info 1 /INPUT 1 "addr"
+    .port_info 2 /INPUT 1 "in0"
+    .port_info 3 /INPUT 1 "in1"
+L_0x1cbb470/d .functor NOT 1, v0x1cba0b0_0, C4<0>, C4<0>, C4<0>;
+L_0x1cbb470 .delay 1 (50000,50000,50000) L_0x1cbb470/d;
+L_0x1cbb5d0/d .functor AND 1, L_0x1cbade0, L_0x1cbb470, C4<1>, C4<1>;
+L_0x1cbb5d0 .delay 1 (50000,50000,50000) L_0x1cbb5d0/d;
+L_0x1cbb7c0/d .functor AND 1, L_0x1cbb310, v0x1cba0b0_0, C4<1>, C4<1>;
+L_0x1cbb7c0 .delay 1 (50000,50000,50000) L_0x1cbb7c0/d;
+L_0x1cbb9b0/d .functor OR 1, L_0x1cbb5d0, L_0x1cbb7c0, C4<0>, C4<0>;
+L_0x1cbb9b0 .delay 1 (50000,50000,50000) L_0x1cbb9b0/d;
+v0x1cb9190_0 .net "addr", 0 0, v0x1cba0b0_0;  alias, 1 drivers
+v0x1cb9250_0 .net "in0", 0 0, L_0x1cbade0;  alias, 1 drivers
+v0x1cb9340_0 .net "in1", 0 0, L_0x1cbb310;  alias, 1 drivers
+v0x1cb9440_0 .net "naddr", 0 0, L_0x1cbb470;  1 drivers
+v0x1cb94e0_0 .net "o0", 0 0, L_0x1cbb5d0;  1 drivers
+v0x1cb95d0_0 .net "o1", 0 0, L_0x1cbb7c0;  1 drivers
+v0x1cb9670_0 .net "out", 0 0, L_0x1cbb9b0;  alias, 1 drivers
+    .scope S_0x1c7bae0;
+T_0 ;
+    %vpi_call 3 14 "$dumpfile", "multiplexer.vcd" {0 0 0};
+    %vpi_call 3 15 "$dumpvars", 32'sb00000000000000000000000000000000, v0x1cba010_0, v0x1cba0b0_0, v0x1cba170_0, v0x1cba260_0, v0x1cba350_0, v0x1cba490_0, v0x1cba620_0 {0 0 0};
+    %vpi_call 3 16 "$display", "A0 A1 | I0 I1 I2 I3 | Out " {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1cba010_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1cba0b0_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 18 "$display", " %b  %b |  %b  %b  %b  %b |   %b ", v0x1cba010_0, v0x1cba0b0_0, v0x1cba170_0, v0x1cba260_0, v0x1cba350_0, v0x1cba490_0, v0x1cba620_0 {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1cba170_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1cba010_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1cba0b0_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 21 "$display", " %b  %b |  %b  %b  %b  %b |   %b ", v0x1cba010_0, v0x1cba0b0_0, v0x1cba170_0, v0x1cba260_0, v0x1cba350_0, v0x1cba490_0, v0x1cba620_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1cba170_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1cba010_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1cba0b0_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 24 "$display", " %b  %b |  %b  %b  %b  %b |   %b ", v0x1cba010_0, v0x1cba0b0_0, v0x1cba170_0, v0x1cba260_0, v0x1cba350_0, v0x1cba490_0, v0x1cba620_0 {0 0 0};
+    %load/vec4 v0x1cba580_0;
+    %store/vec4 v0x1cba170_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1cba260_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1cba010_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1cba0b0_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 28 "$display", " %b  %b |  %b  %b  %b  %b |   %b ", v0x1cba010_0, v0x1cba0b0_0, v0x1cba170_0, v0x1cba260_0, v0x1cba350_0, v0x1cba490_0, v0x1cba620_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1cba260_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1cba010_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1cba0b0_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 31 "$display", " %b  %b |  %b  %b  %b  %b |   %b ", v0x1cba010_0, v0x1cba0b0_0, v0x1cba170_0, v0x1cba260_0, v0x1cba350_0, v0x1cba490_0, v0x1cba620_0 {0 0 0};
+    %load/vec4 v0x1cba580_0;
+    %store/vec4 v0x1cba260_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1cba350_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1cba010_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1cba0b0_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 35 "$display", " %b  %b |  %b  %b  %b  %b |   %b ", v0x1cba010_0, v0x1cba0b0_0, v0x1cba170_0, v0x1cba260_0, v0x1cba350_0, v0x1cba490_0, v0x1cba620_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1cba350_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1cba010_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1cba0b0_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 38 "$display", " %b  %b |  %b  %b  %b  %b |   %b ", v0x1cba010_0, v0x1cba0b0_0, v0x1cba170_0, v0x1cba260_0, v0x1cba350_0, v0x1cba490_0, v0x1cba620_0 {0 0 0};
+    %load/vec4 v0x1cba580_0;
+    %store/vec4 v0x1cba350_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1cba490_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1cba010_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1cba0b0_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 42 "$display", " %b  %b |  %b  %b  %b  %b |   %b ", v0x1cba010_0, v0x1cba0b0_0, v0x1cba170_0, v0x1cba260_0, v0x1cba350_0, v0x1cba490_0, v0x1cba620_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1cba490_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1cba010_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1cba0b0_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 3 45 "$display", " %b  %b |  %b  %b  %b  %b |   %b ", v0x1cba010_0, v0x1cba0b0_0, v0x1cba170_0, v0x1cba260_0, v0x1cba350_0, v0x1cba490_0, v0x1cba620_0 {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "./multiplexer.v";
+    "multiplexer.t.v";
diff --git a/multiplexer.t.v b/multiplexer.t.v
index fd475c4..9dfddb4 100644
--- a/multiplexer.t.v
+++ b/multiplexer.t.v
@@ -3,5 +3,45 @@
 `include "multiplexer.v"
 
 module testMultiplexer ();
-  // Your test code here
+    reg addr0, addr1;
+    reg in0, in1, in2, in3;
+    reg na;
+    wire out;
+    //behavioralMultiplexer decoder (out, addr0, addr1, in0, in1, in2, in3);
+    structuralMultiplexer decoder (out, addr0, addr1, in0, in1, in2, in3); // Swap after testing
+
+    initial begin
+    $dumpfile("multiplexer.vcd");
+    $dumpvars(0, addr0, addr1, in0, in1, in2, in3, out);
+    $display("A0 A1 | I0 I1 I2 I3 | Out ");
+    addr0=0;addr1=0; #1000
+    $display(" %b  %b |  %b  %b  %b  %b |   %b ", addr0, addr1, in0, in1, in2, in3, out);
+    in0 = 0;
+    addr0=0;addr1=0; #1000
+    $display(" %b  %b |  %b  %b  %b  %b |   %b ", addr0, addr1, in0, in1, in2, in3, out);
+    in0 = 1;
+    addr0=0;addr1=0; #1000
+    $display(" %b  %b |  %b  %b  %b  %b |   %b ", addr0, addr1, in0, in1, in2, in3, out);
+    in0 = na;
+    in1 = 0;
+    addr0=1;addr1=0; #1000
+    $display(" %b  %b |  %b  %b  %b  %b |   %b ", addr0, addr1, in0, in1, in2, in3, out);
+    in1 = 1;
+    addr0=1;addr1=0; #1000
+    $display(" %b  %b |  %b  %b  %b  %b |   %b ", addr0, addr1, in0, in1, in2, in3, out);
+    in1 = na;
+    in2 = 0;
+    addr0=0;addr1=1; #1000
+    $display(" %b  %b |  %b  %b  %b  %b |   %b ", addr0, addr1, in0, in1, in2, in3, out);
+    in2 = 1;
+    addr0=0;addr1=1; #1000
+    $display(" %b  %b |  %b  %b  %b  %b |   %b ", addr0, addr1, in0, in1, in2, in3, out);
+    in2 = na;
+    in3 = 0;
+    addr0=1;addr1=1; #1000
+    $display(" %b  %b |  %b  %b  %b  %b |   %b ", addr0, addr1, in0, in1, in2, in3, out);
+    in3 = 1;
+    addr0=1;addr1=1; #1000
+    $display(" %b  %b |  %b  %b  %b  %b |   %b ", addr0, addr1, in0, in1, in2, in3, out);
+    end
 endmodule
diff --git a/multiplexer.v b/multiplexer.v
index b05820f..3556a42 100644
--- a/multiplexer.v
+++ b/multiplexer.v
@@ -1,4 +1,10 @@
 // Multiplexer circuit
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+`define NAND nand #50
+`define NOR nor #50
+`define XOR xor #50
 
 module behavioralMultiplexer
 (
@@ -12,6 +18,18 @@ module behavioralMultiplexer
     assign out = inputs[address];
 endmodule
 
+module bitMultiplexer
+(
+    output out,
+    input addr,
+    input in0, in1
+);
+    wire naddr;
+    `NOT n_addr(naddr, addr);
+    `AND and_0(o0, in0, naddr);
+    `AND and_1(o1, in1, addr);
+    `OR or_out(out, o0, o1);
+endmodule
 
 module structuralMultiplexer
 (
@@ -19,6 +37,8 @@ module structuralMultiplexer
     input address0, address1,
     input in0, in1, in2, in3
 );
-    // Your multiplexer code here
+    wire mux0, mux1;
+    bitMultiplexer mux_0(mux0, address0, in0, in1);
+    bitMultiplexer mux_1(mux1, address0, in2, in3);
+    bitMultiplexer mux_out(out, address1, mux0, mux1);
 endmodule
-
diff --git a/multiplexer.vcd b/multiplexer.vcd
new file mode 100644
index 0000000..d0c79f1
--- /dev/null
+++ b/multiplexer.vcd
@@ -0,0 +1,87 @@
+$date
+	Thu Sep 21 23:09:11 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module testMultiplexer $end
+$var reg 1 ! addr0 $end
+$upscope $end
+$scope module testMultiplexer $end
+$var reg 1 " addr1 $end
+$upscope $end
+$scope module testMultiplexer $end
+$var reg 1 # in0 $end
+$upscope $end
+$scope module testMultiplexer $end
+$var reg 1 $ in1 $end
+$upscope $end
+$scope module testMultiplexer $end
+$var reg 1 % in2 $end
+$upscope $end
+$scope module testMultiplexer $end
+$var reg 1 & in3 $end
+$upscope $end
+$scope module testMultiplexer $end
+$var wire 1 ' out $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+x'
+x&
+x%
+x$
+x#
+0"
+0!
+$end
+#1000000
+0#
+#1200000
+0'
+#2000000
+1#
+#2200000
+1'
+#3000000
+1!
+0$
+x#
+#3200000
+x'
+#3250000
+0'
+#4000000
+1$
+#4200000
+1'
+#5000000
+1"
+0!
+0%
+x$
+#5150000
+x'
+#5200000
+0'
+#6000000
+1%
+#6200000
+1'
+#7000000
+1!
+0&
+x%
+#7200000
+x'
+#7250000
+0'
+#8000000
+1&
+#8200000
+1'
+#9000000