diff --git a/HW2 Write-Up.pdf b/HW2 Write-Up.pdf
new file mode 100644
index 0000000..1e82425
Binary files /dev/null and b/HW2 Write-Up.pdf differ
diff --git a/adder.t.v b/adder.t.v
index 76109ed..6599e36 100644
--- a/adder.t.v
+++ b/adder.t.v
@@ -6,9 +6,31 @@ module testFullAdder();
     reg a, b, carryin;
     wire sum, carryout;
 
-    behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    // behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    structuralFullAdder adder (sum, carryout, a, b, carryin);
 
     initial begin
-        // Your test code here
+        $dumpfile("adder.vcd");
+        $dumpvars(0, a, b, carryin, sum, carryout);
+
+        $display("A B Cin | Sum Cout | Expected Output");
+        a=0; b=0; carryin=0; #1000
+        $display("%b %b  %b  |  %b    %b  |       0 0     ", a, b, carryin, sum, carryout);
+        a=0; b=0; carryin=1; #1000
+        $display("%b %b  %b  |  %b    %b  |       1 0     ", a, b, carryin, sum, carryout);
+        a=0; b=1; carryin=0; #1000
+        $display("%b %b  %b  |  %b    %b  |       1 0     ", a, b, carryin, sum, carryout);
+        a=0; b=1; carryin=1; #1000
+        $display("%b %b  %b  |  %b    %b  |       0 1     ", a, b, carryin, sum, carryout);
+        a=1; b=0; carryin=0; #1000
+        $display("%b %b  %b  |  %b    %b  |       1 0     ", a, b, carryin, sum, carryout);
+        a=1; b=0; carryin=1; #1000
+        $display("%b %b  %b  |  %b    %b  |       0 1     ", a, b, carryin, sum, carryout);
+        a=1; b=1; carryin=0; #1000
+        $display("%b %b  %b  |  %b    %b  |       0 1     ", a, b, carryin, sum, carryout);
+        a=1; b=1; carryin=1; #1000
+        $display("%b %b  %b  |  %b    %b  |       1 1     ", a, b, carryin, sum, carryout);
+
+        $finish();
     end
 endmodule
diff --git a/adder.v b/adder.v
index d21f7e4..f47838f 100644
--- a/adder.v
+++ b/adder.v
@@ -1,11 +1,17 @@
+// define gates with delays
+`define AND and #50
+`define OR or #50
+`define XOR xor #50
+
+
 // Adder circuit
 
 module behavioralFullAdder
 (
-    output sum, 
+    output sum,
     output carryout,
-    input a, 
-    input b, 
+    input a,
+    input b,
     input carryin
 );
     // Uses concatenation operator and built-in '+'
@@ -14,11 +20,17 @@ endmodule
 
 module structuralFullAdder
 (
-    output sum, 
+    output sum,
     output carryout,
-    input a, 
-    input b, 
+    input a,
+    input b,
     input carryin
 );
-    // Your adder code here
+    wire axorb, axorb_Cin, ab;
+
+    `XOR abxorgate (axorb, a, b);
+    `XOR sumxorgate (sum, carryin, axorb);
+    `AND abandgate (ab, a, b);
+    `AND axorbCinandgate (axorb_Cin, axorb, carryin);
+    `OR Coutorgate (carryout, ab, axorb_Cin);
 endmodule
diff --git a/decoder.t.v b/decoder.t.v
index e0e925f..ddafe4f 100644
--- a/decoder.t.v
+++ b/decoder.t.v
@@ -2,32 +2,37 @@
 `timescale 1 ns / 1 ps
 `include "decoder.v"
 
-module testDecoder (); 
+module testDecoder ();
     reg addr0, addr1;
     reg enable;
     wire out0,out1,out2,out3;
 
-    behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
-    //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
+    // behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
+    structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
 
     initial begin
-    $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
-    enable=0;addr0=0;addr1=0; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=0;addr0=1;addr1=0; #1000
-    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=0;addr0=0;addr1=1; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=0;addr0=1;addr1=1; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=0;addr1=0; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | O0 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=1;addr1=0; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | O1 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=0;addr1=1; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | O2 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=1;addr1=1; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | O3 Only", enable, addr0, addr1, out0, out1, out2, out3);
+      $dumpfile("decoder.vcd");
+      $dumpvars(0, addr0, addr1, enable, out0, out1, out2, out3);
+
+      $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
+      enable=0;addr0=0;addr1=0; #1000
+      $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
+      enable=0;addr0=1;addr1=0; #1000
+      $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
+      enable=0;addr0=0;addr1=1; #1000
+      $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
+      enable=0;addr0=1;addr1=1; #1000
+      $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
+      enable=1;addr0=0;addr1=0; #1000
+      $display("%b  %b  %b |  %b  %b  %b  %b | O0 Only", enable, addr0, addr1, out0, out1, out2, out3);
+      enable=1;addr0=1;addr1=0; #1000
+      $display("%b  %b  %b |  %b  %b  %b  %b | O1 Only", enable, addr0, addr1, out0, out1, out2, out3);
+      enable=1;addr0=0;addr1=1; #1000
+      $display("%b  %b  %b |  %b  %b  %b  %b | O2 Only", enable, addr0, addr1, out0, out1, out2, out3);
+      enable=1;addr0=1;addr1=1; #1000
+      $display("%b  %b  %b |  %b  %b  %b  %b | O3 Only", enable, addr0, addr1, out0, out1, out2, out3);
+
+      $finish();
     end
 
 endmodule
diff --git a/decoder.v b/decoder.v
index 17836e0..8d365b4 100644
--- a/decoder.v
+++ b/decoder.v
@@ -1,3 +1,7 @@
+// define gates with delays
+`define AND and #50
+`define NOT not #50
+
 // Decoder circuit
 
 module behavioralDecoder
@@ -17,6 +21,18 @@ module structuralDecoder
     input address0, address1,
     input enable
 );
-    // Your decoder code here
-endmodule
+    wire nadd0, nadd1, add0add1, nadd0nadd1, nadd0add1, add0nadd1;
+
+    `NOT add0inv (nadd0, address0);
+    `NOT add1inv (nadd1, address1);
 
+    `AND nadd0nadd1andgate (nadd0nadd1, nadd0, nadd1);
+    `AND add0nadd1andgate (add0nadd1, address0, nadd1);
+    `AND nadd0add1andgate (nadd0add1, nadd0, address1);
+    `AND add0add1andgate (add0add1, address0, address1);
+
+    `AND Eadd0add1andgate (out0, nadd0nadd1, enable);
+    `AND Enadd0nadd1andgate (out1, add0nadd1, enable);
+    `AND Enadd0add1andgate (out2, nadd0add1, enable);
+    `AND Eadd0nadd1andgate (out3, add0add1, enable);
+endmodule
diff --git a/multiplexer.t.v b/multiplexer.t.v
index fd475c4..cd38c0e 100644
--- a/multiplexer.t.v
+++ b/multiplexer.t.v
@@ -3,5 +3,39 @@
 `include "multiplexer.v"
 
 module testMultiplexer ();
-  // Your test code here
+  wire out;
+  reg address0, address1;
+  reg in0, in1, in2, in3;
+
+  // behavioralMultiplexer mux(out, address0, address1, in0, in1, in2, in3);
+  structuralMultiplexer mux(out, address0, address1, in0, in1, in2, in3);
+
+
+// kind of a random error but I tried to test in a different order and this was the only one that didn't compile in errors - assuming it's due to order of assignments
+
+  initial begin
+    $dumpfile("multiplexer.vcd");
+    $dumpvars(0, address0, address1, in0, in1, in2, in3, out);
+
+    $display("A0 A1 | in0 in1 in2 in3 | Out | Expected Output");
+    address0=0;address1=0;in0=1'b0;in1='bx;in2='bx;in3='bx; #1000
+    $display(" %b  %b |  %b   %b   %b   %b  |  %b  |         0", address0, address1, in0, in1, in2, in3, out);
+    address0=1;address1=0;in0='bx;in1=1'b0;in2='bx;in3='bx; #1000
+    $display(" %b  %b |  %b   %b   %b   %b  |  %b  |         0", address0, address1, in0, in1, in2, in3, out);
+    address0=0;address1=1;in0='bx;in1='bx;in2=1'b0;in3='bx; #1000
+    $display(" %b  %b |  %b   %b   %b   %b  |  %b  |         0", address0, address1, in0, in1, in2, in3, out);
+    address0=1;address1=1;in0='bx;in1='bx;in2='bx;in3=1'b0; #1000
+    $display(" %b  %b |  %b   %b   %b   %b  |  %b  |         0", address0, address1, in0, in1, in2, in3, out);
+    address0=0;address1=0;in0=1'b1;in1=1'bx;in2=1'bx;in3=1'bx; #1000
+    $display(" %b  %b |  %b   %b   %b   %b  |  %b  |         1", address0, address1, in0, in1, in2, in3, out);
+    address0=1;address1=0;in0=1'bx;in1=1'b1;in2=1'bx;in3=1'bx; #1000
+    $display(" %b  %b |  %b   %b   %b   %b  |  %b  |         1", address0, address1, in0, in1, in2, in3, out);
+    address0=0;address1=1;in0=1'bx;in1=1'bx;in2=1'b1;in3=1'bx; #1000
+    $display(" %b  %b |  %b   %b   %b   %b  |  %b  |         1", address0, address1, in0, in1, in2, in3, out);
+    address0=1;address1=1;in0=1'bx;in1=1'bx;in2=1'bx;in3=1'b1; #1000
+    $display(" %b  %b |  %b   %b   %b   %b  |  %b  |         1", address0, address1, in0, in1, in2, in3, out);
+
+    $finish();
+  end
+
 endmodule
diff --git a/multiplexer.v b/multiplexer.v
index b05820f..1e23a2d 100644
--- a/multiplexer.v
+++ b/multiplexer.v
@@ -1,3 +1,8 @@
+// define gates with delays
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+
 // Multiplexer circuit
 
 module behavioralMultiplexer
@@ -19,6 +24,23 @@ module structuralMultiplexer
     input address0, address1,
     input in0, in1, in2, in3
 );
-    // Your multiplexer code here
-endmodule
+    wire nadd0, nadd1, en0, en1, en2, en3, selen0, selen1, selen2, selen3, out0, out1;
+
+    `NOT add0inv (nadd0, address0);
+    `NOT add1inv (nadd1, address1);
+
+    `AND nadd0nadd1 (en0, nadd0, nadd1);
+    `AND add0nadd1 (en1, address0, nadd1);
+    `AND nadd0add1 (en2, nadd0, address1);
+    `AND add0nadd1 (en3, address0, address1);
 
+    `AND selector0 (selen0, en0, in0);
+    `AND selector1 (selen1, en1, in1);
+    `AND selector3 (selen2, en2, in2);
+    `AND selector4 (selen3, en3, in3);
+
+    `OR in0orin1 (out0, selen1, selen2);
+    `OR in2orin3 (out1, selen0, selen3);
+
+    `OR out (out, out0, out1);
+endmodule