diff --git a/adder.t.v b/adder.t.v
index 76109ed..746d141 100644
--- a/adder.t.v
+++ b/adder.t.v
@@ -6,9 +6,29 @@ module testFullAdder();
     reg a, b, carryin;
     wire sum, carryout;
 
-    behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    //behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    structuralFullAdder adder (sum, carryout, a, b, carryin);
 
     initial begin
+        $dumpfile("adder.vcd");
+        $dumpvars(0,testFullAdder);
         // Your test code here
+        $display("a b carryin | sum carryout | expected Output");
+        a=0;b=0;carryin=0; #1000
+        $display("%b %b %b | %b %b | 0 0", a, b, carryin, sum, carryout);
+        a=0;b=1;carryin=0; #1000
+        $display("%b %b %b | %b %b | 1 0", a, b, carryin, sum, carryout);
+        a=1;b=0;carryin=0; #1000
+        $display("%b %b %b | %b %b | 1 0", a, b, carryin, sum, carryout);
+        a=1;b=1;carryin=0; #1000
+        $display("%b %b %b | %b %b | 0 1", a, b, carryin, sum, carryout);
+        a=0;b=0;carryin=1; #1000
+        $display("%b %b %b | %b %b | 1 0", a, b, carryin, sum, carryout);
+        a=0;b=1;carryin=1; #1000
+        $display("%b %b %b | %b %b | 0 1", a, b, carryin, sum, carryout);
+        a=1;b=0;carryin=1; #1000
+        $display("%b %b %b | %b %b | 0 1", a, b, carryin, sum, carryout);
+        a=1;b=1;carryin=1; #1000
+        $display("%b %b %b | %b %b | 1 1", a, b, carryin, sum, carryout);
     end
 endmodule
diff --git a/adder.v b/adder.v
index d21f7e4..1d29263 100644
--- a/adder.v
+++ b/adder.v
@@ -1,4 +1,8 @@
 // Adder circuit
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+`define XOR xor #50
 
 module behavioralFullAdder
 (
@@ -21,4 +25,25 @@ module structuralFullAdder
     input carryin
 );
     // Your adder code here
+    wire axorb;
+    wire nCarryIn;
+    wire notaxorb;
+    wire sumWire0;
+    wire sumWire1;
+    
+    `XOR abxorgate(axorb, a, b);
+    `AND andgate0(sumWire0, axorb, nCarryIn);
+    `NOT invCarryIn(nCarryIn, carryin);
+    `NOT invaxorb(notaxorb, axorb);
+    `AND andgate1(sumWire1, carryin, notaxorb);
+    `OR orgate0(sum, sumWire0, sumWire1);
+
+    wire aandb;
+    wire aorb;
+    wire carryOutWire;
+    
+    `AND abandgate(aandb, a, b);
+    `OR orgate1(aorb, a, b);
+    `AND andgate2(carryOutWire, carryin, aorb);
+    `OR orgate2(carryout, aandb, carryOutWire);
 endmodule
diff --git a/adder_test.png b/adder_test.png
new file mode 100644
index 0000000..aeef3be
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diff --git a/adder_waveform.png b/adder_waveform.png
new file mode 100644
index 0000000..3caa15f
Binary files /dev/null and b/adder_waveform.png differ
diff --git a/decoder.t.v b/decoder.t.v
index e0e925f..fdd52e2 100644
--- a/decoder.t.v
+++ b/decoder.t.v
@@ -7,10 +7,12 @@ module testDecoder ();
     reg enable;
     wire out0,out1,out2,out3;
 
-    behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
-    //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
+    //behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
+    structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
 
     initial begin
+	$dumpfile("decoder.vcd");
+	$dumpvars(0,testDecoder);
     $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
     enable=0;addr0=0;addr1=0; #1000 
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
diff --git a/decoder.v b/decoder.v
index 17836e0..f5ae80a 100644
--- a/decoder.v
+++ b/decoder.v
@@ -1,4 +1,7 @@
 // Decoder circuit
+`define AND and #50
+`define OR or #50
+`define NOT not #50
 
 module behavioralDecoder
 (
@@ -18,5 +21,21 @@ module structuralDecoder
     input enable
 );
     // Your decoder code here
+    wire wire0;
+    wire wire1;
+    wire wire2;
+    wire wire3;
+    wire nA0;
+    wire nA1;
+    `NOT invA0(nA0, address0);
+    `NOT invA1(nA1, address1);
+    `AND and0(wire0, nA0, nA1);
+    `AND and1(wire1, address0, nA1);
+    `AND and2(wire2, nA0, address1);
+    `AND and3(wire3, address0, address1);
+    `AND enableAnd0(out0, enable, wire0);
+    `AND enableAnd1(out1, enable, wire1);
+    `AND enableAnd2(out2, enable, wire2);
+    `AND enableAnd3(out3, enable, wire3);
 endmodule
 
diff --git a/decoder_test.png b/decoder_test.png
new file mode 100644
index 0000000..fd78850
Binary files /dev/null and b/decoder_test.png differ
diff --git a/decoder_waveform.png b/decoder_waveform.png
new file mode 100644
index 0000000..e9573e3
Binary files /dev/null and b/decoder_waveform.png differ
diff --git a/multiplexer.t.v b/multiplexer.t.v
index fd475c4..e72d594 100644
--- a/multiplexer.t.v
+++ b/multiplexer.t.v
@@ -4,4 +4,25 @@
 
 module testMultiplexer ();
   // Your test code here
+    reg addr0, addr1;
+    reg in0, in1, in2, in3;
+    wire out;
+
+    //behavioralMultiplexer multiplexer (out, addr0, addr1, in0, in1, in2, in3);
+    structuralMultiplexer multiplexer (out, addr0, addr1, in0, in1, in2, in3);
+     
+
+    initial begin
+    $dumpfile("multiplexer.vcd");
+    $dumpvars(0,testMultiplexer);
+    $display("A0 A1 I0 I1 I2 I3 | Output | Expected Output");
+    addr0=0;addr1=0;in0=0;in1=1;in2=0;in3=1; #1000
+    $display("%b %b %b %b %b %b | %b | 0", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=1;addr1=0;in0=0;in1=1;in2=0;in3=1; #1000
+    $display("%b %b %b %b %b %b | %b | 1", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=0;addr1=1;in0=0;in1=1;in2=0;in3=1; #1000
+    $display("%b %b %b %b %b %b | %b | 0", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=1;addr1=1;in0=0;in1=1;in2=0;in3=1; #1000
+    $display("%b %b %b %b %b %b | %b | 1", addr0, addr1, in0, in1, in2, in3, out);
+    end
 endmodule
diff --git a/multiplexer.v b/multiplexer.v
index b05820f..80508cd 100644
--- a/multiplexer.v
+++ b/multiplexer.v
@@ -1,5 +1,7 @@
 // Multiplexer circuit
-
+`define AND and #50
+`define OR or #50
+`define NOT not #50
 module behavioralMultiplexer
 (
     output out,
@@ -20,5 +22,32 @@ module structuralMultiplexer
     input in0, in1, in2, in3
 );
     // Your multiplexer code here
+    wire nA0;
+    wire nA1;
+    wire input0Wire0;
+    wire input0Wire1;
+    wire input1Wire0;
+    wire input1Wire1;
+    wire input2Wire0;
+    wire input2Wire1;
+    wire input3Wire0;
+    wire input3Wire1;
+    wire orWire0;
+    wire orWire1;
+
+    `NOT invA0(nA0, address0);
+    `NOT invA1(nA1, address1);
+    `AND input0And0(input0Wire0, nA0, nA1);
+    `AND input0And1(input0Wire1, input0Wire0, in0);
+    `AND input1And0(input1Wire0, address0, nA1);
+    `AND input1And1(input1Wire1, input1Wire0, in1);
+    `AND input2And0(input2Wire0, nA0, address1);
+    `AND input2And1(input2Wire1, input2Wire0, in2);
+    `AND input3And0(input3Wire0, address0, address1);
+    `AND input3And1(input3Wire1, input3Wire0, in3);
+
+    `OR or1(orWire0, input0Wire1, input1Wire1);
+    `OR or2(orWire1, orWire0, input2Wire1);
+    `OR or3(out, orWire1, input3Wire1);
 endmodule
 
diff --git a/multiplexer_test.png b/multiplexer_test.png
new file mode 100644
index 0000000..3d75e13
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diff --git a/multiplexer_waveform.png b/multiplexer_waveform.png
new file mode 100644
index 0000000..c16d173
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diff --git a/writeup.md b/writeup.md
new file mode 100644
index 0000000..603511d
--- /dev/null
+++ b/writeup.md
@@ -0,0 +1,27 @@
+# Test branch results
+
+Decoder
+
+![Decoder test](decoder_test.png)
+
+Multiplexer
+
+![Multiplexer test](multiplexer_test.png)
+
+Adder
+
+![Adder test](adder_test.png)
+
+# Waveforms
+
+Decoder
+
+![Decoder waveform](decoder_waveform.png)
+
+Multiplexer
+
+![Multiplexer waveform](multiplexer_waveform.png)
+
+Adder
+
+![Adder waveform](adder_waveform.png)