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Pre-allocate secure-side context structures
This commit improves ARMv8-M security by pre-allocating secure-side task context structures and changing how tasks reference a secure-side context structure when calling a secure function. The new configuration constant secureconfigMAX_SECURE_CONTEXTS sets the number of secure context structures to pre-allocate. secureconfigMAX_SECURE_CONTEXTS defaults to 8 if left undefined. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
1 parent b97bb48 commit 4209835

27 files changed

+985
-630
lines changed

‎portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c‎

Lines changed: 38 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -36,56 +36,60 @@
3636
#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
3737
#endif
3838

39-
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
39+
void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
4040
{
41-
/* xSecureContextHandle value is in r0. */
41+
/* pxSecureContext value is in r0. */
4242
__asm volatile
4343
(
44-
" .syntax unified \n"
45-
" \n"
46-
" mrs r1, ipsr \n"/* r1 = IPSR. */
47-
" cbz r1, load_ctx_therad_mode \n"/* Do nothing if the processor is running in the Thread Mode. */
48-
" ldmia r0!, {r1, r2} \n"/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
44+
" .syntax unified \n"
45+
" \n"
46+
" mrs r1, ipsr \n" /* r1 = IPSR. */
47+
" cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
48+
" ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
49+
" \n"
4950
#if ( configENABLE_MPU == 1 )
50-
" ldmia r1!, {r3} \n"/* Read CONTROL register value from task's stack. r3 = CONTROL. */
51-
" msr control, r3 \n"/* CONTROL = r3. */
51+
" ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
52+
" msr control, r3 \n" /* CONTROL = r3. */
5253
#endif /* configENABLE_MPU */
53-
" msr psplim, r2 \n"/* PSPLIM = r2. */
54-
" msr psp, r1 \n"/* PSP = r1. */
55-
" \n"
56-
" load_ctx_therad_mode: \n"
57-
" nop \n"
58-
" \n"
54+
" \n"
55+
" msr psplim, r2 \n" /* PSPLIM = r2. */
56+
" msr psp, r1 \n" /* PSP = r1. */
57+
" \n"
58+
" load_ctx_therad_mode: \n"
59+
" bx lr \n"
60+
" \n"
5961
::: "r0", "r1", "r2"
6062
);
6163
}
6264
/*-----------------------------------------------------------*/
6365

64-
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
66+
void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )
6567
{
66-
/* xSecureContextHandle value is in r0. */
68+
/* pxSecureContext value is in r0. */
6769
__asm volatile
6870
(
69-
" .syntax unified \n"
70-
" \n"
71-
" mrs r1, ipsr \n"/* r1 = IPSR. */
72-
" cbz r1, save_ctx_therad_mode \n"/* Do nothing if the processor is running in the Thread Mode. */
73-
" mrs r1, psp \n"/* r1 = PSP. */
71+
" .syntax unified \n"
72+
" \n"
73+
" mrs r1, ipsr \n" /* r1 = IPSR. */
74+
" cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
75+
" mrs r1, psp \n" /* r1 = PSP. */
76+
" \n"
7477
#if ( configENABLE_MPU == 1 )
75-
" mrs r2, control \n"/* r2 = CONTROL. */
76-
" subs r1, r1, #4 \n"/* Make space for the CONTROL value on the stack. */
77-
" str r1, [r0] \n"/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
78-
" stmia r1!, {r2} \n"/* Store CONTROL value on the stack. */
78+
" mrs r2, control \n" /* r2 = CONTROL. */
79+
" subs r1, r1, #4 \n" /* Make space for the CONTROL value on the stack. */
80+
" str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
81+
" stmia r1!, {r2} \n" /* Store CONTROL value on the stack. */
7982
#else /* configENABLE_MPU */
80-
" str r1, [r0] \n"/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
83+
" str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
8184
#endif /* configENABLE_MPU */
82-
" movs r1, %0 \n"/* r1 = securecontextNO_STACK. */
83-
" msr psplim, r1 \n"/* PSPLIM = securecontextNO_STACK. */
84-
" msr psp, r1 \n"/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
85-
" \n"
86-
" save_ctx_therad_mode: \n"
87-
" nop \n"
88-
" \n"
85+
" \n"
86+
" movs r1, %0 \n" /* r1 = securecontextNO_STACK. */
87+
" msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */
88+
" msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
89+
" \n"
90+
" save_ctx_therad_mode: \n"
91+
" bx lr \n"
92+
" \n"
8993
::"i" ( securecontextNO_STACK ) : "r1", "memory"
9094
);
9195
}

‎portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c‎

Lines changed: 39 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -32,57 +32,62 @@
3232
/* Secure port macros. */
3333
#include "secure_port_macros.h"
3434

35-
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
35+
void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
3636
{
37-
/* xSecureContextHandle value is in r0. */
37+
/* pxSecureContext value is in r0. */
3838
__asm volatile
3939
(
40-
" .syntax unified \n"
41-
" \n"
42-
" mrs r1, ipsr \n"/* r1 = IPSR. */
43-
" cbz r1, load_ctx_therad_mode \n"/* Do nothing if the processor is running in the Thread Mode. */
44-
" ldmia r0!, {r1, r2} \n"/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
40+
" .syntax unified \n"
41+
" \n"
42+
" mrs r1, ipsr \n" /* r1 = IPSR. */
43+
" cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
44+
" ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
45+
" \n"
4546
#if ( configENABLE_MPU == 1 )
46-
" ldmia r1!, {r3} \n"/* Read CONTROL register value from task's stack. r3 = CONTROL. */
47-
" msr control, r3 \n"/* CONTROL = r3. */
47+
" ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
48+
" msr control, r3 \n" /* CONTROL = r3. */
4849
#endif /* configENABLE_MPU */
49-
" msr psplim, r2 \n"/* PSPLIM = r2. */
50-
" msr psp, r1 \n"/* PSP = r1. */
51-
" \n"
52-
" load_ctx_therad_mode: \n"
53-
" nop \n"
54-
" \n"
50+
" \n"
51+
" msr psplim, r2 \n" /* PSPLIM = r2. */
52+
" msr psp, r1 \n" /* PSP = r1. */
53+
" \n"
54+
" load_ctx_therad_mode: \n"
55+
" bx lr \n"
56+
" \n"
5557
::: "r0", "r1", "r2"
5658
);
5759
}
5860
/*-----------------------------------------------------------*/
5961

60-
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
62+
void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )
6163
{
62-
/* xSecureContextHandle value is in r0. */
64+
/* pxSecureContext value is in r0. */
6365
__asm volatile
6466
(
65-
" .syntax unified \n"
66-
" \n"
67-
" mrs r1, ipsr \n"/* r1 = IPSR. */
68-
" cbz r1, save_ctx_therad_mode \n"/* Do nothing if the processor is running in the Thread Mode. */
69-
" mrs r1, psp \n"/* r1 = PSP. */
67+
" .syntax unified \n"
68+
" \n"
69+
" mrs r1, ipsr \n" /* r1 = IPSR. */
70+
" cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
71+
" mrs r1, psp \n" /* r1 = PSP. */
72+
" \n"
7073
#if ( configENABLE_FPU == 1 )
71-
" vstmdb r1!, {s0} \n"/* Trigger the defferred stacking of FPU registers. */
72-
" vldmia r1!, {s0} \n"/* Nullify the effect of the pervious statement. */
74+
" vstmdb r1!, {s0} \n" /* Trigger the defferred stacking of FPU registers. */
75+
" vldmia r1!, {s0} \n" /* Nullify the effect of the pervious statement. */
7376
#endif /* configENABLE_FPU */
77+
" \n"
7478
#if ( configENABLE_MPU == 1 )
75-
" mrs r2, control \n"/* r2 = CONTROL. */
76-
" stmdb r1!, {r2} \n"/* Store CONTROL value on the stack. */
79+
" mrs r2, control \n" /* r2 = CONTROL. */
80+
" stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */
7781
#endif /* configENABLE_MPU */
78-
" str r1, [r0] \n"/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
79-
" movs r1, %0 \n"/* r1 = securecontextNO_STACK. */
80-
" msr psplim, r1 \n"/* PSPLIM = securecontextNO_STACK. */
81-
" msr psp, r1 \n"/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
82-
" \n"
83-
" save_ctx_therad_mode: \n"
84-
" nop \n"
85-
" \n"
82+
" \n"
83+
" str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
84+
" movs r1, %0 \n" /* r1 = securecontextNO_STACK. */
85+
" msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */
86+
" msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
87+
" \n"
88+
" save_ctx_therad_mode: \n"
89+
" bx lr \n"
90+
" \n"
8691
::"i" ( securecontextNO_STACK ) : "r1", "memory"
8792
);
8893
}

‎portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port.c‎

Lines changed: 0 additions & 49 deletions
This file was deleted.

‎portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s‎

Lines changed: 34 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -26,52 +26,56 @@
2626
*
2727
*/
2828

29-
SECTION .text:CODE:NOROOT(2)
30-
THUMB
29+
SECTION .text:CODE:NOROOT(2)
30+
THUMB
3131

32-
PUBLIC SecureContext_LoadContextAsm
33-
PUBLIC SecureContext_SaveContextAsm
32+
PUBLIC SecureContext_LoadContextAsm
33+
PUBLIC SecureContext_SaveContextAsm
3434

3535
#if ( configENABLE_FPU == 1 )
36-
#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
36+
#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
3737
#endif
3838
/*-----------------------------------------------------------*/
3939

4040
SecureContext_LoadContextAsm:
41-
/* xSecureContextHandle value is in r0. */
42-
mrs r1, ipsr /* r1 = IPSR. */
43-
cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
44-
ldmia r0!, {r1, r2} /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
41+
/* pxSecureContext value is in r0. */
42+
mrs r1, ipsr /* r1 = IPSR. */
43+
cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
44+
ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
45+
4546
#if ( configENABLE_MPU == 1 )
46-
ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
47-
msr control, r3 /* CONTROL = r3. */
47+
ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
48+
msr control, r3 /* CONTROL = r3. */
4849
#endif /* configENABLE_MPU */
49-
msr psplim, r2 /* PSPLIM = r2. */
50-
msr psp, r1 /* PSP = r1. */
5150

52-
load_ctx_therad_mode:
53-
bx lr
51+
msr psplim, r2 /* PSPLIM = r2. */
52+
msr psp, r1 /* PSP = r1. */
53+
54+
load_ctx_therad_mode:
55+
bx lr
5456
/*-----------------------------------------------------------*/
5557

5658
SecureContext_SaveContextAsm:
57-
/* xSecureContextHandle value is in r0. */
58-
mrs r1, ipsr /* r1 = IPSR. */
59-
cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
60-
mrs r1, psp /* r1 = PSP. */
59+
/* pxSecureContext value is in r0. */
60+
mrs r1, ipsr /* r1 = IPSR. */
61+
cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
62+
mrs r1, psp /* r1 = PSP. */
63+
6164
#if ( configENABLE_MPU == 1 )
62-
mrs r2, control /* r2 = CONTROL. */
63-
subs r1, r1, #4 /* Make space for the CONTROL value on the stack. */
64-
str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
65-
stmia r1!, {r2} /* Store CONTROL value on the stack. */
65+
mrs r2, control /* r2 = CONTROL. */
66+
subs r1, r1, #4 /* Make space for the CONTROL value on the stack. */
67+
str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
68+
stmia r1!, {r2} /* Store CONTROL value on the stack. */
6669
#else /* configENABLE_MPU */
67-
str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
70+
str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
6871
#endif /* configENABLE_MPU */
69-
movs r1, #0 /* r1 = securecontextNO_STACK. */
70-
msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */
71-
msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
7272

73-
save_ctx_therad_mode:
74-
bx lr
73+
movs r1, #0 /* r1 = securecontextNO_STACK. */
74+
msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */
75+
msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
76+
77+
save_ctx_therad_mode:
78+
bx lr
7579
/*-----------------------------------------------------------*/
7680

77-
END
81+
END

‎portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port.c‎

Lines changed: 0 additions & 49 deletions
This file was deleted.

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