Skip to content

Commit fe26af2

Browse files
committed
port: riscv: Fix typo
1 parent 1a1ae36 commit fe26af2

File tree

1 file changed

+1
-1
lines changed

1 file changed

+1
-1
lines changed

portable/GCC/RISC-V/portASM.S

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -197,7 +197,7 @@ definitions. */
197197
*/
198198
pxPortInitialiseStack:
199199
csrr t0, mstatus /* Obtain current mstatus value. */
200-
andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
200+
andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the scheduler has been started, otherwise interrupts would be disabled anyway. */
201201
addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
202202
slli t1, t1, 4
203203
or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */

0 commit comments

Comments
 (0)