diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 6a0c6c8..218b7b4 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -38,7 +38,7 @@ jobs: - name: Clean untracked files and directories (like old submodules) run: git clean -ffdx - name: run test - run: make sim-run SIMULATOR=verilator + run: make sim-test ku040: runs-on: self-hosted diff --git a/Makefile b/Makefile index 0cf951d..e73b0a5 100644 --- a/Makefile +++ b/Makefile @@ -37,6 +37,9 @@ endif ifneq ($(USE_ETHERNET),) PY_PARAMS:=$(PY_PARAMS):use_ethernet=$(USE_ETHERNET) endif +ifneq ($(CPU),) +PY_PARAMS:=$(PY_PARAMS):cpu=$(CPU) +endif # Remove first char (:) from PY_PARAMS PY_PARAMS:=$(shell echo $(PY_PARAMS) | cut -c2-) @@ -44,23 +47,20 @@ PY_PARAMS:=$(shell echo $(PY_PARAMS) | cut -c2-) setup: nix-shell --run "py2hwsw $(CORE) setup --no_verilog_lint --py_params '$(PY_PARAMS)' $(EXTRA_ARGS)" -pc-emul-run: - nix-shell --run "make clean setup && make -C ../$(CORE)_V$(VERSION)/ pc-emul-run" +pc-emul-run: clean setup + nix-shell --run "make -C ../$(CORE)_V$(VERSION)/ pc-emul-run" pc-emul-test: - nix-shell --run "make clean setup && make -C ../$(CORE)_V$(VERSION)/ pc-emul-run" + make pc-emul-run -sim-run: - nix-shell --run "make clean setup && make -C ../$(CORE)_V$(VERSION)/ sim-run SIMULATOR=$(SIMULATOR)" +sim-run: clean setup + nix-shell --run "make -C ../$(CORE)_V$(VERSION)/ sim-run SIMULATOR=$(SIMULATOR)" sim-test: - nix-shell --run "make clean setup USE_INTMEM=1 USE_EXTMEM=0 INIT_MEM=1 && make -C ../$(CORE)_V$(VERSION)/ sim-run SIMULATOR=icarus" - nix-shell --run "make clean setup USE_INTMEM=1 USE_EXTMEM=0 INIT_MEM=0 && make -C ../$(CORE)_V$(VERSION)/ sim-run SIMULATOR=verilator" - nix-shell --run "make clean setup USE_INTMEM=1 USE_EXTMEM=1 INIT_MEM=0 && make -C ../$(CORE)_V$(VERSION)/ sim-run SIMULATOR=verilator" - nix-shell --run "make clean setup USE_INTMEM=0 USE_EXTMEM=1 INIT_MEM=0 && make -C ../$(CORE)_V$(VERSION)/ sim-run SIMULATOR=verilator" + make sim-run CPU=iob_vexriscv SIMULATOR=verilator -fpga-build: - nix-shell --run "make clean setup INIT_MEM=0" +fpga-build: clean + make setup INIT_MEM=0 nix-shell --run "make -C ../$(CORE)_V$(VERSION)/ fpga-sw-build BOARD=$(BOARD)" make -C ../$(CORE)_V$(VERSION)/ fpga-build BOARD=$(BOARD) @@ -69,20 +69,20 @@ fpga-run: make -C ../$(CORE)_V$(VERSION)/ fpga-run BOARD=$(BOARD) fpga-test: - make clean setup fpga-run BOARD=iob_cyclonev_gt_dk USE_INTMEM=0 USE_EXTMEM=1 INIT_MEM=0 - make clean setup fpga-run BOARD=iob_aes_ku040_db_g USE_INTMEM=0 USE_EXTMEM=1 INIT_MEM=0 + make fpga-build fpga-run BOARD=iob_cyclonev_gt_dk USE_INTMEM=0 USE_EXTMEM=1 + make fpga-build fpga-run BOARD=iob_aes_ku040_db_g USE_INTMEM=0 USE_EXTMEM=1 -syn-build: clean - nix-shell --run "make setup && make -C ../$(CORE)_V$(VERSION)/ syn-build SYNTHESIZER=$(SYNTHESIZER)" +syn-build: clean setup + nix-shell --run "make -C ../$(CORE)_V$(VERSION)/ syn-build SYNTHESIZER=$(SYNTHESIZER)" -lint-run: clean - nix-shell --run "make setup && make -C ../$(CORE)_V$(VERSION)/ lint-run LINTER=$(LINTER)" +lint-run: clean setup + nix-shell --run "make -C ../$(CORE)_V$(VERSION)/ lint-run LINTER=$(LINTER)" -doc-build: - nix-shell --run "make clean setup && make -C ../$(CORE)_V$(VERSION)/ doc-build" +doc-build: clean setup + nix-shell --run "make -C ../$(CORE)_V$(VERSION)/ doc-build" -doc-test: - nix-shell --run "make clean setup && make -C ../$(CORE)_V$(VERSION)/ doc-test" +doc-test: clean setup + nix-shell --run "make -C ../$(CORE)_V$(VERSION)/ doc-test" test-all: pc-emul-test sim-test fpga-test syn-build lint-run doc-build doc-test @@ -115,11 +115,11 @@ python-cache-clean: # Tester -tester-sim-run: - nix-shell --run "make clean setup && make -C ../$(CORE)_V$(VERSION)/tester/ sim-run SIMULATOR=$(SIMULATOR)" +tester-sim-run: clean setup + nix-shell --run "make -C ../$(CORE)_V$(VERSION)/tester/ sim-run SIMULATOR=$(SIMULATOR)" -tester-fpga-run: - nix-shell --run "make clean setup && make -C ../$(CORE)_V$(VERSION)/tester/ fpga-sw-build BOARD=$(BOARD)" +tester-fpga-run: clean setup + nix-shell --run "make -C ../$(CORE)_V$(VERSION)/tester/ fpga-sw-build BOARD=$(BOARD)" make -C ../$(CORE)_V$(VERSION)/tester/ fpga-run BOARD=$(BOARD) .PHONY: tester-sim-run tester-fpga-run diff --git a/default.nix b/default.nix index 03f1747..a0447e9 100644 --- a/default.nix +++ b/default.nix @@ -5,8 +5,8 @@ { pkgs ? import (fetchTarball "https://github.com/NixOS/nixpkgs/archive/24.05.tar.gz") {} }: let - py2hwsw_commit = "6393cb57d49a4529e22ff3fd400fd879b8ffbcb2"; # Replace with the desired commit. - py2hwsw_sha256 = "Ud2aZo0YsKGNvODtByf25P/PIpan+3voUO7aP5ODu6c="; # Replace with the actual SHA256 hash. + py2hwsw_commit = "09ea8ddb6b510e894709653666506caead5a93d2"; # Replace with the desired commit. + py2hwsw_sha256 = "iC1Yaeg9NKFIFVwT7o1abXr80ikWZoy6w4TQmIQV3iw="; # Replace with the actual SHA256 hash. # Get local py2hwsw root from `PY2HWSW_ROOT` env variable py2hwswRoot = builtins.getEnv "PY2HWSW_ROOT"; diff --git a/soc_linux.py b/soc_linux.py index 3d574b4..443b2a5 100644 --- a/soc_linux.py +++ b/soc_linux.py @@ -3,57 +3,51 @@ # SPDX-License-Identifier: MIT -def setup(py_params_dict): +def setup(py_params: dict): # Py2hwsw dictionary describing current core - core_dict = { + attributes_dict = { "version": "0.8", "parent": { # SoC-Linux is a child core of iob_system_linux: https://github.com/IObundle/py2hwsw/tree/main/py2hwsw/lib/hardware/iob_system_linux # SoC-Linux will inherit all attributes/files from the iob_system_linux core. "core_name": "iob_system_linux", # Every parameter in the lines below will be passed to the iob_system_linux parent core. - # Full list of parameters availabe here: https://github.com/IObundle/py2hwsw/blob/main/py2hwsw/lib/iob_system_linux/iob_system_linux.py - # "cpu": "iob_vexriscv", - # # NOTE: Place other iob_system_linux python parameters here + # Full list of parameters available here: https://github.com/IObundle/py2hwsw/blob/main/py2hwsw/lib/iob_system/iob_system_linux/iob_system_linux.py # - # "system_attributes": { - # # Every attribute in this dictionary will override/append to the ones of the iob_system_linux parent core. - # "board_list": [ - # "iob_aes_ku040_db_g", - # "iob_cyclonev_gt_dk", - # "iob_zybo_z7", - # ], - # "ports": [ - # { - # # Add new rs232 port for uart - # "name": "rs232_m", - # "descr": "iob-system uart interface", - # "signals": { - # "type": "rs232", - # }, - # }, - # # NOTE: Add other ports here. - # ], - # "subblocks": [ - # { - # # Instantiate a UART16550 core from: https://github.com/IObundle/iob-uart16550 - # "core_name": "iob_uart16550", - # "instance_name": "UART0", # Use same name as one inherited from iob_system to replace it - # "instance_description": "UART peripheral", - # "is_peripheral": True, - # "parameters": {}, - # "connect": { - # "clk_en_rst_s": "clk_en_rst_s", - # # Cbus connected automatically - # "rs232_m": "rs232_m", - # "interrupt_o": "uart_interrupt", - # }, - # }, - # # NOTE: Add other components/peripherals here. + # Select CPU to use. For a list of compatible CPUs and info about custom CPU integration + # check the 'cpu' python parameter at: https://github.com/IObundle/py2hwsw/blob/main/py2hwsw/lib/iob_system/iob_system.py + "cpu": "iob_vexriscv", + # + # NOTE: Place other iob_system_linux python parameters here + # "some_iob_system_linux_param": "my_value", + **py_params, + }, + # Every attribute in this dictionary will override/append to the ones of the iob_system_linux parent core. + "board_list": [ + "iob_aes_ku040_db_g", + "iob_cyclonev_gt_dk", + "iob_zybo_z7", + ], + "ports": [ + { + # Override rs232 port of uart (inherited from iob_system_linux) + "name": "rs232_m", + "descr": "soc_linux uart interface", + "signals": { + "type": "rs232", + }, + }, + # NOTE: Add other ports here. + # { + # "name": "my_custom_interface_io", + # "descr": "Custom SoCLinux interface", + # "signals": [ + # {"name": "my_input_port_i", "width": 32}, + # {"name": "my_output_port_o", "width": 32}, # ], # }, - **py_params_dict, - }, + ], + # NOTE: Add other component overrides here. } - return core_dict + return attributes_dict