hi3516ev300 6.6 LTS: mainline drivers need vendor init for BVT-specific hardware

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Context

Porting hi3516ev300 from vendor Linux 4.9 to mainline 6.6 LTS revealed that mainline drivers for HiSilicon IP exist but miss BVT-specific hardware initialization. The hi3516ev200/ev300 platform was never upstreamed — mainline drivers target older SoCs (hi3516cv300, hi3798) and partially work on ev300 but fail on BVT-specific silicon.

Kernel branch: hisilicon-hi3516ev200-6.6

Drivers requiring vendor patches

1. hisi-sfc (SPI NOR flash controller)

Mainline: drivers/mtd/spi-nor/controllers/hisi-sfc.c (498 lines)
Vendor: drivers/mtd/spi-nor/hisi-sfc.c (603 lines)

Issues found on real hardware:

• Quad read mode — mainline advertises SNOR_HWCAPS_READ_1_1_4 but never sets the flash QE bit. Reads return garbage with opcode 0x6B. Fix: removed quad from hwcaps, uses dual (0x3B) like vendor.
• FMC init missing — mainline hisi_spi_nor_init() only sets timing. Vendor also: selects SPI-NOR flash type in FMC_CFG, switches boot→normal mode, disables DTR mode in FMC_GLOBAL_CFG. Fix: ported vendor init sequence.

Approach taken: patched mainline driver in-place (minimal changes to existing code).

2. mdio-hisi-femac (MDIO bus / Ethernet PHY)

Mainline: drivers/net/mdio/mdio-hisi-femac.c (152 lines)
Vendor: drivers/net/phy/mdio-hisi-femac.c (471 lines)

Issues found on real hardware:

• Internal FEPHY not initialized — mainline is just an MDIO bus read/write driver. The hi3516ev300 has an internal Fast Ethernet PHY (FEPHY) that needs: reset sequence via CRG register, PHY address configuration via control register, analog trim/calibration from OTP data. Without this, MDIO reads return phy_id=0x00000000.
• Path moved in 6.6 — MDIO drivers moved from drivers/net/phy/ to drivers/net/mdio/. Initial port went to wrong path.

Approach taken: wholesale replacement with vendor driver. Too many differences (320 extra lines of FEPHY-specific init) to patch mainline incrementally.

3. hisi_femac (Ethernet MAC)

Mainline: drivers/net/ethernet/hisilicon/hisi_femac.c

Minor issue: compatible string hi3516ev300-femac not in mainline's match table. Fix: added one line to match table.

What needs to happen long-term

Each driver needs a clear porting strategy. Two approaches per driver:

A. Patch mainline (preferred when diff is small)

• hisi-sfc: 3 register writes added to init, 1 hwcaps line removed
• hisi_femac: 1 compatible string added
• Clean, reviewable, potentially upstreamable

B. Replace with vendor (when diff is too large)

• mdio-hisi-femac: 320 lines of FEPHY init, trim, OTP — no way to incrementally patch mainline
• Risk: vendor code uses 4.9 API, needs compat fixes for 6.6

Open questions for future drivers

1. Clock drivers (clk-hi3516ev300.c): vendor-only, no mainline equivalent — must be carried as-is
2. Machine descriptor (mach-hi3516ev300.c): vendor-only, minimal (pure DT boot)
3. Timer (timer-hisp804.c): vendor-only, ported with API updates (setup_irq→request_irq, cycle_t→u64)
4. I2C (i2c-hibvt.c): vendor-only, compiled unchanged
5. Reset controller (reset.c): mainline exists for ARCH_HISI, needed ARCH_HISI_BVT dependency + hibvt_reset_init() function

Build/test status

Component	QEMU	Real HW	Fix
SPI NOR flash	✅	✅	Dual read + FMC init
Ethernet	✅	🔄 testing	Vendor MDIO driver
Boot (U-Boot→kernel)	✅	✅	DTB append in boot Makefile
Squashfs rootfs	✅	✅	—
All services (ssh, ntp, majestic)	✅	🔄	—