diff --git a/fpga_diff/Makefile b/fpga_diff/Makefile index 9f3d2ee4..680cfc7b 100755 --- a/fpga_diff/Makefile +++ b/fpga_diff/Makefile @@ -23,7 +23,8 @@ PRJ_NAME = fpga_$(CPU)$(if $(strip $(SUFFIX)),-$(strip $(SUFFIX)),) PRJ_DIR ?= $(ENV_SCRIPTS_HOME)/$(PRJ_NAME) PRJ ?= $(PRJ_DIR)/$(PRJ_NAME).xpr -.PHONY: bitstream vivado dump_ila write_jtag_flash update_core_flist +.PHONY: bitstream vivado dump_ila update_core_flist \ + write_bitstream halt_soc write_jtag_ddr write_jtag_flash reset_cpu # Get Vivado version VIVADO_VERSION := $(shell vivado -version 2>/dev/null | head -1 | grep -o '[0-9]\{4\}\.[0-9]' || echo "unknown") @@ -41,7 +42,7 @@ bitstream: # RTL_INCLUDE accepts RTL files, directories, and .f/.flist/.list file lists. update_core_flist: - @./tools/update_core_flist.sh "$(CORE_DIR)" -- $(RTL_INCLUDE) + @./tools/update_core_flist.sh vivado "$(CORE_DIR)" -- $(RTL_INCLUDE) # Launch Vivado with FPGA project configuration vivado: check_vivado_version @@ -99,3 +100,7 @@ get_synth_log: all: $(MAKE) update_core_flist CORE_DIR="$(CORE_DIR)" RTL_INCLUDE="$(RTL_INCLUDE)" $(MAKE) vivado CPU=$(CPU) SUFFIX="$(SUFFIX)" + +# UVHS targets use an explicit uvhs_* namespace and do not replace the normal +# Vivado/JTAG targets above. +include uvhs/uvhs.mk diff --git a/fpga_diff/README.md b/fpga_diff/README.md index ec464c50..1c960bc2 100755 --- a/fpga_diff/README.md +++ b/fpga_diff/README.md @@ -48,4 +48,16 @@ FPGA_DDR_LOAD_CMD="bash -lc ' \ ./fpga-host --diff -i .bin ``` +UVHS Flow +========= +The Hejian UVHS flow uses separate `uvhs_*` targets and leaves the targets above +unchanged. Configure the UVHS tool environment in the runtime host shell, then +invoke: + +```shell +make uvhs CPU= CORE_DIR=/path/to/release/build SUFFIX= +``` + +See [`uvhs/README.md`](uvhs/README.md) for the board-template and vendor-DDR +inputs, build stages, and runtime commands. diff --git a/fpga_diff/src/rtl/common/core_def_xdma.sv b/fpga_diff/src/rtl/common/core_def_xdma.sv index 8956db12..ce7a0ba5 100755 --- a/fpga_diff/src/rtl/common/core_def_xdma.sv +++ b/fpga_diff/src/rtl/common/core_def_xdma.sv @@ -54,6 +54,7 @@ module core_def ( output [1:0] uhs1_drv_sth , output uhs1_swvolt_en , output sd_led_control , +`ifndef UVHS output [`CONFIG_RANK_WIDTH-1:0] DDR_CK_T , output [`CONFIG_RANK_WIDTH-1:0] DDR_CK_C , output [`CONFIG_RANK_WIDTH-1:0] DDR_CKE , @@ -68,6 +69,7 @@ module core_def ( inout [63:0] DDR_DQ , inout [7:0] DDR_DQS_T , inout [7:0] DDR_DQS_C , +`endif //==JTAG @@ -998,6 +1000,93 @@ wire [1 : 0] rom_axi_rresp ; (*mark_debug = "true"*) wire rom_axi_rvalid ; (*mark_debug = "true"*) wire rom_axi_rlast ; (*mark_debug = "true"*) wire rom_axi_rready ; + +`ifdef UVHS +wire [7:0] uvhs_flash_axi_awid; +wire [31:0] uvhs_flash_axi_awaddr; +wire [3:0] uvhs_flash_axi_awlen; +wire [2:0] uvhs_flash_axi_awsize; +wire [1:0] uvhs_flash_axi_awburst; +wire [1:0] uvhs_flash_axi_awlock; +wire [3:0] uvhs_flash_axi_awcache; +wire [2:0] uvhs_flash_axi_awprot; +wire [3:0] uvhs_flash_axi_awqos; +wire uvhs_flash_axi_awvalid; +wire uvhs_flash_axi_awready; +wire [7:0] uvhs_flash_axi_wid; +wire [63:0] uvhs_flash_axi_wdata; +wire [7:0] uvhs_flash_axi_wstrb; +wire uvhs_flash_axi_wlast; +wire uvhs_flash_axi_wvalid; +wire uvhs_flash_axi_wready; +wire [7:0] uvhs_flash_axi_bid; +wire [1:0] uvhs_flash_axi_bresp; +wire uvhs_flash_axi_bvalid; +wire uvhs_flash_axi_bready; +wire [7:0] uvhs_flash_axi_arid; +wire [31:0] uvhs_flash_axi_araddr; +wire [3:0] uvhs_flash_axi_arlen; +wire [2:0] uvhs_flash_axi_arsize; +wire [1:0] uvhs_flash_axi_arburst; +wire [1:0] uvhs_flash_axi_arlock; +wire [3:0] uvhs_flash_axi_arcache; +wire [2:0] uvhs_flash_axi_arprot; +wire [3:0] uvhs_flash_axi_arqos; +wire uvhs_flash_axi_arvalid; +wire uvhs_flash_axi_arready; +wire [7:0] uvhs_flash_axi_rid; +wire [63:0] uvhs_flash_axi_rdata; +wire [1:0] uvhs_flash_axi_rresp; +wire uvhs_flash_axi_rlast; +wire uvhs_flash_axi_rvalid; +wire uvhs_flash_axi_rready; + +uvw_general_bus U_UVHS_FLASH_GBUS ( + .dut_axi_aclk (sys_clk_i), + .dut_axi_aclk_en (1'b1), + .dut_axi_aresetn (axi_bclk_sync_rstn), + .dut_axi_awid (uvhs_flash_axi_awid), + .dut_axi_awaddr (uvhs_flash_axi_awaddr), + .dut_axi_awlen (uvhs_flash_axi_awlen), + .dut_axi_awsize (uvhs_flash_axi_awsize), + .dut_axi_awburst (uvhs_flash_axi_awburst), + .dut_axi_awlock (uvhs_flash_axi_awlock), + .dut_axi_awcache (uvhs_flash_axi_awcache), + .dut_axi_awprot (uvhs_flash_axi_awprot), + .dut_axi_awqos (uvhs_flash_axi_awqos), + .dut_axi_awvalid (uvhs_flash_axi_awvalid), + .dut_axi_awready (uvhs_flash_axi_awready), + .dut_axi_wid (uvhs_flash_axi_wid), + .dut_axi_wdata (uvhs_flash_axi_wdata), + .dut_axi_wstrb (uvhs_flash_axi_wstrb), + .dut_axi_wlast (uvhs_flash_axi_wlast), + .dut_axi_wvalid (uvhs_flash_axi_wvalid), + .dut_axi_wready (uvhs_flash_axi_wready), + .dut_axi_bid (uvhs_flash_axi_bid), + .dut_axi_bresp (uvhs_flash_axi_bresp), + .dut_axi_bvalid (uvhs_flash_axi_bvalid), + .dut_axi_bready (uvhs_flash_axi_bready), + .dut_axi_arid (uvhs_flash_axi_arid), + .dut_axi_araddr (uvhs_flash_axi_araddr), + .dut_axi_arlen (uvhs_flash_axi_arlen), + .dut_axi_arsize (uvhs_flash_axi_arsize), + .dut_axi_arburst (uvhs_flash_axi_arburst), + .dut_axi_arlock (uvhs_flash_axi_arlock), + .dut_axi_arcache (uvhs_flash_axi_arcache), + .dut_axi_arprot (uvhs_flash_axi_arprot), + .dut_axi_arqos (uvhs_flash_axi_arqos), + .dut_axi_arvalid (uvhs_flash_axi_arvalid), + .dut_axi_arready (uvhs_flash_axi_arready), + .dut_axi_rid (uvhs_flash_axi_rid), + .dut_axi_rdata (uvhs_flash_axi_rdata), + .dut_axi_rresp (uvhs_flash_axi_rresp), + .dut_axi_rlast (uvhs_flash_axi_rlast), + .dut_axi_rvalid (uvhs_flash_axi_rvalid), + .dut_axi_rready (uvhs_flash_axi_rready), + .sysbus_ghbd_o (), + .sysbus_ghbd_i () +); +`endif `endif `ifdef XS_QSPI2ROM @@ -1124,6 +1213,7 @@ wire [7:0] br2cfg_wstrb; wire [0:0] br2cfg_wvalid; wire [31:0] XDMA_AXI_LITE_awaddr; + wire [2:0] XDMA_AXI_LITE_awprot; wire XDMA_AXI_LITE_awvalid; wire XDMA_AXI_LITE_awready; wire [31:0] XDMA_AXI_LITE_wdata; @@ -1134,6 +1224,7 @@ wire [0:0] br2cfg_wvalid; wire XDMA_AXI_LITE_bvalid; wire XDMA_AXI_LITE_bready; wire [31:0] XDMA_AXI_LITE_araddr; + wire [2:0] XDMA_AXI_LITE_arprot; wire XDMA_AXI_LITE_arvalid; wire XDMA_AXI_LITE_arready; wire [31:0] XDMA_AXI_LITE_rdata; @@ -1154,7 +1245,9 @@ wire [0:0] br2cfg_wvalid; wire [`CONFIG_DIFFTEST_HOST_AXIS_BYTES-1:0] difftest_from_host_axis_tkeep; wire difftest_from_host_axis_tlast; wire difftest_clock_enable; + wire difftest_clock_gate_enable; wire inter_soc_clk; + wire inter_soc_sync_rstn; wire inter_rtc_clk; wire io_host_reset; @@ -1167,20 +1260,15 @@ wire [0:0] br2cfg_wvalid; wire difftest_startup_done_pcie; wire cpu_rstn_pcie; wire io_host_diff_enable_pcie; - wire xdma_link_up_pcie; reg [19:0] difftest_startup_wait_pcie; reg difftest_stream_enable_pcie; wire difftest_pcie_clock; assign sys_rstn_io = sys_rstn & ~io_host_reset; assign cpu_rstn_io = cpu_rstn & ~io_host_reset; - - reg [1:0] pcie_lnk_sync; - always @(posedge sys_clk_i) begin - if (!sys_rstn) pcie_lnk_sync <= 2'b00; - else pcie_lnk_sync <= {pcie_lnk_sync[0], pcie_ep_lnk_up}; - end - wire xdma_link_up = pcie_lnk_sync[1]; + assign difftest_clock_gate_enable = + difftest_clock_enable || ~io_host_diff_enable || + ~sys_rstn_io || ~cpu_rstn_io; RST_SYNC #( .SYNC_STAGES(3), @@ -1202,17 +1290,9 @@ wire [0:0] br2cfg_wvalid; .sync_out (io_host_diff_enable_pcie) ); - RST_SYNC #( - .SYNC_STAGES(3), - .PIPELINE_STAGES(1), - .INIT(1'b0) - ) difftest_link_up_pcie_sync ( - .clk (difftest_pcie_clock), - .async_in (xdma_link_up), - .sync_out (xdma_link_up_pcie) - ); - - assign difftest_startup_ready_pcie = cpu_rstn_pcie & io_host_diff_enable_pcie & xdma_link_up_pcie; + // Host enables DiffTest only after XDMA is accessible. Do not feed the + // physical XDMA link-status output back into fabric logic. + assign difftest_startup_ready_pcie = cpu_rstn_pcie & io_host_diff_enable_pcie; assign difftest_startup_done_pcie = &difftest_startup_wait_pcie; always @(posedge difftest_pcie_clock) begin @@ -1244,7 +1324,7 @@ wire [0:0] br2cfg_wvalid; .M00_AXIS_0_tvalid (difftest_from_host_axis_tvalid), .XDMA_AXI_LITE_awaddr (XDMA_AXI_LITE_awaddr), - .XDMA_AXI_LITE_awprot (3'b000), + .XDMA_AXI_LITE_awprot (XDMA_AXI_LITE_awprot), .XDMA_AXI_LITE_awvalid(XDMA_AXI_LITE_awvalid), .XDMA_AXI_LITE_awready(XDMA_AXI_LITE_awready), .XDMA_AXI_LITE_wdata (XDMA_AXI_LITE_wdata), @@ -1255,7 +1335,7 @@ wire [0:0] br2cfg_wvalid; .XDMA_AXI_LITE_bvalid (XDMA_AXI_LITE_bvalid), .XDMA_AXI_LITE_bready (XDMA_AXI_LITE_bready), .XDMA_AXI_LITE_araddr (XDMA_AXI_LITE_araddr), - .XDMA_AXI_LITE_arprot (3'b000), + .XDMA_AXI_LITE_arprot (XDMA_AXI_LITE_arprot), .XDMA_AXI_LITE_arvalid(XDMA_AXI_LITE_arvalid), .XDMA_AXI_LITE_arready(XDMA_AXI_LITE_arready), .XDMA_AXI_LITE_rdata (XDMA_AXI_LITE_rdata), @@ -1276,13 +1356,23 @@ wire [0:0] br2cfg_wvalid; DifftestClockGate SOC_CLK_CTRL( .CK (sys_clk_i), - .E ((difftest_clock_enable & xdma_link_up ) || ~io_host_diff_enable || ~sys_rstn_io || ~cpu_rstn_io), + .E (difftest_clock_gate_enable), .Q (inter_soc_clk) ); + RST_SYNC #( + .SYNC_STAGES(3), + .PIPELINE_STAGES(1), + .INIT(1'b0) + ) inter_soc_rstn_sync ( + .clk (inter_soc_clk), + .async_in (cpu_rstn_io), + .sync_out (inter_soc_sync_rstn) + ); + DifftestClockGate RTC_CLK_CTRL( .CK (tmclk), - .E ((difftest_clock_enable & xdma_link_up) || ~io_host_diff_enable || ~sys_rstn_io || ~cpu_rstn_io ), + .E (difftest_clock_enable || ~io_host_diff_enable || ~sys_rstn_io || ~cpu_rstn_io ), .Q (inter_rtc_clk) ); @@ -1335,6 +1425,91 @@ mode_ctrl U_MODE_CTRL( .scan_mode ( ) ); +`ifdef UVHS +// The vendor DDR IP uses 34-bit addresses and 14-bit IDs. Keep those narrow +// adaptations local while preserving the common fpga_diff AXI interface. +wire [33:0] uvhs_ddr_awaddr; +wire [33:0] uvhs_ddr_araddr; +wire [13:0] uvhs_ddr_bid; +wire [13:0] uvhs_ddr_rid; +wire uvhs_ddr_user_rst; + +`ifdef CPU_NUTSHELL +assign uvhs_ddr_awaddr = {1'b0, cpu2ddr_m2s_awaddr_mix}; +assign uvhs_ddr_araddr = {1'b0, cpu2ddr_m2s_araddr_mix}; +`else +assign uvhs_ddr_awaddr = cpu2ddr_m2s_awaddr_mix[33:0]; +assign uvhs_ddr_araddr = cpu2ddr_m2s_araddr_mix[33:0]; +`endif +assign cpu2ddr_s2m_bid = {4'b0, uvhs_ddr_bid}; +assign cpu2ddr_s2m_rid = {4'b0, uvhs_ddr_rid}; +assign init_calib_complete = rstn_sw4 & ~uvhs_ddr_user_rst; + +uvw_axi4_to_ddr4 U_UVHS_UVW_AXI4_TO_DDR4 ( + .ddr4ip_dut_axi_aclk (sys_clk_i), + .ddr4ip_dut_axi_aresetn (rstn_sw4), + .ddr4ip_dut_axi_awaddr (uvhs_ddr_awaddr), + .ddr4ip_dut_axi_awburst (cpu2ddr_m2s_awburst), + .ddr4ip_dut_axi_awcache (cpu2ddr_m2s_awcache), + .ddr4ip_dut_axi_awid (cpu2ddr_m2s_awid_mix[13:0]), + .ddr4ip_dut_axi_awlen (cpu2ddr_m2s_awlen), + .ddr4ip_dut_axi_awlock (cpu2ddr_m2s_awlock), + .ddr4ip_dut_axi_awprot (cpu2ddr_m2s_awprot), + .ddr4ip_dut_axi_awqos (cpu2ddr_m2s_awqos), + .ddr4ip_dut_axi_awready (cpu2ddr_s2m_awready), + .ddr4ip_dut_axi_awregion (cpu2ddr_m2s_awregion), + .ddr4ip_dut_axi_awsize (cpu2ddr_m2s_awsize), + .ddr4ip_dut_axi_awvalid (cpu2ddr_m2s_awvalid), + .ddr4ip_dut_axi_wdata (cpu2ddr_m2s_wdata), + .ddr4ip_dut_axi_wlast (cpu2ddr_m2s_wlast), + .ddr4ip_dut_axi_wready (cpu2ddr_s2m_wready), + .ddr4ip_dut_axi_wstrb (cpu2ddr_m2s_wstrb), + .ddr4ip_dut_axi_wvalid (cpu2ddr_m2s_wvalid), + .ddr4ip_dut_axi_bid (uvhs_ddr_bid), + .ddr4ip_dut_axi_bready (cpu2ddr_m2s_bready), + .ddr4ip_dut_axi_bresp (cpu2ddr_s2m_bresp), + .ddr4ip_dut_axi_bvalid (cpu2ddr_s2m_bvalid), + .ddr4ip_dut_axi_araddr (uvhs_ddr_araddr), + .ddr4ip_dut_axi_arburst (cpu2ddr_m2s_arburst), + .ddr4ip_dut_axi_arcache (cpu2ddr_m2s_arcache), + .ddr4ip_dut_axi_arid (cpu2ddr_m2s_arid_mix[13:0]), + .ddr4ip_dut_axi_arlen (cpu2ddr_m2s_arlen), + .ddr4ip_dut_axi_arlock (cpu2ddr_m2s_arlock), + .ddr4ip_dut_axi_arprot (cpu2ddr_m2s_arprot), + .ddr4ip_dut_axi_arqos (cpu2ddr_m2s_arqos), + .ddr4ip_dut_axi_arready (cpu2ddr_s2m_arready), + .ddr4ip_dut_axi_arregion (cpu2ddr_m2s_arregion), + .ddr4ip_dut_axi_arsize (cpu2ddr_m2s_arsize), + .ddr4ip_dut_axi_arvalid (cpu2ddr_m2s_arvalid), + .ddr4ip_dut_axi_rdata (cpu2ddr_s2m_rdata), + .ddr4ip_dut_axi_rid (uvhs_ddr_rid), + .ddr4ip_dut_axi_rlast (cpu2ddr_s2m_rlast), + .ddr4ip_dut_axi_rready (cpu2ddr_m2s_rready), + .ddr4ip_dut_axi_rresp (cpu2ddr_s2m_rresp), + .ddr4ip_dut_axi_rvalid (cpu2ddr_s2m_rvalid), + .ddr4ip_dut_axi_aclk_en (difftest_clock_gate_enable), + .ddr4ip_ddr4_user_clk (), + .ddr4ip_ddr4_user_rst (uvhs_ddr_user_rst), + .sysbus_ghbd_i (256'b0), + .sysbus_ghbd_o (), + .FP_CLK_200M_P (), + .FP_CLK_200M_N (), + .DDR4_DIMM_ACT_N (), + .DDR4_DIMM_A (), + .DDR4_DIMM_BA (), + .DDR4_DIMM_BG (), + .DDR4_DIMM_CK_N (), + .DDR4_DIMM_CK_P (), + .DDR4_DIMM_CKE (), + .DDR4_DIMM_CS_N (), + .DDR4_DIMM_ODT (), + .DDR4_DIMM_RST_B (), + .DDR4_DIMM_DM (), + .DDR4_DIMM_DQ (), + .DDR4_DIMM_DQS_N (), + .DDR4_DIMM_DQS_P () +); +`else jtag_ddr_subsys_wrapper U_JTAG_DDR_SUBSYS( .DDR4_act_n (DDR_ACT_N), .DDR4_adr (DDR_A), @@ -1434,6 +1609,7 @@ jtag_ddr_subsys_wrapper U_JTAG_DDR_SUBSYS( .soc_rstn (rstn_sw4), .calib_complete (init_calib_complete) ); +`endif SimTop_wrapper U_CPU_TOP( .difftest_pcie_clock (difftest_pcie_clock), @@ -1649,6 +1825,11 @@ assign hpm_dig_result = 0; AXI_bridge CFG_AXI_bridge_i (.SYS_INTER_CLK (inter_soc_clk), +`ifdef UVHS + .SYS_INTER_ARESETN (inter_soc_sync_rstn), + .UART_ACLK (uart_sclk), + .UART_ARESETN (uart_sclk_sync_rstn), +`endif .ACLK (sys_clk_i), .ARESETN (axi_bclk_sync_rstn), @@ -1690,6 +1871,47 @@ AXI_bridge CFG_AXI_bridge_i .S00_AXI_wstrb (cpu2cfg_m2s_wstrb), .S00_AXI_wvalid (cpu2cfg_m2s_wvalid), +`ifdef UVHS + .UVHS_FLASH_AXI_araddr (uvhs_flash_axi_araddr), + .UVHS_FLASH_AXI_arburst (uvhs_flash_axi_arburst), + .UVHS_FLASH_AXI_arcache (uvhs_flash_axi_arcache), + .UVHS_FLASH_AXI_arid (uvhs_flash_axi_arid), + .UVHS_FLASH_AXI_arlen (uvhs_flash_axi_arlen), + .UVHS_FLASH_AXI_arlock (uvhs_flash_axi_arlock), + .UVHS_FLASH_AXI_arprot (uvhs_flash_axi_arprot), + .UVHS_FLASH_AXI_arqos (uvhs_flash_axi_arqos), + .UVHS_FLASH_AXI_arready (uvhs_flash_axi_arready), + .UVHS_FLASH_AXI_arsize (uvhs_flash_axi_arsize), + .UVHS_FLASH_AXI_arvalid (uvhs_flash_axi_arvalid), + .UVHS_FLASH_AXI_awaddr (uvhs_flash_axi_awaddr), + .UVHS_FLASH_AXI_awburst (uvhs_flash_axi_awburst), + .UVHS_FLASH_AXI_awcache (uvhs_flash_axi_awcache), + .UVHS_FLASH_AXI_awid (uvhs_flash_axi_awid), + .UVHS_FLASH_AXI_awlen (uvhs_flash_axi_awlen), + .UVHS_FLASH_AXI_awlock (uvhs_flash_axi_awlock), + .UVHS_FLASH_AXI_awprot (uvhs_flash_axi_awprot), + .UVHS_FLASH_AXI_awqos (uvhs_flash_axi_awqos), + .UVHS_FLASH_AXI_awready (uvhs_flash_axi_awready), + .UVHS_FLASH_AXI_awsize (uvhs_flash_axi_awsize), + .UVHS_FLASH_AXI_awvalid (uvhs_flash_axi_awvalid), + .UVHS_FLASH_AXI_bid (uvhs_flash_axi_bid), + .UVHS_FLASH_AXI_bready (uvhs_flash_axi_bready), + .UVHS_FLASH_AXI_bresp (uvhs_flash_axi_bresp), + .UVHS_FLASH_AXI_bvalid (uvhs_flash_axi_bvalid), + .UVHS_FLASH_AXI_rdata (uvhs_flash_axi_rdata), + .UVHS_FLASH_AXI_rid (uvhs_flash_axi_rid), + .UVHS_FLASH_AXI_rlast (uvhs_flash_axi_rlast), + .UVHS_FLASH_AXI_rready (uvhs_flash_axi_rready), + .UVHS_FLASH_AXI_rresp (uvhs_flash_axi_rresp), + .UVHS_FLASH_AXI_rvalid (uvhs_flash_axi_rvalid), + .UVHS_FLASH_AXI_wdata (uvhs_flash_axi_wdata), + .UVHS_FLASH_AXI_wid (uvhs_flash_axi_wid), + .UVHS_FLASH_AXI_wlast (uvhs_flash_axi_wlast), + .UVHS_FLASH_AXI_wready (uvhs_flash_axi_wready), + .UVHS_FLASH_AXI_wstrb (uvhs_flash_axi_wstrb), + .UVHS_FLASH_AXI_wvalid (uvhs_flash_axi_wvalid), +`endif + .SYS_CFG_APB_paddr (syscfg_paddr_mix), .SYS_CFG_APB_penable (syscfg_penable), .SYS_CFG_APB_prdata (syscfg_prdata), diff --git a/fpga_diff/src/rtl/common/fpga_top_debug.sv b/fpga_diff/src/rtl/common/fpga_top_debug.sv index 9cf9bc9c..31d5d6a9 100755 --- a/fpga_diff/src/rtl/common/fpga_top_debug.sv +++ b/fpga_diff/src/rtl/common/fpga_top_debug.sv @@ -15,7 +15,7 @@ module fpga_top_debug input clk8_n, input clk7_p, // ddr 80MHz input clk7_n, - input clk6_p, // system 200MHz + input clk6_p, // system 200MHz / UVHS UART 50MHz input clk6_n, input clk5_p, // debug 25MHz input clk5_n, @@ -34,14 +34,16 @@ module fpga_top_debug output uart2_sout, input uart2_sin, `endif - //PCIE + //PCIE +`ifndef UVHS input refclk_p, // pcie 100MHz input refclk_n, output PERST_N, - + input refclk2_p, // pcie 100MHz input refclk2_n, output PERST2_N, +`endif `ifdef XS_XDMA_EP input [`XDMA_PCIE_LANES-1:0] pci_ep_rxn, input [`XDMA_PCIE_LANES-1:0] pci_ep_rxp, @@ -53,6 +55,7 @@ module fpga_top_debug input pcie_ep_perstn, `endif //DDR +`ifndef UVHS output [`CONFIG_RANK_WIDTH-1:0] DDR0_CK_T, output [`CONFIG_RANK_WIDTH-1:0] DDR0_CK_C, output [`CONFIG_RANK_WIDTH-1:0] DDR0_CKE, @@ -67,6 +70,7 @@ module fpga_top_debug inout [63:0] DDR0_DQ, inout [7:0] DDR0_DQS_T, inout [7:0] DDR0_DQS_C, +`endif `ifdef XS_GMAC input RGMII_RXCLK, @@ -108,10 +112,20 @@ wire vio_sw4; wire sys_rstn; wire cpu_setn_buf; wire sys_clk_i, dev_clk_i; +wire sys_rstn_to_core; +wire cpu_rstn_to_core; +wire ddr_rstn_to_core; wire pcie_rstn; (*mark_debug = "true"*) wire cpu_setn_rflag; (*mark_debug = "true"*) reg cpu_rstn; +`ifdef UVHS +assign sys_rstn = rstn_sw6; +assign cpu_setn_buf = rstn_sw5; +assign sys_rstn_to_core = rstn_sw6; +assign cpu_rstn_to_core = rstn_sw5; +assign ddr_rstn_to_core = rstn_sw4; +`else IBUF sys_rstn_ibuf (.O(sys_rstn), .I(rstn_sw6)); IBUF cpu_rstn_ibuf (.O(cpu_setn_buf), .I(rstn_sw5)); OBUF pcie_rstn_obuf (.O(PERST_N), .I(vio_sw6)); @@ -133,13 +147,28 @@ always@(posedge sys_clk_i) begin cpu_rstn <= cpu_rstn; end +assign sys_rstn_to_core = sys_rstn && vio_sw6; +assign cpu_rstn_to_core = cpu_rstn; +assign ddr_rstn_to_core = rstn_sw4 && vio_sw4; +`endif + +`ifdef XS_GMAC // Suppose PHY_RESET_B active high. // Although 88E1116R pin10 resetn is active low. // But this pin is on connector, which might not have current by default? -assign PHY_RESET_B = cpu_rstn; +assign PHY_RESET_B = cpu_rstn_to_core; +`endif -wire tmclk; wire tmclk_buf; +wire cqetmclk_buf; +wire dbg_clk_buf; + +`ifdef UVHS +assign tmclk_buf = clk8_p; +assign cqetmclk_buf = clk6_p; +assign dbg_clk_buf = clk5_p; +`else +wire tmclk; IBUFGDS ibufgds_tmclk_1MHz ( .I (clk8_p), @@ -153,7 +182,6 @@ BUFG bufg_tmclk ); wire cqetmclk; -wire cqetmclk_buf; IBUFGDS ibufgds_tmclk_200MHz ( .I (clk6_p), @@ -168,7 +196,6 @@ BUFG bufg_cqetmclk ); wire dbg_clk; -wire dbg_clk_buf; IBUFGDS ibufgds_dbgclk_25MHz ( .I (clk5_p), @@ -181,30 +208,38 @@ BUFG bufg_dbgclk .I (dbg_clk), .O (dbg_clk_buf) ); +`endif +`ifndef UVHS wire pcie_sysclk_gt; wire pcie_sysclk; IBUFDS_GTE4 refclk_ibuf ( - .O(pcie_sysclk_gt), - .ODIV2(pcie_sysclk), - .I(refclk_p), - .CEB(1'b0), + .O(pcie_sysclk_gt), + .ODIV2(pcie_sysclk), + .I(refclk_p), + .CEB(1'b0), .IB(refclk_n) ); IBUFDS_GTE4 refclk2_ibuf ( - .O(pcie2_sysclk_gt), - .ODIV2(pcie2_sysclk), - .I(refclk2_p), - .CEB(1'b0), + .O(pcie2_sysclk_gt), + .ODIV2(pcie2_sysclk), + .I(refclk2_p), + .CEB(1'b0), .IB(refclk2_n) ); +`endif assign sys_clk_i = dbg_clk_buf; +`ifdef UVHS +assign dev_clk_i = cqetmclk_buf; +`else assign dev_clk_i = dbg_clk_buf; +`endif +`ifndef UVHS vio_0 u_vio( .clk (dbg_clk_buf), @@ -212,6 +247,7 @@ vio_0 u_vio( .probe_out1 (vio_sw5), .probe_out2 (vio_sw4) ); +`endif //------------led test------------------ wire sdmmc_cclk_card; @@ -332,9 +368,9 @@ core_def core_def .cpu_wr_ddr_valid (led0), .sys_clk_i (sys_clk_i), .dev_clk_i (dev_clk_i), - .sys_rstn (sys_rstn && vio_sw6), - .cpu_rstn (cpu_rstn), - .rstn_sw4 (rstn_sw4 && vio_sw4), + .sys_rstn (sys_rstn_to_core), + .cpu_rstn (cpu_rstn_to_core), + .rstn_sw4 (ddr_rstn_to_core), .dft_lgc_rst_n (1'b1), .dft_se (1'b0), .chip_mode_i (2'b00), // normal mode @@ -380,24 +416,8 @@ core_def core_def // .qspi_mi2(qspi_mi2), // .qspi_mi3(qspi_mi3), - // sdmmc - .sd_card_clk_out (sdmmc_cclk_card), - .sd_cmd_out (sdmmc_sd_cmd_out), - .sd_cmd_out_oe (sdmmc_sd_cmd_out_en), - .sd_dat_out (sdmmc_sd_dat_out), - .sd_dat_out_oe (sdmmc_sd_dat_out_en), - .uhs1_drv_sth (sdmmc_uhs1_drv_sth), - .uhs1_swvolt_en (sdmmc_uhs1_swvolt_en), - .sd_vdd1_on (sdmmc_sd_vdd1_on), - .sd_vdd1_sel (sdmmc_sd_vdd1_sel), - .sd_card_det_in (sdmmc_card_detect_n), - .sd_card_wp_in (sdmmc_card_write_prot), - .sd_cmd_in (sdmmc_sd_cmd_in), - .sd_dat_in (sdmmc_sd_dat_in), - .sd_led_control ( ), - - `ifdef XS_GMAC - // gmac +`ifdef XS_GMAC + // GMAC .io_gmac_mdo_oe ( io_gmac_mdo_oe ), .io_gmac_mdo ( io_gmac_mdo ), .io_gmac_mck_out ( io_gmac_mck_out ), @@ -408,9 +428,10 @@ core_def core_def .io_gmac_rxd_vld ( io_gmac_rxd_vld ), .io_gmac_rxd ( io_gmac_rxd ), .io_gmac_txd ( io_gmac_txd ), - `endif +`endif - // ddr +`ifndef UVHS + // DDR .DDR_CK_T (DDR0_CK_T ), .DDR_CK_C (DDR0_CK_C ), .DDR_CKE (DDR0_CKE ), @@ -424,31 +445,24 @@ core_def core_def .DDR_DM_N (DDR0_DM ), .DDR_DQ (DDR0_DQ ), .DDR_DQS_T (DDR0_DQS_T ), - .DDR_DQS_C (DDR0_DQS_C )/*, - .DDR_ZQ (DDR0_ZQ), - .gmac_gmii_mdc_o(gmac_gmii_mdc_o), - .gmac_gmii_mdo_o(gmac_gmii_mdo_o), - .gmac_gmii_mdo_o_e(gmac_gmii_mdo_o_e), - .gmac_clk_tx_o(gmac_clk_tx_o), - .gmac_phy_txd(gmac_phy_txd), - .gmac_phy_txen(gmac_phy_txen), - .gmac_gmii_mdi_i(gmac_gmii_mdi_i), - .gmac_clk_rx_i(gmac_clk_rx_i), - .gmac_phy_rxd(gmac_phy_rxd), - .gmac_phy_rxdv(gmac_phy_rxdv), - - .gpio_porta_ddr(gpio_porta_ddr), - .gpio_porta_dr(gpio_porta_dr), - .gpio_ext_porta(gpio_ext_porta), - - .jtag_tck(jtag_tck), - .jtag_tdi(jtag_tdi), - .jtag_tms(jtag_tms), - .jtag_trstn(jtag_trstn), - .jtag_tdo(jtag_tdo), - - */ + .DDR_DQS_C (DDR0_DQS_C ), +`endif + // SDMMC + .sd_card_clk_out (sdmmc_cclk_card), + .sd_cmd_out (sdmmc_sd_cmd_out), + .sd_cmd_out_oe (sdmmc_sd_cmd_out_en), + .sd_dat_out (sdmmc_sd_dat_out), + .sd_dat_out_oe (sdmmc_sd_dat_out_en), + .uhs1_drv_sth (sdmmc_uhs1_drv_sth), + .uhs1_swvolt_en (sdmmc_uhs1_swvolt_en), + .sd_vdd1_on (sdmmc_sd_vdd1_on), + .sd_vdd1_sel (sdmmc_sd_vdd1_sel), + .sd_card_det_in (sdmmc_card_detect_n), + .sd_card_wp_in (sdmmc_card_write_prot), + .sd_cmd_in (sdmmc_sd_cmd_in), + .sd_dat_in (sdmmc_sd_dat_in), + .sd_led_control () ); //--- diff --git a/fpga_diff/src/rtl/kmh/SimTop_wrapper.sv b/fpga_diff/src/rtl/kmh/SimTop_wrapper.sv index 8e7c5f93..d909dc4c 100755 --- a/fpga_diff/src/rtl/kmh/SimTop_wrapper.sv +++ b/fpga_diff/src/rtl/kmh/SimTop_wrapper.sv @@ -250,6 +250,11 @@ wire [149:0] trace_iaddr; wire [11:0] trace_itype; wire [20:0] trace_iretire; wire [2:0] trace_ilastsize; +wire [47:0] difftest_mem_awaddr_int; +wire [47:0] difftest_mem_araddr_int; + +assign mem_core_awaddr = difftest_mem_awaddr_int[35:0]; +assign mem_core_araddr = difftest_mem_araddr_int[35:0]; `ifndef CONFIG_SIMTOP_HAS_DMA assign dma_core_awready = 1'b0; @@ -275,7 +280,7 @@ SimTop u_XSTop( .peripheral_awready (peri_awready ), .peripheral_awvalid (peri_awvalid ), .peripheral_awid (peri_awid ), - .peripheral_awaddr ({16'd0, peri_awaddr}), + .peripheral_awaddr (peri_awaddr ), .peripheral_awlen (peri_awlen ), .peripheral_awsize (peri_awsize ), .peripheral_awburst (peri_awburst ), @@ -295,7 +300,7 @@ SimTop u_XSTop( .peripheral_arready (peri_arready ), .peripheral_arvalid (peri_arvalid ), .peripheral_arid (peri_arid ), - .peripheral_araddr ({16'd0, peri_araddr}), + .peripheral_araddr (peri_araddr ), .peripheral_arlen (peri_arlen ), .peripheral_arsize (peri_arsize ), .peripheral_arburst (peri_arburst ), @@ -313,7 +318,7 @@ SimTop u_XSTop( .dma_awready (dma_core_awready ), .dma_awvalid (dma_core_awvalid ), .dma_awid (dma_core_awid ), - .dma_awaddr (dma_core_awaddr[35:0] ), + .dma_awaddr ({12'b0, dma_core_awaddr}), .dma_awlen (dma_core_awlen ), .dma_awsize (dma_core_awsize ), .dma_awburst (dma_core_awburst ), @@ -333,7 +338,7 @@ SimTop u_XSTop( .dma_arready (dma_core_arready ), .dma_arvalid (dma_core_arvalid ), .dma_arid (dma_core_arid ), - .dma_araddr (dma_core_araddr[35:0] ), + .dma_araddr ({12'b0, dma_core_araddr}), .dma_arlen (dma_core_arlen ), .dma_arsize (dma_core_arsize ), .dma_arburst (dma_core_arburst ), @@ -348,9 +353,16 @@ SimTop u_XSTop( .dma_rresp (dma_core_rresp ), .dma_rlast (dma_core_rlast ), `endif +`ifdef UVHS + // UVHS does not expose XiangShan's SystemJTAG pins. + .io_systemjtag_jtag_TCK (1'b0), + .io_systemjtag_jtag_TMS (1'b1), + .io_systemjtag_jtag_TDI (1'b0), +`else .io_systemjtag_jtag_TCK (io_systemjtag_jtag_TCK), .io_systemjtag_jtag_TMS (io_systemjtag_jtag_TMS), .io_systemjtag_jtag_TDI (io_systemjtag_jtag_TDI), +`endif .io_systemjtag_jtag_TDO_data (io_systemjtag_jtag_TDO_data), .io_systemjtag_jtag_TDO_driven (io_systemjtag_jtag_TDO_driven), .io_systemjtag_reset (io_systemjtag_reset), @@ -370,7 +382,7 @@ SimTop u_XSTop( .io_pll0_ctrl_5 (io_pll0_ctrl_5), .io_extIntrs (io_extIntrs ), .io_rtc_clock (tmclk), - .io_riscv_rst_vec_0 (38'h10000000), + .io_riscv_rst_vec_0 (48'h0000_1000_0000), //difftest @@ -413,7 +425,7 @@ SimTop u_XSTop( .difftest_mem_awvalid (mem_core_awvalid ), .difftest_mem_awid (mem_core_awid ), .difftest_mem_awuser (), - .difftest_mem_awaddr ({12'd0, mem_core_awaddr}), + .difftest_mem_awaddr (difftest_mem_awaddr_int), .difftest_mem_awlen (mem_core_awlen ), .difftest_mem_awsize (mem_core_awsize ), .difftest_mem_awburst (mem_core_awburst ), @@ -435,7 +447,7 @@ SimTop u_XSTop( .difftest_mem_arvalid (mem_core_arvalid ), .difftest_mem_arid (mem_core_arid ), .difftest_mem_aruser (), - .difftest_mem_araddr ({12'd0, mem_core_araddr}), + .difftest_mem_araddr (difftest_mem_araddr_int), .difftest_mem_arlen (mem_core_arlen ), .difftest_mem_arsize (mem_core_arsize ), .difftest_mem_arburst (mem_core_arburst ), diff --git a/fpga_diff/src/tcl/common/AXI_bridge.tcl b/fpga_diff/src/tcl/common/AXI_bridge.tcl index c79b8654..f0f37217 100644 --- a/fpga_diff/src/tcl/common/AXI_bridge.tcl +++ b/fpga_diff/src/tcl/common/AXI_bridge.tcl @@ -190,6 +190,7 @@ proc create_root_design { parentCell } { # Set parent object as current current_bd_instance $parentObj + set uvhs_flow [expr {[info exists ::env(UVHS_FLOW)] && $::env(UVHS_FLOW) eq "1"}] # Create interface ports set S00_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI ] @@ -224,6 +225,40 @@ proc create_root_design { parentCell } { CONFIG.WUSER_WIDTH {0} \ ] $S00_AXI + if {$uvhs_flow} { + set UVHS_FLASH_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 UVHS_FLASH_AXI ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {64} \ + CONFIG.FREQ_HZ {25000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {8} \ + CONFIG.MAX_BURST_LENGTH {16} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI3} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $UVHS_FLASH_AXI + } + set SYS_CFG_APB [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:apb_rtl:1.0 SYS_CFG_APB ] set UART_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 UART_0 ] @@ -247,14 +282,29 @@ proc create_root_design { parentCell } { # Create ports set ACLK [ create_bd_port -dir I -type clk -freq_hz 25000000 ACLK ] + set aclk_busif rom_axi + if {$uvhs_flow} { + append aclk_busif :UVHS_FLASH_AXI + } set_property -dict [ list \ - CONFIG.ASSOCIATED_BUSIF {rom_axi} \ - ] $ACLK + CONFIG.ASSOCIATED_BUSIF $aclk_busif \ + ] $ACLK set ARESETN [ create_bd_port -dir I -type rst ARESETN ] set SYS_INTER_CLK [ create_bd_port -dir I -type clk -freq_hz 25000000 SYS_INTER_CLK ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ - ] $SYS_INTER_CLK + ] $SYS_INTER_CLK + if {$uvhs_flow} { + set_property CONFIG.ASSOCIATED_RESET {ARESETN} $ACLK + set_property CONFIG.POLARITY {ACTIVE_LOW} $ARESETN + set_property CONFIG.ASSOCIATED_RESET {SYS_INTER_ARESETN} $SYS_INTER_CLK + set SYS_INTER_ARESETN [ create_bd_port -dir I -type rst SYS_INTER_ARESETN ] + set_property CONFIG.POLARITY {ACTIVE_LOW} $SYS_INTER_ARESETN + set UART_ACLK [ create_bd_port -dir I -type clk -freq_hz 50000000 UART_ACLK ] + set UART_ARESETN [ create_bd_port -dir I -type rst UART_ARESETN ] + set_property CONFIG.ASSOCIATED_RESET {UART_ARESETN} $UART_ACLK + set_property CONFIG.POLARITY {ACTIVE_LOW} $UART_ARESETN + } set uart0_intc [ create_bd_port -dir O -type intr uart0_intc ] # Create instance: axi_apb_bridge_0, and set properties @@ -266,9 +316,10 @@ proc create_root_design { parentCell } { # Create instance: axi_interconnect_0, and set properties set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set axi_slave_count [expr {$uvhs_flow ? 3 : 2}] set_property -dict [ list \ CONFIG.NUM_MI {4} \ - CONFIG.NUM_SI {2} \ + CONFIG.NUM_SI $axi_slave_count \ ] $axi_interconnect_0 # Create instance: extllc_bram_ctrl, and set properties @@ -322,12 +373,59 @@ proc create_root_design { parentCell } { connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins axi_interconnect_0/M03_AXI] [get_bd_intf_pins extllc_bram_ctrl/S_AXI] connect_bd_intf_net -intf_net extllc_bram_ctrl_BRAM_PORTA [get_bd_intf_pins extllc_bram_ctrl/BRAM_PORTA] [get_bd_intf_pins extllc_bram/BRAM_PORTA] connect_bd_intf_net -intf_net jtag_axi_flash_M_AXI [get_bd_intf_pins axi_interconnect_0/S01_AXI] [get_bd_intf_pins jtag_axi_flash/M_AXI] + if {$uvhs_flow} { + connect_bd_intf_net -intf_net UVHS_FLASH_AXI_0_1 [get_bd_intf_ports UVHS_FLASH_AXI] [get_bd_intf_pins axi_interconnect_0/S02_AXI] + } connect_bd_intf_net -intf_net axi_uart16550_0_UART [get_bd_intf_ports UART_0] [get_bd_intf_pins axi_uart16550_0/UART] # Create port connections - connect_bd_net -net ACLK_0_1 [get_bd_ports ACLK] [get_bd_pins axi_apb_bridge_0/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins extllc_bram_ctrl/s_axi_aclk] [get_bd_pins jtag_axi_flash/aclk] - connect_bd_net -net ARESETN_0_1 [get_bd_ports ARESETN] [get_bd_pins axi_apb_bridge_0/s_axi_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_uart16550_0/s_axi_aresetn] [get_bd_pins extllc_bram_ctrl/s_axi_aresetn] [get_bd_pins jtag_axi_flash/aresetn] + set aclk_pins [list \ + [get_bd_pins axi_apb_bridge_0/s_axi_aclk] \ + [get_bd_pins axi_interconnect_0/ACLK] \ + [get_bd_pins axi_interconnect_0/M00_ACLK] \ + [get_bd_pins axi_interconnect_0/M02_ACLK] \ + [get_bd_pins axi_interconnect_0/M03_ACLK] \ + [get_bd_pins axi_interconnect_0/S01_ACLK] \ + [get_bd_pins extllc_bram_ctrl/s_axi_aclk] \ + [get_bd_pins jtag_axi_flash/aclk] \ + ] + if {$uvhs_flow} { + lappend aclk_pins [get_bd_pins axi_interconnect_0/S02_ACLK] + } else { + lappend aclk_pins \ + [get_bd_pins axi_interconnect_0/M01_ACLK] \ + [get_bd_pins axi_uart16550_0/s_axi_aclk] + } + connect_bd_net -net ACLK_0_1 [get_bd_ports ACLK] {*}$aclk_pins + set aresetn_pins [list \ + [get_bd_pins axi_apb_bridge_0/s_axi_aresetn] \ + [get_bd_pins axi_interconnect_0/ARESETN] \ + [get_bd_pins axi_interconnect_0/M00_ARESETN] \ + [get_bd_pins axi_interconnect_0/M02_ARESETN] \ + [get_bd_pins axi_interconnect_0/M03_ARESETN] \ + [get_bd_pins axi_interconnect_0/S01_ARESETN] \ + [get_bd_pins extllc_bram_ctrl/s_axi_aresetn] \ + [get_bd_pins jtag_axi_flash/aresetn] \ + ] + if {!$uvhs_flow} { + lappend aresetn_pins \ + [get_bd_pins axi_interconnect_0/S00_ARESETN] \ + [get_bd_pins axi_interconnect_0/M01_ARESETN] \ + [get_bd_pins axi_uart16550_0/s_axi_aresetn] + } else { + lappend aresetn_pins [get_bd_pins axi_interconnect_0/S02_ARESETN] + } + connect_bd_net -net ARESETN_0_1 [get_bd_ports ARESETN] {*}$aresetn_pins connect_bd_net -net SYS_INTER_CLK_1 [get_bd_ports SYS_INTER_CLK] [get_bd_pins axi_interconnect_0/S00_ACLK] + if {$uvhs_flow} { + connect_bd_net -net SYS_INTER_ARESETN_1 [get_bd_ports SYS_INTER_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] + connect_bd_net -net UART_ACLK_1 [get_bd_ports UART_ACLK] \ + [get_bd_pins axi_interconnect_0/M01_ACLK] \ + [get_bd_pins axi_uart16550_0/s_axi_aclk] + connect_bd_net -net UART_ARESETN_1 [get_bd_ports UART_ARESETN] \ + [get_bd_pins axi_interconnect_0/M01_ARESETN] \ + [get_bd_pins axi_uart16550_0/s_axi_aresetn] + } connect_bd_net -net axi_uart16550_0_ip2intc_irpt [get_bd_ports uart0_intc] [get_bd_pins axi_uart16550_0/ip2intc_irpt] connect_bd_net -net xlconstant_0_dout [get_bd_pins axi_uart16550_0/freeze] [get_bd_pins xlconstant_0/dout] @@ -340,6 +438,12 @@ proc create_root_design { parentCell } { exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces jtag_axi_flash/Data] [get_bd_addr_segs SYS_CFG_APB/Reg] exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces jtag_axi_flash/Data] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces jtag_axi_flash/Data] [get_bd_addr_segs extllc_bram_ctrl/S_AXI/Mem0] + if {$uvhs_flow} { + assign_bd_address -offset 0x00000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces UVHS_FLASH_AXI] [get_bd_addr_segs rom_axi/Reg] -force + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces UVHS_FLASH_AXI] [get_bd_addr_segs SYS_CFG_APB/Reg] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces UVHS_FLASH_AXI] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces UVHS_FLASH_AXI] [get_bd_addr_segs extllc_bram_ctrl/S_AXI/Mem0] + } # Restore current instance diff --git a/fpga_diff/src/tcl/common/defines.tcl b/fpga_diff/src/tcl/common/defines.tcl index a2ee1721..5e3a1a6b 100755 --- a/fpga_diff/src/tcl/common/defines.tcl +++ b/fpga_diff/src/tcl/common/defines.tcl @@ -1,9 +1,5 @@ set defines [list \ XIANGSHAN_FPGA \ - RANDOMIZE_GARBAGE_ASSIGN \ - RANDOMIZE_REG_INIT \ - RANDOMIZE_MEM_INIT \ - RANDOMIZE_DELAY=1 \ DDR4_16G_X8 \ DQ64 \ DDR4_2400 \ diff --git a/fpga_diff/src/tcl/common/xdma_ep.tcl b/fpga_diff/src/tcl/common/xdma_ep.tcl index feee4ad8..d254ba7a 100644 --- a/fpga_diff/src/tcl/common/xdma_ep.tcl +++ b/fpga_diff/src/tcl/common/xdma_ep.tcl @@ -174,6 +174,18 @@ proc env_choice {name default allowed} { return $value } +proc env_positive_integer {name default} { + set value $default + if {[info exists ::env($name)] && [string trim $::env($name)] ne ""} { + set value [string trim $::env($name)] + } + if {![string is integer -strict $value] || $value <= 0} { + error "$name must be a positive integer, got '$value'" + } + puts "INFO: $name=$value" + return $value +} + if { $bCheckIPs == 1 } { common::send_gid_msg -ssname BD::TCL -id 2058 -severity "INFO" "Current scripts_vivado_version value: '$::vivado_version'" @@ -221,6 +233,13 @@ proc create_root_design { parentCell } { variable xdma_vlnv variable util_vlnv set xdma_link_width [env_choice XDMA_LINK_WIDTH X4 {X4 X8}] + set uvhs_flow [expr {[info exists ::env(UVHS_FLOW)] && $::env(UVHS_FLOW) eq "1"}] + if {$uvhs_flow} { + set xdma_enable_pf0_bar1 [env_choice XDMA_ENABLE_PF0_BAR1 1 {0 1}] + set xdma_axilite_master_scale [env_choice XDMA_AXILITE_MASTER_SCALE Kilobytes {Kilobytes Megabytes Gigabytes}] + set xdma_axilite_master_size [env_positive_integer XDMA_AXILITE_MASTER_SIZE 512] + set xdma_pf0_bar1_enabled [expr {$xdma_enable_pf0_bar1 eq "1" ? "true" : "false"}] + } set xdma_lane_count [string range $xdma_link_width 1 end] set xdma_lane_msb [expr {$xdma_lane_count - 1}] if {$xdma_link_width eq "X4"} { @@ -378,6 +397,16 @@ proc create_root_design { parentCell } { error "Unsupported XDMA IP version: $xdma_vlnv (only 4.1 or 4.2 supported)" } + if {$uvhs_flow} { + set_property -dict [list \ + CONFIG.axilite_master_scale $xdma_axilite_master_scale \ + CONFIG.axilite_master_size $xdma_axilite_master_size \ + CONFIG.pf0_bar1_enabled $xdma_pf0_bar1_enabled \ + CONFIG.pf0_bar1_scale {Kilobytes} \ + CONFIG.pf0_bar1_size {64} \ + ] $xdma_0 + } + puts "INFO: wiring XDMA ST interfaces directly on axi_aclk" # Create interface connections diff --git a/fpga_diff/tools/rtl_filelist_lib.sh b/fpga_diff/tools/rtl_filelist_lib.sh new file mode 100644 index 00000000..1ff7ca46 --- /dev/null +++ b/fpga_diff/tools/rtl_filelist_lib.sh @@ -0,0 +1,168 @@ +#!/usr/bin/env bash + +# Shared RTL_INCLUDE parser. Call rtl_flist_parse_inputs BASE_DIR INPUT... +# after sourcing this file, then consume rtl_flist_files and +# rtl_flist_include_dirs. + +declare -a rtl_flist_files=() +declare -a rtl_flist_include_dirs=() +declare -A rtl_flist_seen_files=() +declare -A rtl_flist_seen_dirs=() +declare -A rtl_flist_active_lists=() + +rtl_flist_fail() { + echo "ERROR: $*" >&2 + exit 1 +} + +rtl_flist_resolve_path() { + local base_dir=$1 + local path=$2 + + if [[ $path != /* ]]; then + path="$base_dir/$path" + fi + realpath -e -- "$path" +} + +rtl_flist_add_include_dir() { + local base_dir=$1 + local path=$2 + local resolved + + resolved=$(rtl_flist_resolve_path "$base_dir" "$path") || + rtl_flist_fail "RTL include directory not found: $path" + [[ -d $resolved ]] || rtl_flist_fail "RTL include path is not a directory: $path" + if [[ -z ${rtl_flist_seen_dirs[$resolved]+x} ]]; then + rtl_flist_seen_dirs[$resolved]=1 + rtl_flist_include_dirs+=("$resolved") + fi +} + +rtl_flist_add_file() { + local base_dir=$1 + local path=$2 + local resolved + + resolved=$(rtl_flist_resolve_path "$base_dir" "$path") || + rtl_flist_fail "RTL source not found: $path" + [[ -f $resolved ]] || rtl_flist_fail "RTL source is not a file: $path" + case $resolved in + *.v|*.sv|*.vh|*.svh) ;; + *) rtl_flist_fail "unsupported RTL source: $path" ;; + esac + + if [[ -z ${rtl_flist_seen_files[$resolved]+x} ]]; then + rtl_flist_seen_files[$resolved]=1 + rtl_flist_files+=("$resolved") + fi + rtl_flist_add_include_dir / "$(dirname -- "$resolved")" +} + +rtl_flist_add_dir() { + local base_dir=$1 + local path=$2 + local recursive=$3 + local resolved + local -a find_depth=() + + resolved=$(rtl_flist_resolve_path "$base_dir" "$path") || + rtl_flist_fail "RTL directory not found: $path" + [[ -d $resolved ]] || rtl_flist_fail "RTL path is not a directory: $path" + rtl_flist_add_include_dir / "$resolved" + if [[ $recursive == 0 ]]; then + find_depth=(-maxdepth 1) + fi + while IFS= read -r -d '' rtl_file; do + rtl_flist_add_file / "$rtl_file" + done < <( + find "$resolved" "${find_depth[@]}" -type f \ + \( -name '*.v' -o -name '*.sv' -o -name '*.vh' -o -name '*.svh' \) \ + -print0 | LC_ALL=C sort -z + ) +} + +rtl_flist_parse_filelist() { + local caller_dir=$1 + local path=$2 + local filelist + local filelist_dir + local line + local token + local pending="" + local value + local -a tokens=() + local -a values=() + + filelist=$(rtl_flist_resolve_path "$caller_dir" "$path") || + rtl_flist_fail "RTL file list not found: $path" + [[ -f $filelist ]] || rtl_flist_fail "RTL file list is not a file: $path" + if [[ -n ${rtl_flist_active_lists[$filelist]+x} ]]; then + rtl_flist_fail "recursive RTL file list: $filelist" + fi + + rtl_flist_active_lists[$filelist]=1 + filelist_dir=$(dirname -- "$filelist") + while IFS= read -r line || [[ -n $line ]]; do + line=${line%$'\r'} + line=${line%%//*} + line=${line%%#*} + read -r -a tokens <<< "$line" + for token in "${tokens[@]}"; do + if [[ -n $pending ]]; then + case $pending in + filelist) rtl_flist_parse_filelist "$filelist_dir" "$token" ;; + library) rtl_flist_add_dir "$filelist_dir" "$token" 0 ;; + source) rtl_flist_add_file "$filelist_dir" "$token" ;; + include) rtl_flist_add_include_dir "$filelist_dir" "$token" ;; + esac + pending="" + continue + fi + + case $token in + -f|-F) pending=filelist ;; + -y) pending=library ;; + -v) pending=source ;; + -I) pending=include ;; + -f*|-F*) rtl_flist_parse_filelist "$filelist_dir" "${token:2}" ;; + -y*) rtl_flist_add_dir "$filelist_dir" "${token:2}" 0 ;; + -v*) rtl_flist_add_file "$filelist_dir" "${token:2}" ;; + -I*) rtl_flist_add_include_dir "$filelist_dir" "${token:2}" ;; + +incdir+*) + IFS=+ read -r -a values <<< "${token#+incdir+}" + for value in "${values[@]}"; do + [[ -n $value ]] && rtl_flist_add_include_dir "$filelist_dir" "$value" + done + ;; + +libext+*) ;; + *.v|*.sv|*.vh|*.svh) rtl_flist_add_file "$filelist_dir" "$token" ;; + *) rtl_flist_fail "unsupported option in $filelist: $token" ;; + esac + done + done < "$filelist" + [[ -z $pending ]] || rtl_flist_fail "missing argument after file-list option in $filelist" + unset 'rtl_flist_active_lists[$filelist]' +} + +rtl_flist_parse_inputs() { + local base_dir=$1 + local input + local resolved + shift + + for input in "$@"; do + resolved=$(rtl_flist_resolve_path "$base_dir" "$input") || + rtl_flist_fail "RTL_INCLUDE path not found: $input" + if [[ -d $resolved ]]; then + rtl_flist_add_dir / "$resolved" 1 + elif [[ -f $resolved ]]; then + case $input in + *.f|*.flist|*.list) rtl_flist_parse_filelist / "$resolved" ;; + *) rtl_flist_add_file / "$resolved" ;; + esac + else + rtl_flist_fail "RTL_INCLUDE path not found: $input" + fi + done +} diff --git a/fpga_diff/tools/update_core_flist.sh b/fpga_diff/tools/update_core_flist.sh index 47a0100f..f793d058 100755 --- a/fpga_diff/tools/update_core_flist.sh +++ b/fpga_diff/tools/update_core_flist.sh @@ -2,202 +2,164 @@ set -euo pipefail -fail() { - echo "ERROR: $*" >&2 - exit 1 -} - usage() { - echo "Usage: $0 CORE_DIR [--] [RTL_INCLUDE ...]" >&2 + cat >&2 <<'EOF' +Usage: + update_core_flist.sh vivado CORE_DIR [--] [RTL_INCLUDE ...] + update_core_flist.sh uvhs CORE_DIR WORK_DIR CPU OUTPUT [--] [RTL_INCLUDE ...] +EOF exit 2 } -[[ $# -ge 1 ]] || usage +script_dir=$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")" && pwd) +fpga_diff_dir=$(cd -- "$script_dir/.." && pwd) +source "$script_dir/rtl_filelist_lib.sh" -core_dir=$1 -shift -if [[ ${1:-} == -- ]]; then +generate_vivado_filelist() { + local core_dir=$1 + local output=$fpga_diff_dir/src/tcl/cpu_files.tcl + local tmp_dir + local tmp_output shift -fi - -[[ -d $core_dir ]] || fail "CORE_DIR is not a directory: $core_dir" -fpga_diff_dir=$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/.." && pwd) -awk_script="$fpga_diff_dir/core_flist.awk" -output_tcl="$fpga_diff_dir/src/tcl/cpu_files.tcl" -tmp_dir=$(mktemp -d) -trap 'rm -rf "$tmp_dir"' EXIT - -declare -a rtl_files=() -declare -a rtl_include_dirs=() -declare -A seen_files=() -declare -A seen_dirs=() -declare -A active_filelists=() - -resolve_path() { - local base_dir=$1 - local path=$2 - - if [[ $path != /* ]]; then - path="$base_dir/$path" + [[ -d $core_dir ]] || rtl_flist_fail "CORE_DIR is not a directory: $core_dir" + core_dir=$(realpath -e -- "$core_dir") + rtl_flist_parse_inputs "$PWD" "$@" + + tmp_dir=$(mktemp -d) + trap 'rm -rf "$tmp_dir"' RETURN + find "$core_dir" -path "$core_dir/rtl/verification" -prune -o \ + -type f \( -name '*.v' -o -name '*.sv' -o -name '*.vh' -o -name '*.svh' \) \ + -print | LC_ALL=C sort > "$tmp_dir/cpu_files" + : > "$tmp_dir/rtl_files" + : > "$tmp_dir/rtl_include_dirs" + if ((${#rtl_flist_files[@]})); then + printf '%s\n' "${rtl_flist_files[@]}" > "$tmp_dir/rtl_files" fi - realpath -e -- "$path" -} - -add_include_dir() { - local base_dir=$1 - local path=$2 - local resolved - - resolved=$(resolve_path "$base_dir" "$path") || - fail "RTL include directory not found: $path" - [[ -d $resolved ]] || fail "RTL include path is not a directory: $path" - if [[ -z ${seen_dirs[$resolved]+x} ]]; then - seen_dirs[$resolved]=1 - rtl_include_dirs+=("$resolved") + if ((${#rtl_flist_include_dirs[@]})); then + printf '%s\n' "${rtl_flist_include_dirs[@]}" > "$tmp_dir/rtl_include_dirs" fi -} - -add_rtl_file() { - local base_dir=$1 - local path=$2 - local resolved - resolved=$(resolve_path "$base_dir" "$path") || fail "RTL source not found: $path" - [[ -f $resolved ]] || fail "RTL source is not a file: $path" - case $resolved in - *.v|*.sv|*.vh|*.svh) ;; - *) - fail "unsupported RTL source: $path" - ;; - esac - - if [[ -z ${seen_files[$resolved]+x} ]]; then - seen_files[$resolved]=1 - rtl_files+=("$resolved") - fi - add_include_dir / "$(dirname -- "$resolved")" + tmp_output=$tmp_dir/cpu_files.tcl + awk -v var=cpu_files -v detect_simtop_dma=1 -f "$fpga_diff_dir/core_flist.awk" \ + "$tmp_dir/cpu_files" > "$tmp_output" + awk -v var=rtl_include_files -f "$fpga_diff_dir/core_flist.awk" \ + "$tmp_dir/rtl_files" >> "$tmp_output" + awk -v var=rtl_include_dirs -f "$fpga_diff_dir/core_flist.awk" \ + "$tmp_dir/rtl_include_dirs" >> "$tmp_output" + mkdir -p "$(dirname -- "$output")" + mv -- "$tmp_output" "$output" + echo "INFO: generated $output with ${#rtl_flist_files[@]} external RTL files" } -add_rtl_dir() { - local base_dir=$1 - local path=$2 - local recursive=$3 - local resolved - local -a find_depth=() - - resolved=$(resolve_path "$base_dir" "$path") || fail "RTL directory not found: $path" - [[ -d $resolved ]] || fail "RTL path is not a directory: $path" - add_include_dir / "$resolved" - if [[ $recursive == 0 ]]; then - find_depth=(-maxdepth 1) - fi - while IFS= read -r -d '' rtl_file; do - add_rtl_file / "$rtl_file" - done < <( - find "$resolved" "${find_depth[@]}" -type f \ +generate_uvhs_filelist() { + local core_dir=$1 + local work_dir=$2 + local cpu=$3 + local output=$4 + local core_rtl_dir + local core_generated_dir + local module_name + local source_file + local found + local tmp_dir + local tmp_output + local -a required_modules=() + shift 4 + + core_dir=$(realpath -e -- "$core_dir") + work_dir=$(realpath -e -- "$work_dir") + core_rtl_dir=$core_dir/rtl + core_generated_dir=$core_dir/generated-src + [[ -d $core_rtl_dir ]] || rtl_flist_fail "FPGA release RTL not found: $core_rtl_dir" + rtl_flist_parse_inputs "$PWD" "$@" + + mkdir -p "$(dirname -- "$output")" + tmp_dir=$(mktemp -d) + trap 'rm -rf "$tmp_dir"' RETURN + tmp_output=$tmp_dir/filelist.f + + { + printf '+define+SYNTHESIS\n+define+XIANGSHAN_FPGA\n+define+UVHS\n' + printf '+define+DDR4_16G_X8\n+define+DQ64\n+define+DDR4_2400\n' + printf '+define+DQ=64\n+define+MICRON_DDR\n+define+DDR4_16Gbx8\n' + printf '+define+DDR4\n+define+SRAM_SYN\n+define+DATA_VERSION=0\n' + if [[ $cpu == nutshell ]]; then + printf '+define+CPU_NUTSHELL\n' + fi + if [[ $cpu == kmh ]] && + grep -Eq '^[[:space:]]*(input|output)[[:space:]].*dma_awready' "$core_rtl_dir/SimTop.sv"; then + printf '+define+CONFIG_SIMTOP_HAS_DMA\n' + fi + + printf '+incdir+%s\n' "$core_dir" "$core_rtl_dir" + if [[ -d $core_generated_dir ]]; then + printf '+incdir+%s\n' "$core_generated_dir" + fi + printf '+incdir+%s/src/rtl/common\n' "$fpga_diff_dir" + + find "$fpga_diff_dir/src/rtl/common" -type f \ \( -name '*.v' -o -name '*.sv' -o -name '*.vh' -o -name '*.svh' \) \ - -print0 | LC_ALL=C sort -z - ) -} - -parse_filelist() { - local caller_dir=$1 - local path=$2 - local filelist - local filelist_dir - local line - local token - local pending="" - local value - local -a tokens=() - local -a values=() - - filelist=$(resolve_path "$caller_dir" "$path") || - fail "RTL file list not found: $path" - [[ -f $filelist ]] || fail "RTL file list is not a file: $path" - if [[ -n ${active_filelists[$filelist]+x} ]]; then - fail "recursive RTL file list: $filelist" - fi - - active_filelists[$filelist]=1 - filelist_dir=$(dirname -- "$filelist") - # Match -F semantics: relative entries belong to the containing file list. - while IFS= read -r line || [[ -n $line ]]; do - line=${line%$'\r'} - line=${line%%//*} - line=${line%%#*} - read -r -a tokens <<< "$line" - for token in "${tokens[@]}"; do - if [[ -n $pending ]]; then - case $pending in - filelist) parse_filelist "$filelist_dir" "$token" ;; - library) add_rtl_dir "$filelist_dir" "$token" 0 ;; - source) add_rtl_file "$filelist_dir" "$token" ;; - include) add_include_dir "$filelist_dir" "$token" ;; - esac - pending="" - continue + ! -name 'u0_xdma.v' -print | LC_ALL=C sort + if [[ -d $work_dir/rtl/stubs ]]; then + find "$work_dir/rtl/stubs" -type f -name '*.v' -print | LC_ALL=C sort + fi + if [[ -d $fpga_diff_dir/src/rtl/$cpu ]]; then + find "$fpga_diff_dir/src/rtl/$cpu" -type f \ + \( -name '*.v' -o -name '*.sv' -o -name '*.vh' -o -name '*.svh' \) \ + -print | LC_ALL=C sort + fi + find "$core_rtl_dir" -type f \ + \( -name '*.v' -o -name '*.sv' -o -name '*.vh' -o -name '*.svh' \) \ + -print | LC_ALL=C sort + if ((${#rtl_flist_include_dirs[@]})); then + printf '+incdir+%s\n' "${rtl_flist_include_dirs[@]}" + fi + if ((${#rtl_flist_files[@]})); then + printf '%s\n' "${rtl_flist_files[@]}" + fi + } > "$tmp_output" + + mv -- "$tmp_output" "$output" + case $cpu in + kmh|nutshell) required_modules=(SimTop) ;; + nanhu) required_modules=(XlnFpgaTop) ;; + esac + for module_name in "${required_modules[@]}"; do + found=0 + while IFS= read -r source_file; do + [[ $source_file != +* && -f $source_file ]] || continue + if grep -Eq "^[[:space:]]*module[[:space:]]+$module_name([[:space:]#(]|$)" "$source_file"; then + found=1 + break fi - - case $token in - -f|-F) pending=filelist ;; - -y) pending=library ;; - -v) pending=source ;; - -I) pending=include ;; - -f*|-F*) parse_filelist "$filelist_dir" "${token:2}" ;; - -y*) add_rtl_dir "$filelist_dir" "${token:2}" 0 ;; - -v*) add_rtl_file "$filelist_dir" "${token:2}" ;; - -I*) add_include_dir "$filelist_dir" "${token:2}" ;; - +incdir+*) - IFS=+ read -r -a values <<< "${token#+incdir+}" - for value in "${values[@]}"; do - [[ -n $value ]] && add_include_dir "$filelist_dir" "$value" - done - ;; - +libext+*) ;; - *.v|*.sv|*.vh|*.svh) add_rtl_file "$filelist_dir" "$token" ;; - *) fail "unsupported option in $filelist: $token" ;; - esac - done - done < "$filelist" - [[ -z $pending ]] || fail "missing argument after file-list option in $filelist" - unset 'active_filelists[$filelist]' + done < "$output" + [[ $found == 1 ]] || rtl_flist_fail "required module not found: $module_name" + echo "INFO: found required module: $module_name" + done + echo "INFO: generated UVHS file list $output" } -for rtl_include in "$@"; do - if [[ -d $rtl_include ]]; then - add_rtl_dir "$PWD" "$rtl_include" 1 - elif [[ -f $rtl_include ]]; then - case $rtl_include in - *.f|*.flist|*.list) parse_filelist "$PWD" "$rtl_include" ;; - *) add_rtl_file "$PWD" "$rtl_include" ;; - esac - else - fail "RTL_INCLUDE path not found: $rtl_include" - fi -done - -core_dir=$(realpath -e -- "$core_dir") -find "$core_dir" -path "$core_dir/rtl/verification" -prune -o \ - -type f \( -name '*.v' -o -name '*.sv' -o -name '*.vh' -o -name '*.svh' \) \ - -print | LC_ALL=C sort > "$tmp_dir/cpu_files" -: > "$tmp_dir/rtl_files" -: > "$tmp_dir/rtl_include_dirs" -if ((${#rtl_files[@]})); then - printf '%s\n' "${rtl_files[@]}" > "$tmp_dir/rtl_files" -fi -if ((${#rtl_include_dirs[@]})); then - printf '%s\n' "${rtl_include_dirs[@]}" > "$tmp_dir/rtl_include_dirs" -fi - -tmp_output="$tmp_dir/cpu_files.tcl" -awk -v var=cpu_files -v detect_simtop_dma=1 -f "$awk_script" \ - "$tmp_dir/cpu_files" > "$tmp_output" -awk -v var=rtl_include_files -f "$awk_script" \ - "$tmp_dir/rtl_files" >> "$tmp_output" -awk -v var=rtl_include_dirs -f "$awk_script" \ - "$tmp_dir/rtl_include_dirs" >> "$tmp_output" -mv -- "$tmp_output" "$output_tcl" - -echo "INFO: generated $output_tcl with ${#rtl_files[@]} external RTL files" +mode=${1:-} +[[ -n $mode ]] || usage +shift +case $mode in + vivado) + [[ $# -ge 1 ]] || usage + core_dir=$1 + shift + [[ ${1:-} != -- ]] || shift + generate_vivado_filelist "$core_dir" "$@" + ;; + uvhs) + [[ $# -ge 4 ]] || usage + core_dir=$1 + work_dir=$2 + cpu=$3 + output=$4 + shift 4 + [[ ${1:-} != -- ]] || shift + generate_uvhs_filelist "$core_dir" "$work_dir" "$cpu" "$output" "$@" + ;; + *) usage ;; +esac diff --git a/fpga_diff/uvhs/README.md b/fpga_diff/uvhs/README.md new file mode 100644 index 00000000..c6094e00 --- /dev/null +++ b/fpga_diff/uvhs/README.md @@ -0,0 +1,366 @@ +# UVHS FPGA-Diff Flow + +This directory contains the UVHS build and runtime flow for FPGA-Diff. UVHS +commands use the `uvhs_*` prefix and do not replace the existing Vivado, PCIe, +or JTAG commands. + +## RTL Input + +Generate an FPGA release before entering `env-scripts`. `CORE_DIR` is the +release `build` directory, not the design source checkout: + +```text +design RTL -> difftest fpga-release -> /build -> env-scripts +``` + +The release step owns FPGA clock-gate replacement and generated RAM-style +conversion. The UVHS flow only consumes that result. + +`RTL_INCLUDE` accepts RTL files, directories, and nested `.f`, `.flist`, or +`.list` files. Relative entries are resolved from the file list that contains +them. Both build flows call `tools/update_core_flist.sh`, which uses +`tools/rtl_filelist_lib.sh` for parsing. Vivado mode generates +`cpu_files.tcl`; UVHS mode combines the parsed additions with release RTL and +FPGA-Diff wrappers in `filelist.f`. + +| File-list stage | Vivado | UVHS | +| --- | --- | --- | +| Shared input | `CORE_DIR` and optional `RTL_INCLUDE` | `CORE_DIR` and optional `RTL_INCLUDE` | +| Core files | Scans the complete release build, excluding `rtl/verification` | Reads release `rtl/` and optional `generated-src/` headers | +| Board wrappers and IP | Added later by `xs_uart.tcl` from Tcl lists | Written directly into the complete UVHS `filelist.f` | +| Output | Tcl variables in `src/tcl/cpu_files.tcl` | Flat uvsyn input in `/rtl/filelist.f` | +| Consumer | Vivado project creation | UVHS `read_verilog -f` | + +## Build + +```sh +make uvhs CPU= CORE_DIR=/path/to/release/build \ + RTL_INCLUDE=/path/to/extra.f SUFFIX= +``` + +`RTL_INCLUDE` is optional. `uvhs` is the stable build entry point: it runs the +frontend and backend in order, generates the per-FPGA bitstreams, and commits +the runtime database. The lower-level `uvhs_frontend` and `uvhs_backend` +targets remain available for stage reuse and debugging. `ENV_SCRIPTS_HOME` +defaults to the current `fpga_diff` directory; it only needs to be overridden +when build outputs should live elsewhere. + +`uvhs_frontend` performs these steps: + +1. Copies the vendor board template into an isolated work directory. +2. Prepares repository-owned Vivado IP and the 64-bit generalBus DCP. +3. Imports the selected DDR DCP and validates its AXI width. +4. Builds the complete RTL file list and checks the expected top module. +5. Sources an optional `UVHS_PROBE_TCL`, then elaborates and synthesizes the + design with uvsyn. +6. Registers the DDR instance used by runtime `writemem`. + +`uvhs_preflight` is an early prerequisite check, not a synthesis or hardware +test. Its loops check the three required environment variables, host commands, +the selected CPU and release directory, UVHS/Vivado executables, repository +helper scripts, board-template files, and the external DDR directory. This +keeps a missing input from being discovered after a multi-hour run has started. + +IP preparation intentionally retains two files. `prepare_ip.sh` is the outer +orchestrator for three different sources: repository Vivado IP, the vendor +Python generalBus generator, and an external DDR checkpoint. The child +`export_vivado_ip.tcl` must run inside Vivado because it uses project, IP, BD, +and checkpoint commands. Merging them would require Vivado to launch a nested +Vivado process or embedding a generated Tcl file in shell, neither of which +simplifies the execution model. + +`uvhs_backend` follows the vendor implementation sequence: clock inference and +transformation, remap, partition, localization, system routing, FPGA PnR, +timing signoff, bitstream generation, and runtime database commit. Fill-rate +validation and automatic partitioning are kept next to that sequence in +`compilation/backend_run.tcl`. + +`compilation/timing.tcl` supplies the external clocks and asynchronous groups +to the frontend. The groups are applied again after UVHS has inferred and +transformed clocks, then once more to each linked FPGA netlist before Vivado +optimization. + +The default XiangShan partition limits are 70% LUT and 35% LUT6. They can be +changed with `UVHS_LUT_FILL_RATE` and `UVHS_LUT6_FILL_RATE` for placement +experiments. `UVHS_EXPORT_IP_FORCE=1` regenerates cached Vivado and generalBus +IP. `uvhs_clean` removes only the selected work directory and refuses to run +while its runtime session is active. + +The default topology keeps the XiangShan CHI/CMN memory path, configuration +bridge, runtime flash interface, syscfg, and boot ROM with user DDR on B0/F0. +The physical UV_FMCH_FLASH USB-UART remains on B0/F1, while the core, DiffTest +endpoint, and XDMA host path stay on B0/F2. The remaining logic is partitioned +automatically. XiangShan uses these path constraints together with high +partition effort and the `uv_placer_balance_slrs` PnR strategy. + +UVHS drives the AXI UART16550 from `clk6_p` at a fixed 50 MHz. The CPU/SoC +`clk5_p` frequency comes from the system sign-off result committed in the +selected runtime database, so each partition and PnR result runs at its own +reported frequency. The fixed UART clock matches the 50 MHz clock declared by +the XiangShan FPGA device tree and keeps UART baud timing independent of CPU +clock gating. + +## Runtime + +```sh +make uvhs_write_bitstream CPU= SUFFIX= +make uvhs_runtime_status CPU= SUFFIX= +make uvhs_halt_soc CPU= SUFFIX= +make uvhs_write_ddr CPU= SUFFIX= WORKLOAD=/path/to/image.txt +make uvhs_write_flash CPU= SUFFIX= WORKLOAD=/path/to/image.bin +make uvhs_reset_cpu CPU= SUFFIX= +make uvhs_ila_arm CPU= SUFFIX= TRIGGER=/path/to/trigger.ini +make uvhs_ila CPU= SUFFIX= +make uvhs_vcd CPU= SUFFIX= +make uvhs_ila_clear CPU= SUFFIX= +make uvhs_runtime_stop CPU= SUFFIX= +``` + +`uvhs_write_bitstream` downloads the completed runtime database, initializes +the hardware, and keeps a detached UVHS session alive. Later reset and memory +commands must use that same session. Its PID, command files, and log are stored +under `runtime-work` in the selected build directory. The session has no idle +timeout; use `uvhs_runtime_stop` after testing to release it cleanly. +After the session stops, the released FPGA reports link down; loading the same +database and calling `initialize` without `download` fails. Start the next +runtime session with `uvhs_write_bitstream` so it reloads and downloads +`hw.dat`. + +`uvhs_write_ddr` converts the Vivado address/data-pair format to the DDR DCP +word width and calls `writemem -rtl`. It leaves the CPU halted until +`uvhs_reset_cpu` is issued. + +`uvhs_write_flash` locates the compiled generalBus endpoint with +`query -ipinfo -tclobj`, then writes through its 64-bit AXI port and the +existing 32-bit AXI flash bridge. The generalBus view starts at offset zero; +the CPU and normal JTAG address map are unchanged. A complete readback match +is required before the command succeeds. + +The runtime implementation has two control layers: + +- `runtime_server.tcl` is loaded once by the `uv_shell` process that owns the + downloaded database. It implements reset, DDR, flash, waveform capture, and + a small command-file service. Hardware operations therefore remain in the + same UVHS process for the whole board session. +- `runtime_session.sh` runs outside UVHS. `start` detaches `uv_shell` and waits + for its ready marker; `check` verifies the process and, when requested, its + ready marker; `enqueue` writes one Tcl argument list atomically and waits for + its result; and `wait` removes session state after the server handles `stop`. + The one-argument `check` also protects `uvhs_clean`. It contains no board + commands. + +The old `runtime_command.tcl` layer was merged into the server. It previously +redeclared all memory helpers on every command and depended on reset procedures +from the server's global Tcl scope. + +## UVHS ILA Waveform Capture + +The probe scripts describe compile-time instrumentation, not a runtime dump. +The frontend sources `compilation/probe_ila.tcl` by default. It samples only +the XDMA host trigger on `core_def.sys_clk_i`. `compilation/probe_kmh.tcl` is +the larger XiangShan profile used by the 2026-08-04 and 2026-08-07 debug +builds. Its generated hierarchy must be checked before it is reused with a +different XiangShan RTL revision. The braces preserve hierarchy indexes such +as `[0]`. Set `UVHS_PROBE_TCL` to select a profile or an external file; an +override must retain the XDMA host trigger if host-controlled capture is +required. Set it to an empty value for a build with no UHD instrumentation. +The scripts call `probe_net` for sampled signals and `trigger_net` for signals +that may participate in a trigger condition. + +```tcl +set uvhs_ila_clock_path [string trim { + fpga_top_debug.core_def.sys_clk_i +}] +set uvhs_ila_probe_paths { + fpga_top_debug.core_def.cpu_rstn_io + fpga_top_debug.core_def.io_host_ila_trigger +} +set uvhs_ila_trigger_paths { + fpga_top_debug.core_def.io_host_ila_trigger +} +``` + +Signal hierarchy must match the selected generated RTL. After adding probes to +the default file, build a new database and bitstream normally: + +```sh +make uvhs CPU= CORE_DIR=/path/to/release/build SUFFIX=probe +``` + +Select the repository KMH profile, an external profile, or no ILA as follows: + +```sh +make uvhs CPU= CORE_DIR=/path/to/release/build SUFFIX=probe \ + UVHS_PROBE_TCL=/path/to/env-scripts/fpga_diff/uvhs/compilation/probe_kmh.tcl +make uvhs CPU= CORE_DIR=/path/to/release/build SUFFIX=probe \ + UVHS_PROBE_TCL=/path/to/probe.tcl +make uvhs CPU= CORE_DIR=/path/to/release/build SUFFIX=noila \ + UVHS_PROBE_TCL= +``` + +The frontend records the probe and trigger declarations. The backend already +runs `trigger_probe -check` after runtime-data initialization and +`trigger_probe -group` after clock transformation, which inserts and groups the +debug hardware before partitioning. + +At runtime, `runtime/trigger.ini` matches the `test0` group in +`probe_kmh.tcl`. Use another condition file for another probe profile, based +on the group and signal names reported by `query -trigger`: + +```ini +[test0] +LOGIC = OR +fpga_top_debug.core_def.io_host_ila_trigger = R + +[UHD_FINAL_CONDITIONS_LOGIC] +LOGIC = OR +test0 +``` + +Waveform capture is split around the host run. `uvhs_ila_arm` validates and +installs the trigger condition, starts capture, and returns immediately. It +does not reset or release the CPU. `uvhs_ila` waits for an armed trigger, +uploads the UHD data, reconstructs the waveform database, and calls +`uvhs_vcd`. The standalone `uvhs_vcd` target repeats only the USDB-to-VCD +conversion. The commands create both files below the selected build directory: + +```text +runtime-work/UHD/uvhs_ila/UvData.usdb +runtime-work/UHD/uvhs_ila/UvData.vcd +``` + +The corresponding UVHS runtime sequence is: + +```tcl +trigger -ini_check /path/to/trigger.ini +trigger -set -condition /path/to/trigger.ini -position 0 +capture -enable +trigger -enable +trigger -status -wait 1 -timeout 60 +upload_uhd -depth 1000000 -position 0 -out uvhs_ila +``` + +The FPGA host clears `HOST_IO_ILA_TRIGGER`, invokes `FPGA_ILA_DUMP_CMD`, and +then releases the CPU. It raises that signal at Good Trap or DiffTest failure. +Use `uvhs_ila_arm` as the hook so capture starts before the host releases the +CPU and the requested history precedes the host trigger: + +```sh +export FPGA_ILA_DUMP_CMD='ssh \ + "make -C /path/to/env-scripts/fpga_diff uvhs_ila_arm \ + CPU= SUFFIX= \ + TRIGGER=/path/to/env-scripts/fpga_diff/uvhs/runtime/trigger.ini \ + UVHS_ILA_POSITION=0"' + +/path/to/fpga-host + +# Run on the runtime host after fpga-host exits. +make uvhs_ila CPU= SUFFIX= +``` + +The arm command must use the same runtime work directory as +`uvhs_write_bitstream`. If the FPGA host and UVHS runtime are on one machine, +omit `ssh `. The trigger signal must be listed in the compile-time +`trigger_net` group; adding it to RTL with `mark_debug` alone is not sufficient. + +Clear the trigger configuration after a timed-out or unwanted capture with: + +```sh +make uvhs_ila_clear CPU= SUFFIX= +``` + +This runs the prototyping command `trigger -clear`; it removes the configured +conditions so the trigger is no longer armed. Omitting probes at compile time +avoids their resource and timing cost entirely; leaving compiled probes idle +avoids capture and upload traffic but does not recover those implementation +resources. In HSP, capture runs in hardware without stopping the DUT clock. +The upload, waveform generation, and USDB-to-VCD conversion increase +debug-command latency rather than DUT cycle time. A large probe set can still +lower the achievable clock frequency indirectly by adding routing and timing +pressure during compilation. +The runtime command service is serial, so `uvhs_ila_clear` is handled after an +in-flight `uvhs_ila` wait reaches its trigger or timeout; it is not an +asynchronous interrupt for the current wait. + +The USDB-to-VCD step is equivalent to: + +```sh +USDB=/path/to/UvData.usdb +$UV_ROOT/uvd/uvs/bin/usdb2vcd \ + -i "$USDB" -o "${USDB%.usdb}.vcd" +``` + +The upload window is controlled when starting the capture: + +```sh +make uvhs_ila_arm CPU= SUFFIX= TRIGGER=/path/to/trigger.ini \ + UVHS_ILA_POSITION=0 +make uvhs_ila CPU= SUFFIX= UVHS_ILA_DEPTH=1000000 +``` + +`UVHS_ILA_DEPTH` is the total uploaded sample count. `UVHS_ILA_POSITION` is the +percentage after the trigger, from 0 through 100. Position 0, the default, +keeps the window before the trigger; 50 centers it; 100 keeps the window after +the trigger. Position 0 requests no intentional post-trigger allocation, but +the trigger-recognition and capture-stop pipeline can still leave a small tail +after the sampled trigger edge. `UVHS_ILA_CLOCK` can select the depth-counting +clock by a runtime-database global clock name or a frequency; when empty, the +tool uses its 200 MHz TS clock. If the compile-time sampling path is a gated +clock, pass +its backend clock path through `UVHS_ILA_GATED_CLOCK`; its frequency defaults +to 25 MHz and can be changed with `UVHS_ILA_GATED_CLOCK_FREQUENCY`. Prefer the +ungated parent clock in new probe files so capture completion does not depend +on DUT clock-gate state. `UVHS_ILA_TIMEOUT` defaults to 60 seconds. This is the +UVHS UHD path; the normal Vivado flow continues to use `make dump_ila` and a +`.ltx` file. + +UHD capture inserts its own external DDR wrapper on every FPGA containing a +probe group. The four PDDR4DME cards on the FPGA FMC3 connectors are reserved +for UHD. The DUT DDR controller is constrained to B0/F0, which owns the separate +`pddr4dme_user_inst`. The default topology also keeps B0/F1 for the USB-UART +daughter card and B0/F2 for CPU/XDMA. This avoids sharing an UHD card with the +DUT DDR controller. + +## Compatibility Boundary + +The retained compatibility code is limited to observed tool behavior: + +- `shell_compat.sh` selects Bash in generated synthesis and PnR launchers and + translates the observed Vivado-to-UVHS signoff differences for the DDR UI + clock alias and multicycle reset syntax. +- `uv_shell_exec_compat.sh` prepares the required libffi/libpcre compatibility + links and restores runtime libraries after the vendor launcher sanitizes + `LD_LIBRARY_PATH`. +- The generalBus export uses a private generator copy and makes its DCP copy + synchronous so the project is not removed before the copy finishes. +- `vivado_pre_opt.tcl` preserves the XDMA GT reference clock and marks the + validated XDMA CDC registers. + +The flow does not patch user timing constraints, hierarchy names, VIO/ILA +logic, or DDR pins. The generated signoff UDC is normalized only immediately +before the UVHS timing worker reads it. + +## Files + +| File | Role | +| --- | --- | +| `uvhs.mk` | Build and runtime target wiring. | +| `../tools/update_core_flist.sh` | Shared Vivado/UVHS RTL file-list entry point. | +| `../tools/rtl_filelist_lib.sh` | Nested file-list parsing and path resolution. | +| `compilation/flow_common.tcl` | Shared UVHS path, environment, and source helpers. | +| `compilation/frontend_run.tcl` | RTL/IP import, elaboration, and uvsyn frontend. | +| `compilation/backend_run.tcl` | Fill-rate setup, partition, routing, PnR, and database commit. | +| `compilation/assemble.tcl` | Assembles the FPGA set from the vendor board description. | +| `compilation/partition.tcl` | Places memory/configuration on B0/F0 and the core/DiffTest/XDMA path on B0/F2. | +| `compilation/assign_pin.tcl` | Physical UART daughter-card, clock, PCIe, JTAG, SD, and control pins. | +| `compilation/timing.tcl` | External clock and asynchronous-group constraints. | +| `compilation/vivado_pre_opt.tcl` | XDMA refclock and CDC constraints. | +| `compilation/prepare_ip.sh` | Coordinates Vivado, generalBus, and external DDR IP preparation. | +| `compilation/export_vivado_ip.tcl` | Runs repository-owned XCI/BD exports inside Vivado. | +| `compilation/probe_ila.tcl` | Minimal host-trigger UHD probe profile. | +| `compilation/probe_kmh.tcl` | KMH debug UHD probe profile. | +| `compilation/shell_compat.sh` | Generated launcher and signoff-constraint compatibility. | +| `runtime/uv_shell_exec_compat.sh` | Runtime library wrapper for UVHS shells and generated Python workers. | +| `runtime/runtime_server.tcl` | Download, reset, DDR, flash, capture, and command service. | +| `runtime/runtime_session.sh` | Process lifecycle and atomic command/result transport. | +| `runtime/trigger.ini` | KMH rising-edge host trigger condition. | diff --git a/fpga_diff/uvhs/compilation/assemble.tcl b/fpga_diff/uvhs/compilation/assemble.tcl new file mode 100644 index 00000000..28ad8c87 --- /dev/null +++ b/fpga_diff/uvhs/compilation/assemble.tcl @@ -0,0 +1,119 @@ +################################################################################ +# Assemble the active FPGA set from the vendor four-FPGA board template. +################################################################################ + +set uvhs_base_assemble ./script/1B_4F_HGC_assemble.tcl +set uvhs_target_fpga b0.f2 +set uvhs_known_fpgas {b0.f0 b0.f1 b0.f2 b0.f3} +set uvhs_keep_fpgas {} +foreach uvhs_fpga [split [uvhs::env_or_default UVHS_KEEP_FPGAS $uvhs_target_fpga]] { + set uvhs_fpga [string tolower [string trim $uvhs_fpga]] + if {$uvhs_fpga ne "" && [lsearch -exact $uvhs_keep_fpgas $uvhs_fpga] < 0} { + lappend uvhs_keep_fpgas $uvhs_fpga + } +} +if {[lsearch -exact $uvhs_keep_fpgas $uvhs_target_fpga] < 0} { + lappend uvhs_keep_fpgas $uvhs_target_fpga +} +foreach uvhs_fpga $uvhs_keep_fpgas { + if {[lsearch -exact $uvhs_known_fpgas $uvhs_fpga] < 0} { + error "UVHS_KEEP_FPGAS contains unknown FPGA '$uvhs_fpga'" + } +} + +if {![file exists $uvhs_base_assemble]} { + error "missing base assembly file: $uvhs_base_assemble" +} + +set uvhs_fh [open $uvhs_base_assemble r] +set uvhs_base_data [read $uvhs_fh] +close $uvhs_fh + +# Record daughter cards attached only to FPGAs that will be unplugged. Their +# create commands must be removed together with their connector commands. +set uvhs_remove_dc_instances {} +foreach uvhs_line [split $uvhs_base_data "\n"] { + set uvhs_trimmed_line [string trim $uvhs_line] + if {[regexp {^config_hw[ \t]+-connect_daughter_card[ \t]+\{([^ \t]+)[ \t]+([^ \t]+)\.FMC\}} $uvhs_trimmed_line -> uvhs_connector uvhs_instance]} { + set uvhs_lower_connector [string tolower $uvhs_connector] + foreach uvhs_fpga $uvhs_known_fpgas { + if {[string first $uvhs_fpga $uvhs_lower_connector] == 0 && + [lsearch -exact $uvhs_keep_fpgas $uvhs_fpga] < 0} { + lappend uvhs_remove_dc_instances $uvhs_instance + break + } + } + } +} + +set uvhs_filtered_lines [list] +foreach uvhs_line [split $uvhs_base_data "\n"] { + set uvhs_trimmed_line [string trim $uvhs_line] + if {[regexp {^config_hw[ \t]+-create_(daughter_card|peripheral)[ \t]+[^ \t]+[ \t]+-instance[ \t]+([^ \t]+)} $uvhs_trimmed_line -> uvhs_create_type uvhs_instance] && + [lsearch -exact $uvhs_remove_dc_instances $uvhs_instance] >= 0} { + puts "INFO: UVHS selected-FPGA overlay: remove unused daughter-card instance: $uvhs_trimmed_line" + continue + } + if {[regexp {^config_hw[ \t]+-unplug_fpga[ \t]+} $uvhs_trimmed_line]} { + puts "INFO: UVHS selected-FPGA overlay: replace base unplug: $uvhs_trimmed_line" + continue + } + if {[regexp {^config_hw[ \t]+-connect_daughter_card[ \t]+\{([^ \t]+)[ \t]+([^ \t]+)\.FMC\}} $uvhs_trimmed_line -> uvhs_connector uvhs_instance]} { + set uvhs_lower_connector [string tolower $uvhs_connector] + set uvhs_remove_link 0 + foreach uvhs_fpga $uvhs_known_fpgas { + if {[string first $uvhs_fpga $uvhs_lower_connector] == 0 && + [lsearch -exact $uvhs_keep_fpgas $uvhs_fpga] < 0} { + set uvhs_remove_link 1 + break + } + } + if {$uvhs_remove_link} { + puts "INFO: UVHS selected-FPGA overlay: remove unused daughter-card link: $uvhs_trimmed_line" + continue + } + } + if {[string match "config_hw -connect_fpga *" $uvhs_trimmed_line]} { + set uvhs_lower_line [string tolower $uvhs_trimmed_line] + set uvhs_touches_kept 0 + set uvhs_touches_unused 0 + foreach uvhs_fpga $uvhs_known_fpgas { + if {[string first $uvhs_fpga $uvhs_lower_line] >= 0} { + if {[lsearch -exact $uvhs_keep_fpgas $uvhs_fpga] >= 0} { + set uvhs_touches_kept 1 + } else { + set uvhs_touches_unused 1 + } + } + } + if {$uvhs_touches_unused || !$uvhs_touches_kept} { + puts "INFO: UVHS selected-FPGA overlay: remove unused FPGA link: $uvhs_trimmed_line" + continue + } + } + lappend uvhs_filtered_lines $uvhs_line +} +set uvhs_base_data [join $uvhs_filtered_lines "\n"] + +set uvhs_unplug_overlay "" +foreach uvhs_fpga $uvhs_known_fpgas { + if {[lsearch -exact $uvhs_keep_fpgas $uvhs_fpga] >= 0} { + append uvhs_unplug_overlay "#config_hw -unplug_fpga $uvhs_fpga\n" + } else { + append uvhs_unplug_overlay "puts \"INFO: UVHS selected-FPGA overlay: unplug $uvhs_fpga, keep $uvhs_keep_fpgas\"\n" + append uvhs_unplug_overlay "config_hw -unplug_fpga $uvhs_fpga\n" + } +} +set uvhs_create_board_replacements [regsub -line {^(config_hw[ \t]+-create_board_instance[ \t]+1[ \t]*)$} \ + $uvhs_base_data "\\1\n$uvhs_unplug_overlay" uvhs_base_data] +if {$uvhs_create_board_replacements != 1} { + error "unexpected UVHS assembly template: create_board_instance marker not found" +} + +set uvhs_overlay_file [file join [pwd] script .uvhs_assemble.tcl] +set uvhs_fh [open $uvhs_overlay_file w] +puts -nonewline $uvhs_fh $uvhs_base_data +close $uvhs_fh + +puts "INFO: source UVHS assembly overlay $uvhs_overlay_file" +source $uvhs_overlay_file diff --git a/fpga_diff/uvhs/compilation/assign_pin.tcl b/fpga_diff/uvhs/compilation/assign_pin.tcl new file mode 100644 index 00000000..e7c98ec4 --- /dev/null +++ b/fpga_diff/uvhs/compilation/assign_pin.tcl @@ -0,0 +1,102 @@ +################################################################################ +# Pin assignment for fpga_diff on the U2.2 VU19P platform. +# +# CPU, PCIe, and low-speed debug I/O use b0.f2. UART0 uses the USB-UART on the +# flash daughter card at b0.F1_FMC0. The user-DDR controller uses b0.f0. +################################################################################ + +proc pin_name {top port} { + if {$top eq "" || $top eq "none"} { + return $port + } + return "${top}.${port}" +} + +set top [uvhs::env_or_default UVHS_ASSIGN_PIN_TOP fpga_top_debug] +set xdma_link_width [string toupper [string trim [uvhs::env_or_default XDMA_LINK_WIDTH X4]]] +if {$xdma_link_width ni {X4 X8}} { + error "XDMA_LINK_WIDTH must be one of X4/X8, got '$xdma_link_width'" +} +set xdma_lane_count [expr {$xdma_link_width eq "X8" ? 8 : 4}] + +set apc16_indices { + 101 102 104 105 114 115 117 57 + 81 82 84 85 94 95 97 98 + 61 62 64 65 74 75 77 78 + 118 58 54 55 44 45 41 42 +} + +proc apc16_pin {port slot} { + global apc16_indices + global top + assign_pin -port [pin_name $top $port] -connector b0.F2_APC16 -index [lindex $apc16_indices $slot] +} + +# Low-speed debug/control pins on the unused F2 APC16 connector. +# rstn_sw* are exported as UVHS global resets and must not also be assign_pin'd. +apc16_pin led0 3 +apc16_pin led2 4 +# led3 is driven by the user-DDR calibration status on F0. +assign_pin -port [pin_name $top led3] -connector b0.F0_FMC1 -index 311 + +# UV_FMCH_FLASH drives USB_UART_RX at FMC[270] and receives USB_UART_TX at +# FMC[311], so the FPGA RX/TX directions map to 270/311 respectively. +set uvhs_uart0_connector b0.F1_FMC0 +set uvhs_uart0_tx_index 311 +set uvhs_uart0_rx_index 270 +puts "INFO: UART0 pins: TX ${uvhs_uart0_connector}\[$uvhs_uart0_tx_index\], RX ${uvhs_uart0_connector}\[$uvhs_uart0_rx_index\]" +assign_pin -port [pin_name $top uart0_sout] -connector $uvhs_uart0_connector -index $uvhs_uart0_tx_index +assign_pin -port [pin_name $top uart0_sin] -connector $uvhs_uart0_connector -index $uvhs_uart0_rx_index +apc16_pin uart1_sout 8 +apc16_pin uart1_sin 9 +apc16_pin uart2_sout 10 +apc16_pin uart2_sin 11 + +apc16_pin JTAG_TCK 12 +apc16_pin JTAG_TMS 13 +apc16_pin JTAG_TDI 14 +apc16_pin JTAG_TDO 15 +apc16_pin JTAG_TRSTn 16 + +apc16_pin SD_CLK 17 +apc16_pin SD_CMD 18 +apc16_pin SD_DATA0 19 +apc16_pin SD_DATA1 20 +apc16_pin SD_DATA2 21 +apc16_pin SD_DATA3 22 +apc16_pin SD_DECT 23 + +# U2 global clocks on F2 use the package pins declared by the board file. +assign_pin -port [pin_name $top clk6_p] -fpga b0.f2 -pin CA39 +assign_pin -port [pin_name $top clk6_n] -fpga b0.f2 -pin CA40 +assign_pin -port [pin_name $top clk8_p] -fpga b0.f2 -pin G36 +assign_pin -port [pin_name $top clk8_n] -fpga b0.f2 -pin F36 +assign_pin -port [pin_name $top clk5_p] -fpga b0.f2 -pin AW17 +assign_pin -port [pin_name $top clk5_n] -fpga b0.f2 -pin AY17 + +assign_pin -port [pin_name $top pcie_ep_lnk_up] -connector b0.F2_APC16 -index 58 + +# XDMA endpoint signals. X4 uses the HGC7 lane group from the Hejian official +# XDMA EP example; bind HGC6 only when X8 is explicitly selected. +puts "INFO: assign XDMA PCIe pins for $xdma_link_width" +assign_pin -port [pin_name $top pcie_ep_gt_ref_clk_p] -connector b0.F2_HGC7 -index 29 +assign_pin -port [pin_name $top pcie_ep_gt_ref_clk_n] -connector b0.F2_HGC7 -index 30 +assign_pin -port [pin_name $top pcie_ep_perstn] -connector b0.F2_APC16 -index 118 + +set xdma_rx_connectors {b0.F2_HGC7 b0.F2_HGC7 b0.F2_HGC7 b0.F2_HGC7 b0.F2_HGC6 b0.F2_HGC6 b0.F2_HGC6 b0.F2_HGC6} +set xdma_tx_connectors {b0.F2_HGC7 b0.F2_HGC7 b0.F2_HGC7 b0.F2_HGC7 b0.F2_HGC6 b0.F2_HGC6 b0.F2_HGC6 b0.F2_HGC6} +set xdma_rxp_indices {16 13 4 1 16 13 4 1} +set xdma_rxn_indices {17 14 5 2 17 14 5 2} +set xdma_txp_indices {35 32 23 20 35 32 23 20} +set xdma_txn_indices {36 33 24 21 36 33 24 21} +for {set i 0} {$i < $xdma_lane_count} {incr i} { + assign_pin -port [pin_name $top [format {pci_ep_rxp[%d]} $i]] -connector [lindex $xdma_rx_connectors $i] -index [lindex $xdma_rxp_indices $i] + assign_pin -port [pin_name $top [format {pci_ep_rxn[%d]} $i]] -connector [lindex $xdma_rx_connectors $i] -index [lindex $xdma_rxn_indices $i] + assign_pin -port [pin_name $top [format {pci_ep_txp[%d]} $i]] -connector [lindex $xdma_tx_connectors $i] -index [lindex $xdma_txp_indices $i] + assign_pin -port [pin_name $top [format {pci_ep_txn[%d]} $i]] -connector [lindex $xdma_tx_connectors $i] -index [lindex $xdma_txn_indices $i] +} + +# The vendor DDR DCP declares its PDDR4DME binding through UV_HW_IP metadata. +# UVHS owns those physical pins; assigning clk7 or DDR4_DIMM ports here would +# double-constrain the same daughter-card pads. +puts "INFO: vendor uvw_axi4_to_ddr4 IP owns the PDDR4DME DDR pin assignment" diff --git a/fpga_diff/uvhs/compilation/backend_run.tcl b/fpga_diff/uvhs/compilation/backend_run.tcl new file mode 100644 index 00000000..70a9e2a9 --- /dev/null +++ b/fpga_diff/uvhs/compilation/backend_run.tcl @@ -0,0 +1,145 @@ +################################################################################ +# UVHS backend flow for fpga_diff. +################################################################################ + +source [file join [file dirname [file normalize [info script]]] flow_common.tcl] +set_working_space hw.dat + +set_parallel_option -max_threads 4 -max_processes 8 -label fpga + +set_option time.auto_clock_config true +set_option time.group_io_logic false +set_option time.clock_part_group_mode 2 +set_option part.allow_timing_group_merge false +set_option clock.transform_clock.multi_iteration true +set_option clock.glitch.force_transform true +set_option clock.async_control.force_accept true +set_option time.enable_sign_off true +set_option time.incremental_sign_off true + +create_system_design -name VU19P_X4 -platform U2.2 +uvhs::source_required assemble.tcl + +set ::env(UVHS_ASSIGN_PIN_TOP) none +uvhs::source_required assign_pin.tcl +unset ::env(UVHS_ASSIGN_PIN_TOP) + +create_design -name test +read_netlist +link_design +uvhs::source_required partition.tcl +report_resource -depth 4 + +instrument_design +sanitize_design +check_design +init_runtime_data +trigger_probe -check +sweep_design + +set xdma_axi_clock_pin \ + [get_pins -quiet core_def/xdma_ep_i/TO_DIFFTEST_PCIE_CLK] +if {[llength $xdma_axi_clock_pin] != 1} { + error "required XDMA AXI clock pin not found" +} +set xdma_axi_clock_period [expr { + [string equal -nocase [uvhs::env_or_default XDMA_LINK_WIDTH X4] X8] + ? 4.0 : 8.0 +}] +create_clock -name XDMA_AXI_ACLK -period $xdma_axi_clock_period \ + $xdma_axi_clock_pin + +set ddr_ui_clock_pin [get_pins -quiet \ + core_def/U_UVHS_UVW_AXI4_TO_DDR4/ddr4ip_ddr4_user_clk] +if {[llength $ddr_ui_clock_pin] != 1} { + error "required DDR user-interface clock pin not found" +} +create_clock -name DDR_UI_CLK -period 5.0 $ddr_ui_clock_pin + +foreach {clock_name master_name cell_name} { + SOC_GATED_CLK CPU_CLK_IN core_def/SOC_CLK_CTRL_UVin_bufgce_1 + RTC_GATED_CLK TMCLK core_def/RTC_CLK_CTRL_UVin_bufgce_1 +} { + set master_clock [get_clocks -quiet $master_name] + set input_pin [get_pins -quiet ${cell_name}/I] + set output_pin [get_pins -quiet ${cell_name}/O] + if {![llength $input_pin] && ![llength $output_pin]} { + puts "INFO: skip optimized-away generated clock $clock_name" + continue + } + if {[llength $master_clock] != 1 || [llength $input_pin] != 1 || + [llength $output_pin] != 1} { + error "required generated clock path not found for $clock_name" + } + create_generated_clock -add -name $clock_name \ + -master_clock $master_clock -source $input_pin -divide_by 1 $output_pin +} + +infer_clock +report_clock -inferred +fpga_diff_set_async_clock_groups +transform_clock +set fill_rate_args {} +foreach {option variable} { + -lut UVHS_LUT_FILL_RATE + -lut6 UVHS_LUT6_FILL_RATE +} { + set value [uvhs::env_or_default $variable ""] + if {$value eq ""} { + continue + } + if {![string is double -strict $value] || $value <= 0 || $value > 100} { + error "$variable must be in (0, 100], got '$value'" + } + lappend fill_rate_args $option $value +} +if {[llength $fill_rate_args]} { + puts "INFO: set UVHS fill rates: $fill_rate_args" + set_fill_rate {*}$fill_rate_args +} +trigger_probe -group +sweep_design -remap +report_clock + +check_design +report_resource -depth 4 +report_system_resource +list_partition_constraints -all +partition_design -tdc -tdss true \ + -bs_max_blk_ratio 0.96 -bs_min_blk_ratio 0.005 -effort high +report_resource -depth 4 + +instrument_design +localize_design -replicate_cell -clock -self_check +sweep_design -keep_feedthrough +localize_design -data +route_design +check_timing -verbose -exclude clock_tdm +report_system_performance -show_clock_relation -verbose +report_path -normalize -exception -tdr -net -rtl \ + -max_path 100 -sort_by fmax + +insert_tdm +reopt_design -verbose +bind_system +save_runtime_data + +set_option compile.resourceUsageLimit 100 +set_option compile.strategyNum 1 +set_option compile.strategy0 uv_placer_balance_slrs +set_option compile.stage.preOpt \ + [uvhs::path vivado_pre_opt.tcl] + +compile_fpga -parallel_option fpga -genScriptOnly -explore +set shell_helper [uvhs::path shell_compat.sh] +if {![file isfile $shell_helper]} { + error "UVHS shell compatibility helper not found: $shell_helper" +} +exec bash $shell_helper patch-pnr hw.dat/Compile/PnR +compile_fpga -parallel_option fpga -runOnly -explore + +report_path -max_path 100 +report_system_performance +commit_runtime_data +puts "UVHS_BACKEND_SUCCESS" +exit diff --git a/fpga_diff/uvhs/compilation/export_vivado_ip.tcl b/fpga_diff/uvhs/compilation/export_vivado_ip.tcl new file mode 100644 index 00000000..f77039bf --- /dev/null +++ b/fpga_diff/uvhs/compilation/export_vivado_ip.tcl @@ -0,0 +1,346 @@ +################################################################################ +# Export Vivado IP/BD checkpoints for UVHS blackbox import. +################################################################################ + +set origin_dir "." +set out_dir "./uvhs_ip" +set force 0 +set jobs 8 +set core_dir "" + +proc print_help {} { + puts "Usage:" + puts " vivado -mode batch -source uvhs/compilation/export_vivado_ip.tcl -tclargs \\" + puts " --origin_dir --out_dir \[--core_dir \] \[--force\] \[--jobs N\]" + exit 0 +} + +for {set i 0} {$i < $::argc} {incr i} { + set option [lindex $::argv $i] + switch -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--out_dir" { incr i; set out_dir [lindex $::argv $i] } + "--core_dir" { incr i; set core_dir [lindex $::argv $i] } + "--force" { set force 1 } + "--jobs" { incr i; set jobs [lindex $::argv $i] } + "--help" { print_help } + default { + puts "ERROR: unknown option $option" + print_help + } + } +} + +set origin_dir [file normalize $origin_dir] +set out_dir [file normalize $out_dir] +if {$core_dir ne ""} { + set core_dir [file normalize $core_dir] +} +set tcl_dir [file join $origin_dir src tcl common] +set export_project_dir [file join $out_dir vivado_ip_export] +set export_project [file join $export_project_dir vivado_ip_export.xpr] + +set ::vivado_version [version -short] +set ::core_dir $core_dir + +if {$force && [file exists $export_project_dir]} { + file delete -force $export_project_dir +} + +file mkdir $out_dir +file mkdir [file join $out_dir rtl soc] +file mkdir [file join $out_dir rtl device pcie] +file mkdir $export_project_dir + +if {[file exists $export_project]} { + open_project $export_project +} else { + create_project vivado_ip_export $export_project_dir -part xcvu19p-fsva3824-2-e + set_property target_language Verilog [current_project] + set_property simulator_language Mixed [current_project] +} + +proc add_core_generated_headers {core_dir} { + if {$core_dir eq "" || ![file isdirectory $core_dir]} { + return + } + + set header_candidates [list \ + [file join $core_dir generated-src DifftestMacros.svh] \ + [file join $core_dir rtl DifftestMacros.svh] \ + ] + foreach hdr $header_candidates { + if {![file exists $hdr]} { + continue + } + set hdr [file normalize $hdr] + if {[llength [get_files -quiet $hdr]] == 0} { + add_files -norecurse $hdr + } + set hdr_file [get_files -quiet $hdr] + if {[llength $hdr_file] > 0} { + set_property file_type {Verilog Header} $hdr_file + } + puts "INFO: added core generated header $hdr" + return + } + puts "WARNING: DifftestMacros.svh not found under core_dir $core_dir" +} + +add_core_generated_headers $core_dir + +proc source_ip_tcl {script} { + if {![file exists $script]} { + error "missing IP script $script" + } + puts "INFO: source $script" + uplevel #0 [list source $script] +} + +proc run_synthesis {run_name jobs} { + set run [get_runs -quiet $run_name] + if {[llength $run] == 0} { + error "run $run_name not found" + } + + reset_run $run + clear_auto_incremental_imports $run_name + launch_runs $run -jobs $jobs + wait_on_run $run + + set status [get_property STATUS $run] + puts "INFO: $run_name status: $status" + if {![string match "*Complete*" $status]} { + error "$run_name did not complete: $status" + } + return $run +} + +proc run_and_copy_dcp {run_name out_file jobs force} { + if {[file exists $out_file] && !$force} { + puts "INFO: reuse existing $out_file" + return + } + + set run [run_synthesis $run_name $jobs] + + set run_dir [get_property DIRECTORY $run] + set dcps [glob -nocomplain [file join $run_dir *.dcp]] + if {[llength $dcps] == 0} { + error "no DCP generated in $run_dir" + } + + file mkdir [file dirname $out_file] + file copy -force [lindex $dcps 0] $out_file + puts "INFO: exported $out_file" +} + +proc run_and_write_opened_dcp {run_name out_file jobs force} { + if {[file exists $out_file] && !$force} { + puts "INFO: reuse existing $out_file" + return + } + + run_synthesis $run_name $jobs + + catch {close_design} + open_run $run_name + file mkdir [file dirname $out_file] + write_checkpoint -force $out_file + puts "INFO: exported stitched checkpoint $out_file" +} + +proc copy_generated_stub {kind name} { + global export_project_dir out_dir + + if {$kind eq "xci"} { + set candidates [concat \ + [glob -nocomplain [file join $export_project_dir *.srcs sources_1 ip $name ${name}_stub.v]] \ + [glob -nocomplain [file join $export_project_dir *.gen sources_1 ip $name ${name}_stub.v]]] + } else { + set candidates [glob -nocomplain [file join $export_project_dir *.gen sources_1 bd $name ${name}_bmstub.v]] + } + if {[llength $candidates] != 1} { + error "cannot find generated $kind stub for $name" + } + + set stub [file join $out_dir rtl stubs ${name}.v] + file mkdir [file dirname $stub] + file copy -force [lindex $candidates 0] $stub + puts "INFO: exported generated stub $stub" +} + +proc clear_auto_incremental_imports {run_name} { + global export_project_dir + + set run [get_runs -quiet $run_name] + if {[llength $run] > 0} { + set props [list_property $run] + foreach {prop value} { + AUTO_INCREMENTAL_CHECKPOINT 0 + INCREMENTAL_CHECKPOINT {} + STEPS.SYNTH_DESIGN.ARGS.INCREMENTAL_MODE off + } { + if {[lsearch -exact $props $prop] >= 0} { + set rc [catch {set_property $prop $value $run} err] + if {$rc == 0} { + puts "INFO: cleared auto-incremental property $prop on run $run_name" + } else { + puts "WARNING: failed to clear auto-incremental property $prop on run $run_name: $err" + } + } + } + } + + foreach imports_dir [glob -nocomplain [file join $export_project_dir *.srcs utils_1 imports $run_name]] { + file delete -force $imports_dir + puts "INFO: removed stale auto-incremental checkpoint imports for $run_name: $imports_dir" + } +} + +proc verify_checkpoint {label dcp} { + open_checkpoint $dcp + set cell_count [llength [get_cells -hier -quiet]] + if {$cell_count == 0} { + close_design + error "$label synthesized to an empty design" + } + set blackbox_cells [get_cells -hier -quiet -filter {IS_BLACKBOX == 1}] + set blackbox_names [list] + if {[llength $blackbox_cells] > 0} { + set blackbox_names [get_property NAME $blackbox_cells] + } + close_design + set unexpected_blackboxes [list] + foreach blackbox $blackbox_names { + if {$blackbox eq "dbg_hub"} { + puts "INFO: $label keeps Vivado debug hub blackbox $blackbox" + } else { + lappend unexpected_blackboxes $blackbox + } + } + if {[llength $unexpected_blackboxes] > 0} { + error "$label still has blackbox cells after checkpoint export: $unexpected_blackboxes" + } +} + +proc launch_run_list {run_list jobs} { + if {[llength $run_list] == 0} { + return + } + + foreach run $run_list { + reset_run $run + } + launch_runs $run_list -jobs $jobs + foreach run $run_list { + wait_on_run $run + } + + foreach run $run_list { + set status [get_property STATUS $run] + puts "INFO: $run status: $status" + if {![string match "*Complete*" $status] && ![string match "*cached IP results*" $status]} { + error "IP run $run did not complete: $status" + } + } +} + +proc create_and_launch_bd_ip_runs {bd jobs} { + catch {create_ip_run $bd} + set bd_name [file rootname [file tail $bd]] + set run_list [get_runs -quiet ${bd_name}_*_synth_1] + launch_run_list $run_list $jobs + return $run_list +} + +proc export_xci_ip {name script out_file jobs force} { + if {[llength [get_ips -quiet $name]] == 0} { + source_ip_tcl $script + } + + set ip [get_ips -quiet $name] + if {[llength $ip] == 0} { + error "IP $name was not created by $script" + } + + set ip_file [get_property IP_FILE $ip] + if {$ip_file ne ""} { + set ip_file_obj [get_files -quiet $ip_file] + if {[llength $ip_file_obj] > 0} { + set_property GENERATE_SYNTH_CHECKPOINT true $ip_file_obj + } + } + generate_target all $ip + catch {create_ip_run $ip} + run_and_copy_dcp ${name}_synth_1 $out_file $jobs $force + copy_generated_stub xci $name + verify_checkpoint "IP $name" $out_file +} + +proc export_bd_ip {name script out_file jobs force} { + if {[llength [get_files -quiet ${name}.bd]] == 0} { + source_ip_tcl $script + } + + set bd [get_files -quiet ${name}.bd] + if {[llength $bd] == 0} { + error "BD $name was not created by $script" + } + + open_bd_design $bd + current_bd_design $name + validate_bd_design + save_bd_design + generate_target all $bd + catch {make_wrapper -files $bd -top} + copy_generated_stub bd $name + + if {[file exists $out_file] && !$force} { + puts "INFO: reuse existing $out_file" + return + } + + # Build child IP OOC runs first, then synthesize the BD top as one + # checkpoint. This keeps the exported artifact as a single DCP while + # letting Vivado handle encrypted or packaged IP internals through their + # generated runs instead of compiling raw shared sources. + create_and_launch_bd_ip_runs $bd $jobs + set_property top $name [current_fileset] + update_compile_order -fileset sources_1 + run_and_write_opened_dcp synth_1 $out_file $jobs $force + verify_checkpoint "BD $name" $out_file +} + +set exports [list \ + [list xci blk_mem_gen_0 [file join $tcl_dir blk_mem_gen_0.tcl] [file join $out_dir rtl soc blk_mem_gen_0.dcp]] \ + [list bd AXI_bridge [file join $tcl_dir AXI_bridge.tcl] [file join $out_dir rtl soc AXI_bridge.dcp]] \ + [list bd data_bridge [file join $tcl_dir data_bridge.tcl] [file join $out_dir rtl soc data_bridge.dcp]] \ + [list bd xdma_ep [file join $tcl_dir xdma_ep.tcl] [file join $out_dir rtl device pcie xdma_ep.dcp]] \ +] + +set failed_exports [list] +foreach item $exports { + lassign $item kind name script out_file + puts "INFO: exporting $kind $name" + set rc [catch { + if {$kind eq "xci"} { + export_xci_ip $name $script $out_file $jobs $force + } else { + export_bd_ip $name $script $out_file $jobs $force + } + } err opts] + if {$rc != 0} { + catch {close_design} + lappend failed_exports $name + puts "ERROR: failed to export $name" + puts "ERROR: $err" + } +} + +if {[llength $failed_exports] > 0} { + error "Vivado IP/BD DCP export failed for: $failed_exports" +} + +close_project +puts "INFO: Vivado IP export finished." diff --git a/fpga_diff/uvhs/compilation/flow_common.tcl b/fpga_diff/uvhs/compilation/flow_common.tcl new file mode 100644 index 00000000..79ab6748 --- /dev/null +++ b/fpga_diff/uvhs/compilation/flow_common.tcl @@ -0,0 +1,24 @@ +namespace eval uvhs { + variable script_dir [file dirname [file normalize [info script]]] + + proc path {name} { + variable script_dir + return [file join $script_dir $name] + } + + proc env_or_default {name default} { + if {[info exists ::env($name)] && $::env($name) ne ""} { + return $::env($name) + } + return $default + } + + proc source_required {name} { + set file [path $name] + if {![file exists $file]} { + error "required UVHS flow file not found: $file" + } + puts "INFO: source $file" + uplevel #0 [list source $file] + } +} diff --git a/fpga_diff/uvhs/compilation/frontend_run.tcl b/fpga_diff/uvhs/compilation/frontend_run.tcl new file mode 100644 index 00000000..2a5d01ee --- /dev/null +++ b/fpga_diff/uvhs/compilation/frontend_run.tcl @@ -0,0 +1,135 @@ +################################################################################ +# UVHS frontend flow for fpga_diff. +################################################################################ + +source [file join [file dirname [file normalize [info script]]] flow_common.tcl] + +proc uvhs::import_blackbox {module dcp args} { + if {![file exists $dcp] || [file size $dcp] == 0} { + error "required blackbox DCP missing or empty for $module: $dcp" + } + + puts "INFO: set_blackbox $module $dcp" + uplevel #0 [concat [list set_blackbox -module $module -source_file $dcp] $args] +} + +proc uvhs::import_ip {module dcp stub args} { + foreach {kind file} [list DCP $dcp stub $stub] { + if {![file exists $file] || [file size $file] == 0} { + error "required $module $kind missing or empty: $file" + } + } + + puts "INFO: set_ip $module $dcp" + uplevel #0 [concat [list set_ip -module $module -source_file $dcp] $args] + puts "INFO: read_verilog $stub" + read_verilog $stub +} + +proc uvhs::append_option_once {file line} { + set data "" + if {[file exists $file]} { + set input [open $file r] + set data [read $input] + close $input + foreach existing [split $data "\n"] { + if {[string trim $existing] eq $line} { + return + } + } + } + + set output [open $file a] + if {$data ne "" && ![string match *\n $data]} { + puts $output "" + } + puts $output $line + close $output +} + +# UVHS runtime writemem discovers backdoor instances from these database files; +# the installed release does not expose an equivalent frontend Tcl command. +proc uvhs::register_runtime_memory {working_space inst_path} { + if {$inst_path eq "" || $inst_path eq "none"} { + return + } + set option_dir [file join $working_space DB Options] + file mkdir $option_dir + set option "add_rtl_inst -inst_name $inst_path" + append_option_once [file join $option_dir option.add_rtl_inst.txt] $option + append_option_once [file join $option_dir option.txt] $option + puts "INFO: registered UVHS runtime memory instance $inst_path" +} + +proc uvhs::start_frontend_shell_compat {} { + set helper [uvhs::path shell_compat.sh] + if {![file isfile $helper]} { + error "UVHS shell compatibility helper not found: $helper" + } + set module_makefile [file join [pwd] hw.dat Synthesis Uvsyn Script module.makefile] + exec bash $helper wait-module $module_makefile & + puts "INFO: started UVHS frontend shell compatibility helper" +} + +create_working_space -force hw.dat +set_option syn.computeFeCheckSum true + +set_parallel_option -max_threads 4 -max_processes 16 -label frontend +set_parallel_option -max_threads 16 -label runtime + +set_option global.log.label MEMORY +set_option syn.checkMultiDriver false +set_option syn.multipleDriverConflict WOR +set_option syn.engine uvsyn +set_option time.auto_clock_config true +set_option clock.transform_clock.multi_iteration true +set_option clock.glitch.force_transform true +set_option clock.async_control.force_accept true +set_option time.enable_sign_off true +set_option time.incremental_sign_off true +set_option signal.uhd.sampling_clock.allow_local_clock true + +set design_top fpga_top_debug +set ddr_inst_path ${design_top}.core_def.U_UVHS_UVW_AXI4_TO_DDR4 +create_system_design -name VU19P_X4 -platform U2.2 + +uvhs::source_required assemble.tcl +uvhs::source_required assign_pin.tcl +set probe_script [uvhs::env_or_default UVHS_PROBE_TCL ""] +if {$probe_script ne ""} { + set probe_script [file normalize $probe_script] + if {![file isfile $probe_script]} { + error "UVHS probe script not found: $probe_script" + } + puts "INFO: source UVHS probe script $probe_script" + source $probe_script +} +set_constraint_files [uvhs::path timing.tcl] +foreach reset_port {rstn_sw6 rstn_sw5 rstn_sw4} { + create_reset -port ${design_top}.${reset_port} -active 0 +} + +uvhs::import_blackbox blk_mem_gen_0 ./rtl/soc/blk_mem_gen_0.dcp +uvhs::import_blackbox AXI_bridge ./rtl/soc/AXI_bridge.dcp +uvhs::import_blackbox data_bridge ./rtl/soc/data_bridge.dcp +uvhs::import_blackbox xdma_ep ./rtl/device/pcie/xdma_ep.dcp +uvhs::import_blackbox uvw_general_bus \ + ./rtl/soc/uvw_general_bus/uvw_general_bus.dcp \ + -clock_enable_pairs {dut_axi_aclk dut_axi_aclk_en 1} +uvhs::import_ip uvw_axi4_to_ddr4 ./rtl/soc/uvw_axi4_to_ddr4.dcp \ + ./rtl/soc/uvw_axi4_to_ddr4_Stub.v \ + -clock_enable_pairs {ddr4ip_dut_axi_aclk ddr4ip_dut_axi_aclk_en 1} \ + -script_file {prePlace ./script/uvw_axi4_to_ddr4_pblock.tcl} + +set filelist ./rtl/filelist.f +if {![file exists $filelist]} { + error "required UVHS RTL file list not found: $filelist" +} +read_verilog -f $filelist -mfcu +elaborate_design $design_top +uvhs::start_frontend_shell_compat +synthesize_design -parallel_option frontend +save_working_space +uvhs::register_runtime_memory hw.dat $ddr_inst_path +puts "UVHS_FRONTEND_SUCCESS" +exit diff --git a/fpga_diff/uvhs/compilation/partition.tcl b/fpga_diff/uvhs/compilation/partition.tcl new file mode 100644 index 00000000..a586f117 --- /dev/null +++ b/fpga_diff/uvhs/compilation/partition.tcl @@ -0,0 +1,95 @@ +################################################################################ +# Keep the DUT DDR controller on the FPGA and connector of the user DDR card. +################################################################################ + +set uvhs_ddr_cell \ + [get_cells -quiet {core_def/U_UVHS_UVW_AXI4_TO_DDR4}] +if {[llength $uvhs_ddr_cell] != 1} { + error "expected one UVHS DUT DDR instance, got [llength $uvhs_ddr_cell]" +} + +# Keep the XiangShan memory and configuration paths with the user DDR. Keep the +# core and DiffTest host path with XDMA. UART pins remain on the physical F1 +# daughter card. +set uvhs_f0_cells $uvhs_ddr_cell +set uvhs_memory_path_names { + core_def/U_CPU_TOP/u_XSTop/soc/chi_extllc_opt + core_def/U_CPU_TOP/u_XSTop/soc/nocMisc + core_def/U_CPU_TOP/u_XSTop/soc/imsic_bus_tops + core_def/U_CPU_TOP/u_XSTop/soc/widget + core_def/U_CPU_TOP/u_XSTop/soc/fragmenter + core_def/U_CPU_TOP/u_XSTop/soc/tl2axi4 + core_def/U_CPU_TOP/u_XSTop/soc/axi4yank + core_def/U_CPU_TOP/u_XSTop/soc/axi4buf +} +set uvhs_config_path_names { + core_def/CFG_AXI_bridge_i + core_def/U_UVHS_FLASH_GBUS + core_def/U_SYS_CFG + core_def/u_rom +} +set uvhs_host_path_names { + core_def/U_CPU_TOP/u_XSTop/soc/core_with_l2 + core_def/U_CPU_TOP/u_XSTop/endpoint + core_def/U_CPU_TOP/u_XSTop/difftest_cfg + core_def/U_CPU_TOP/u_XSTop/difftest_host + core_def/U_CPU_TOP/u_XSTop/difftest_memCtrl + core_def/xdma_ep_i +} +set uvhs_xiangshan_cell [get_cells -quiet {core_def/U_CPU_TOP/u_XSTop}] +if {[llength $uvhs_xiangshan_cell] == 1} { + set uvhs_memory_path_cells [get_cells -quiet $uvhs_memory_path_names] + if {[llength $uvhs_memory_path_cells] != [llength $uvhs_memory_path_names]} { + error [format "incomplete XiangShan memory path: expected %d cells, got %d" \ + [llength $uvhs_memory_path_names] \ + [llength $uvhs_memory_path_cells]] + } + set uvhs_config_path_cells [get_cells -quiet $uvhs_config_path_names] + if {[llength $uvhs_config_path_cells] != [llength $uvhs_config_path_names]} { + error [format "incomplete XiangShan configuration path: expected %d cells, got %d" \ + [llength $uvhs_config_path_names] \ + [llength $uvhs_config_path_cells]] + } + set uvhs_host_path_cells [get_cells -quiet $uvhs_host_path_names] + if {[llength $uvhs_host_path_cells] != [llength $uvhs_host_path_names]} { + error [format "incomplete XiangShan host path: expected %d cells, got %d" \ + [llength $uvhs_host_path_names] \ + [llength $uvhs_host_path_cells]] + } + set uvhs_f0_cells [concat $uvhs_f0_cells $uvhs_memory_path_cells \ + $uvhs_config_path_cells] + create_fpga -name b0.f2 -cells $uvhs_host_path_cells + puts "INFO: constrain XiangShan host path to b0.f2: $uvhs_host_path_cells" +} elseif {[llength $uvhs_xiangshan_cell]} { + error "expected at most one XiangShan top cell, got [llength $uvhs_xiangshan_cell]" +} else { + puts "INFO: skip XiangShan partition constraints for this CPU" +} +create_fpga -name b0.f0 -cells $uvhs_f0_cells +set uvhs_ddr_connector b0.F0_FMC0 +set_property -name connector -value $uvhs_ddr_connector \ + -objects $uvhs_ddr_cell +set uvhs_bound_ddr_connector \ + [get_property -name connector -objects $uvhs_ddr_cell] +if {$uvhs_bound_ddr_connector ne $uvhs_ddr_connector} { + error "failed to constrain UVHS DUT DDR to $uvhs_ddr_connector" +} +puts "INFO: constrain UVHS DUT DDR to $uvhs_bound_ddr_connector" +if {[info exists uvhs_memory_path_cells]} { + puts "INFO: constrain XiangShan memory path to b0.f0: $uvhs_memory_path_cells" + puts "INFO: constrain XiangShan configuration path to b0.f0: $uvhs_config_path_cells" +} +if {[llength $uvhs_xiangshan_cell] == 1} { + set uvhs_clock_enable_net \ + [get_nets -quiet {core_def/difftest_clock_gate_enable}] + if {[llength $uvhs_clock_enable_net] != 1} { + error "expected one DiffTest clock-enable net, got [llength $uvhs_clock_enable_net]" + } + assign_route -signals $uvhs_clock_enable_net -path {b0.f2 b0.f0} + puts "INFO: constrain DiffTest clock enable to direct b0.f2-b0.f0 route" +} +unset -nocomplain uvhs_ddr_cell uvhs_ddr_connector \ + uvhs_bound_ddr_connector uvhs_f0_cells uvhs_memory_path_names \ + uvhs_memory_path_cells uvhs_config_path_names uvhs_config_path_cells \ + uvhs_host_path_names uvhs_host_path_cells \ + uvhs_xiangshan_cell uvhs_clock_enable_net diff --git a/fpga_diff/uvhs/compilation/prepare_ip.sh b/fpga_diff/uvhs/compilation/prepare_ip.sh new file mode 100755 index 00000000..2063de58 --- /dev/null +++ b/fpga_diff/uvhs/compilation/prepare_ip.sh @@ -0,0 +1,107 @@ +#!/usr/bin/env bash +set -euo pipefail + +[[ $# == 7 ]] || { + echo "Usage: $0 ORIGIN_DIR WORK_DIR CORE_DIR JOBS FORCE DDR_SOURCE DDR_WIDTH" >&2 + exit 64 +} +: "${UV_ROOT:?UV_ROOT is not set}" +: "${UV_XILINX_VIVADO:?UV_XILINX_VIVADO is not set}" + +origin_dir=$1 +work_dir=$2 +core_dir=$3 +jobs=$4 +force=$5 +ddr_source=$6 +ddr_width=$7 +script_dir=$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")" && pwd) + +require_file() { + [[ -s $1 ]] || { + echo "ERROR: required UVHS IP file is missing or empty: $1" >&2 + exit 1 + } +} + +generalbus_stub_is_64() { + grep -Eq 'output[[:space:]]+\[63:0\][[:space:]]*dut_axi_wdata' "$1" && + grep -Eq 'input[[:space:]]+\[63:0\][[:space:]]*dut_axi_rdata' "$1" +} + +# Export the Vivado IP owned by this repository. +vivado=$UV_XILINX_VIVADO/bin/vivado +vivado_args=( + --origin_dir "$origin_dir" --out_dir "$work_dir" + --core_dir "$core_dir" --jobs "$jobs" +) +[[ $force != 1 ]] || vivado_args+=(--force) +export VIVADO_HOME=$UV_XILINX_VIVADO XILINX_VIVADO=$UV_XILINX_VIVADO +"$vivado" -mode batch -source "$script_dir/export_vivado_ip.tcl" \ + -tclargs "${vivado_args[@]}" + +# Generate the vendor generalBus from a private copy. Its original generator +# removes the Vivado project before an asynchronous DCP copy has completed. +gbus_source=$UV_ROOT/platform/U2.2/Prototype/ips/uvw_gbus.3.1 +gbus_gen=$work_dir/ip-gen/generalbus +gbus_release=$gbus_gen/uvw_general_bus +require_file "$gbus_source/gen_generalbus_ip.py" +require_file "$gbus_source/uvw_axi3_generalbus.json" +if [[ $force == 1 || ! -s $gbus_release/uvw_general_bus.dcp || + ! -s $gbus_release/uvw_general_bus_Stub.v ]] || + ! generalbus_stub_is_64 "$gbus_release/uvw_general_bus_Stub.v"; then + rm -rf "$gbus_gen" + mkdir -p "$gbus_gen" + cp -a "$gbus_source" "$gbus_gen/ip-src" + generator=$gbus_gen/ip-src/gen_generalbus_ip.py + sed -i '/os[.]popen.*f_dcp_in.*f_dcp_out/c\ shutil.copy2(f_dcp_in, f_dcp_out)' \ + "$generator" + sed -i 's|#!/bin/tcsh|#!/usr/bin/env bash|' "$generator" + grep -Fq 'shutil.copy2(f_dcp_in, f_dcp_out)' "$generator" + grep -Fq '#!/usr/bin/env bash' "$generator" + json=$gbus_gen/uvw_axi3_generalbus.json + cp -f "$gbus_source/uvw_axi3_generalbus.json" "$json" + sed -i -E \ + "s|(\"IP_LOCATION\"[[:space:]]*:[[:space:]]*)\"[^\"]*\"|\1\"$gbus_gen/ip-src\"|; \ + s|(\"DATA_WIDTH\"[[:space:]]*:[[:space:]]*)\"[^\"]*\"|\1\"64\"|" "$json" + (cd "$gbus_gen" && PATH="$UV_XILINX_VIVADO/bin:$PATH" \ + python3 "$generator" -j "$json") +fi +require_file "$gbus_release/uvw_general_bus.dcp" +require_file "$gbus_release/uvw_general_bus_Stub.v" +generalbus_stub_is_64 "$gbus_release/uvw_general_bus_Stub.v" +rm -rf "$work_dir/rtl/soc/uvw_general_bus" +mkdir -p "$work_dir/rtl/soc" "$work_dir/rtl/stubs" +cp -a "$gbus_release" "$work_dir/rtl/soc/uvw_general_bus" +cp -f "$gbus_release/uvw_general_bus_Stub.v" "$work_dir/rtl/stubs/uvw_general_bus.v" +echo "INFO: prepared 64-bit UVHS generalBus DCP" + +# Import the externally generated DDR DCP using its canonical work-tree names. +[[ $ddr_width == 64 || $ddr_width == 256 ]] || { + echo "ERROR: unsupported UVHS DDR AXI width: $ddr_width" >&2 + exit 1 +} +ddr_files=( + rtl/soc/uvw_axi4_to_ddr4.dcp rtl/soc/uvw_axi4_to_ddr4_Stub.v + script/uvw_axi4_to_ddr4_pblock.tcl script/custom_parts_ddr4_KSM26SES8_2666.csv +) +for rel in "${ddr_files[@]}"; do + base=${rel##*/} + destination=$work_dir/$rel + source_file= + for candidate in "$ddr_source/$rel" "$ddr_source/$base"; do + [[ ! -f $candidate ]] || { source_file=$candidate; break; } + done + [[ -n $source_file ]] || source_file=$(find "$ddr_source" -type f -name "$base" -size +0c -print -quit) + [[ -z $source_file ]] || { mkdir -p "$(dirname "$destination")"; cp -f "$source_file" "$destination"; } +done +for rel in "${ddr_files[@]:0:3}"; do require_file "$work_dir/$rel"; done +ddr_stub=$work_dir/rtl/soc/uvw_axi4_to_ddr4_Stub.v +if gzip -t "$ddr_stub" 2>/dev/null; then + gzip -dc "$ddr_stub" >"$ddr_stub.decompressed" + mv -f "$ddr_stub.decompressed" "$ddr_stub" +fi +last_bit=$((ddr_width - 1)) +grep -Eq "input[[:space:]]+\[$last_bit:0\][[:space:]]*ddr4ip_dut_axi_wdata" "$ddr_stub" +grep -Eq "output[[:space:]]+\[$last_bit:0\][[:space:]]*ddr4ip_dut_axi_rdata" "$ddr_stub" +echo "INFO: verified UVHS DDR DCP AXI data width: $ddr_width" diff --git a/fpga_diff/uvhs/compilation/probe_ila.tcl b/fpga_diff/uvhs/compilation/probe_ila.tcl new file mode 100644 index 00000000..1ba4ac40 --- /dev/null +++ b/fpga_diff/uvhs/compilation/probe_ila.tcl @@ -0,0 +1,35 @@ +# The XDMA host trigger is always available. Add temporary design-specific +# paths below when a build needs more probes or trigger sources. +set uvhs_ila_group_name uvhs_ila +# Sampling clock path for this probe/trigger group. Prefer the ungated parent +# clock so post-trigger samples can complete after the DUT clock stops. +set uvhs_ila_clock_path [string trim { + fpga_top_debug.core_def.sys_clk_i +}] +# Probe signal paths, one per line. +set uvhs_ila_probe_paths { + fpga_top_debug.core_def.io_host_ila_trigger +} +# Trigger signal paths, one per line. +set uvhs_ila_trigger_paths { + fpga_top_debug.core_def.io_host_ila_trigger +} + +if {$uvhs_ila_clock_path eq ""} { + if {[llength $uvhs_ila_probe_paths] || + [llength $uvhs_ila_trigger_paths]} { + error "UVHS ILA signals require a sampling clock path" + } +} else { + if {[llength $uvhs_ila_probe_paths]} { + probe_net -clock $uvhs_ila_clock_path -add $uvhs_ila_probe_paths + } + if {[llength $uvhs_ila_trigger_paths]} { + trigger_net -add -group $uvhs_ila_group_name \ + -clock $uvhs_ila_clock_path \ + -signal $uvhs_ila_trigger_paths + } +} + +unset uvhs_ila_group_name uvhs_ila_clock_path +unset uvhs_ila_probe_paths uvhs_ila_trigger_paths diff --git a/fpga_diff/uvhs/compilation/probe_kmh.tcl b/fpga_diff/uvhs/compilation/probe_kmh.tcl new file mode 100644 index 00000000..02e6be4b --- /dev/null +++ b/fpga_diff/uvhs/compilation/probe_kmh.tcl @@ -0,0 +1,1216 @@ +# KMH probe profile used by the 2026-08-04 and 2026-08-07 debug builds. +# Signal paths must be checked when the generated XiangShan hierarchy changes. +probe_net -clock {fpga_top_debug.core_def.sys_clk_i} -add { \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_awaddr \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_awlen \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_awready \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_awsize \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_awvalid \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_awid \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_wdata \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_wlast \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_wready \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_wvalid \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_bready \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_bresp \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_bvalid \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_bid \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_araddr \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_arlen \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_arready \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_arsize \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_arvalid \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_arid \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_rdata \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_rlast \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_rready \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_rresp \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_rvalid \ +fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4.ddr4ip_dut_axi_rid \ +} +probe_net -clock {fpga_top_debug.core_def.sys_clk_i} -add { \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.io_csrio_tlb_satp_mode[3:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.io_csrio_tlb_satp_asid[15:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.io_csrio_tlb_vsatp_mode[3:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.io_csrio_tlb_vsatp_asid[15:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.io_csrio_tlb_hgatp_mode[3:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.io_csrio_tlb_hgatp_vmid[15:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.io_csrio_tlb_priv_mxr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.io_csrio_tlb_priv_sum \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.io_csrio_tlb_priv_vmxr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.io_csrio_tlb_priv_vsum \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.io_csrio_tlb_priv_virt \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.io_csrio_tlb_priv_spvp \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.io_csrio_tlb_priv_imode[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.io_csrio_tlb_priv_dmode[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.Fence.io_fenceio_sfence_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.Fence.io_fenceio_sfence_bits_rs1 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.Fence.io_fenceio_sfence_bits_rs2 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.Fence.io_fenceio_sfence_bits_addr[49:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.Fence.io_fenceio_sfence_bits_id[15:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.Fence.io_fenceio_sfence_bits_flushPipe \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.Fence.io_fenceio_sfence_bits_hv \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.Fence.io_fenceio_sfence_bits_hg \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_0_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_0_req_bits_vaddr[49:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_0_resp_bits_paddr_0[47:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_0_resp_bits_miss \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_0_resp_bits_excp_0_gpf_ld \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_0_resp_bits_excp_0_gpf_st \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_0_resp_bits_excp_0_pf_ld \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_0_resp_bits_excp_0_pf_st \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_0_resp_bits_excp_0_af_ld \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_0_resp_bits_excp_0_af_st \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_1_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_1_req_bits_vaddr[49:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_1_resp_bits_paddr_0[47:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_1_resp_bits_miss \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_1_resp_bits_excp_0_gpf_ld \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_1_resp_bits_excp_0_pf_ld \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_1_resp_bits_excp_0_af_ld \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_2_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_2_req_bits_vaddr[49:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_2_resp_bits_paddr_0[47:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_2_resp_bits_miss \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_2_resp_bits_excp_0_gpf_ld \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_2_resp_bits_excp_0_pf_ld \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.io_requestor_2_resp_bits_excp_0_af_ld \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.io_w_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.io_w_bits_wayIdx[5:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_0 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_3 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_4 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_5 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_6 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_7 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_8 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_9 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_10 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_11 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_12 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_13 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_14 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_15 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_16 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_17 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_18 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_19 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_20 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_21 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_22 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_23 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_24 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_25 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_26 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_27 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_28 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_29 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_30 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_31 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_32 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_33 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_34 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_35 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_36 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_37 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_38 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_39 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_40 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_41 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_42 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_43 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_44 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_45 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_46 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_47 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_0 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_1 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_2 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_3 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_4 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_5 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_6 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_7 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_8 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_9 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_10 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_11 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_12 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_13 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_14 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_15 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_16 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_17 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_18 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_19 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_20 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_21 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_22 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_23 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_24 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_25 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_26 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_27 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_28 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_29 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_30 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_31 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_32 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_33 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_34 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_35 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_36 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_37 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_38 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_39 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_40 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_41 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_42 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_43 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_44 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_45 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_46 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_1_47 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_0 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_1 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_2 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_3 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_4 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_5 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_6 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_7 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_8 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_9 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_10 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_11 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_12 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_13 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_14 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_15 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_16 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_17 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_18 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_19 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_20 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_21 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_22 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_23 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_24 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_25 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_26 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_27 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_28 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_29 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_30 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_31 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_32 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_33 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_34 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_35 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_36 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_37 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_38 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_39 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_40 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_41 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_42 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_43 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_44 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_45 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_46 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_ld_tlb_ld.entries.page_ldtlb_storage_fa.hitVecReg_2_47 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.io_requestor_0_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.io_requestor_0_req_bits_vaddr[49:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.io_requestor_0_resp_bits_paddr_0[47:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.io_requestor_0_resp_bits_miss \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.io_requestor_0_resp_bits_excp_0_gpf_st \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.io_requestor_0_resp_bits_excp_0_pf_st \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.io_requestor_0_resp_bits_excp_0_af_st \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.io_requestor_1_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.io_requestor_1_req_bits_vaddr[49:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.io_requestor_1_resp_bits_paddr_0[47:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.io_requestor_1_resp_bits_miss \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.io_requestor_1_resp_bits_excp_0_gpf_st \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.io_requestor_1_resp_bits_excp_0_pf_st \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.io_requestor_1_resp_bits_excp_0_af_st \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.io_w_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.io_w_bits_wayIdx[5:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_0 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_2 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_3 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_4 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_5 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_6 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_7 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_8 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_9 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_10 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_11 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_12 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_13 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_14 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_15 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_16 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_17 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_18 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_19 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_20 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_21 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_22 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_23 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_24 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_25 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_26 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_27 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_28 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_29 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_30 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_31 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_32 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_33 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_34 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_35 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_36 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_37 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_38 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_39 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_40 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_41 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_42 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_43 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_44 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_45 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_46 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_47 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_0 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_1 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_2 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_3 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_4 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_5 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_6 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_7 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_8 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_9 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_10 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_11 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_12 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_13 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_14 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_15 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_16 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_17 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_18 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_19 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_20 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_21 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_22 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_23 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_24 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_25 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_26 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_27 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_28 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_29 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_30 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_31 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_32 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_33 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_34 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_35 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_36 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_37 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_38 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_39 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_40 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_41 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_42 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_43 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_44 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_45 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_46 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dtlb_st_tlb_st.entries.page_sttlb_storage_fa.hitVecReg_1_47 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.io_requestor_0_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.io_requestor_0_req_bits_vaddr[49:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.io_requestor_0_resp_bits_paddr_0[47:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.io_requestor_0_resp_bits_miss \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.io_requestor_0_resp_bits_excp_0_gpf_instr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.io_requestor_0_resp_bits_excp_0_pf_instr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.io_requestor_0_resp_bits_excp_0_af_instr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.io_requestor_1_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.io_requestor_1_req_bits_vaddr[49:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.io_requestor_1_resp_bits_paddr_0[47:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.io_requestor_1_resp_bits_miss \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.io_requestor_1_resp_bits_excp_0_gpf_instr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.io_requestor_1_resp_bits_excp_0_pf_instr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.io_requestor_1_resp_bits_excp_0_af_instr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.io_w_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.io_w_bits_wayIdx[5:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_0 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_2 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_3 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_4 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_5 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_6 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_7 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_8 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_9 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_10 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_11 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_12 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_13 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_14 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_15 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_16 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_17 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_18 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_19 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_20 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_21 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_22 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_23 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_24 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_25 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_26 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_27 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_28 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_29 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_30 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_31 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_32 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_33 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_34 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_35 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_36 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_37 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_38 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_39 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_40 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_41 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_42 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_43 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_44 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_45 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_46 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_47 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_0 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_1 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_2 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_3 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_4 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_5 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_6 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_7 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_8 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_9 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_10 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_11 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_12 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_13 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_14 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_15 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_16 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_17 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_18 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_19 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_20 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_21 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_22 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_23 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_24 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_25 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_26 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_27 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_28 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_29 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_30 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_31 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_32 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_33 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_34 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_35 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_36 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_37 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_38 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_39 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_40 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_41 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_42 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_43 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_44 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_45 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_46 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.frontend.inner_itlb.entries.page_itlb_storage_fa.hitVecReg_1_47 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_req_0_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_req_0_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_req_0_bits_vpn[37:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_req_0_bits_s2xlate[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s2xlate[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_entry_tag[34:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_entry_n \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_entry_perm_d \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_entry_perm_a \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_entry_perm_g \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_entry_perm_u \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_entry_perm_x \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_entry_perm_w \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_entry_perm_r \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_entry_ppn[40:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_entry_level[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_entry_v \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_addr_low[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_ppn_low_0[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_ppn_low_1[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_ppn_low_2[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_ppn_low_3[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_ppn_low_4[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_ppn_low_5[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_ppn_low_6[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_ppn_low_7[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_valididx_0 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_valididx_1 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_valididx_2 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_valididx_3 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_valididx_4 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_valididx_5 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_valididx_6 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_valididx_7 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_pteidx_0 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_pteidx_1 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_pteidx_2 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_pteidx_3 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_pteidx_4 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_pteidx_5 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_pteidx_6 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_pteidx_7 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_pf \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s1_af \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s2_entry_tag[37:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s2_entry_n \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s2_entry_ppn[37:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s2_entry_perm_d \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s2_entry_perm_a \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s2_entry_perm_g \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s2_entry_perm_u \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s2_entry_perm_x \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s2_entry_perm_w \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s2_entry_perm_r \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s2_entry_level[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s2_gpf \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_0_resp_bits_s2_gaf \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.tlbCounter[5:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_req_0_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_req_0_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_req_0_bits_vpn[37:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_req_0_bits_s2xlate[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s2xlate[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_entry_tag[34:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_entry_n \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_entry_perm_d \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_entry_perm_a \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_entry_perm_g \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_entry_perm_u \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_entry_perm_x \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_entry_perm_w \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_entry_perm_r \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_entry_ppn[40:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_entry_level[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_entry_v \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_addr_low[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_ppn_low_0[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_ppn_low_1[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_ppn_low_2[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_ppn_low_3[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_ppn_low_4[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_ppn_low_5[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_ppn_low_6[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_ppn_low_7[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_valididx_0 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_valididx_1 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_valididx_2 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_valididx_3 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_valididx_4 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_valididx_5 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_valididx_6 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_valididx_7 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_pteidx_0 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_pteidx_1 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_pteidx_2 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_pteidx_3 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_pteidx_4 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_pteidx_5 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_pteidx_6 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_pteidx_7 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_pf \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s1_af \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s2_entry_tag[37:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s2_entry_n \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s2_entry_ppn[37:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s2_entry_perm_d \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s2_entry_perm_a \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s2_entry_perm_g \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s2_entry_perm_u \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s2_entry_perm_x \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s2_entry_perm_w \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s2_entry_perm_r \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s2_entry_level[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s2_gpf \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.io_tlb_1_resp_bits_s2_gaf \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.auto_out_a_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.auto_out_a_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.auto_out_a_bits_source[3:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.auto_out_a_bits_address[47:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.auto_out_d_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.auto_out_d_bits_opcode[3:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.auto_out_d_bits_size[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.auto_out_d_bits_source[3:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.auto_out_d_bits_data[255:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_req_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_req_bits_req_info_vpn[37:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_req_bits_req_info_s2xlate[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_req_bits_req_info_source[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_req_bits_isFirst \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_req_bits_isHptwReq \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_req_bits_hptwId[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_req_info_vpn[37:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_req_info_s2xlate[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_req_info_source[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_isFirst \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_hit \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_prefetch \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_bypassed \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toFsm_l3Hit \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toFsm_l2Hit \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toFsm_l1Hit \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toFsm_stage1Hit \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toFsm_ppn[37:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_isHptwReq \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_l3Hit \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_l2Hit \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_l1Hit \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_ppn[35:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_id[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_resp_entry_tag[37:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_resp_entry_vmid[13:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_resp_entry_n \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_resp_entry_pbmt[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_resp_entry_ppn[37:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_resp_entry_perm_d \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_resp_entry_perm_a \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_resp_entry_perm_g \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_resp_entry_perm_u \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_resp_entry_perm_x \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_resp_entry_perm_w \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_resp_entry_perm_r \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_resp_entry_level[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_resp_gpf \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_resp_bits_toHptw_bypassed \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_refill_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_refill_bits_levelOH_sp \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_refill_bits_levelOH_l0 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_refill_bits_levelOH_l1 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_refill_bits_levelOH_l2 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_refill_bits_levelOH_l3 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_refill_bits_req_info_dup_0_vpn[37:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_refill_bits_req_info_dup_0_s2xlate[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_refill_bits_req_info_dup_0_source[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.cache.io_refill_bits_sel_pte_dup_0[63:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.io_req_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.io_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.io_req_bits_req_info_vpn[37:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.io_req_bits_req_info_s2xlate[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.io_req_bits_req_info_source[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.idle \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.level[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.s_mem_req \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.w_mem_resp \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.s_hptw_req \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.w_hptw_resp \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.accessFault \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.find_pte \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.guestFault \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.io_mem_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.io_resp_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.io_llptw_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.io_hptw_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.ptw.io_hptw_req_bits_gvpn[43:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.hptw.io_req_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.hptw.io_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.hptw.io_req_bits_gvpn[37:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.hptw.io_req_bits_ppn[35:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.hptw.io_req_bits_l3Hit \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.hptw.io_req_bits_l2Hit \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.hptw.io_req_bits_l1Hit \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.hptw.io_req_bits_bypassed \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.hptw.idle \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.hptw.level[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.hptw.af_level[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.hptw.l3Hit \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.hptw.l2Hit \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.hptw.l1Hit \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.hptw.bypassed \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.hptw.io_mem_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.hptw.io_resp_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.llptw.io_in_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.llptw.io_in_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.llptw.io_in_bits_req_info_vpn[37:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.llptw.io_in_bits_req_info_s2xlate[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.llptw.io_in_bits_req_info_source[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.llptw.io_out_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.llptw.io_mem_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.missQueue.io_out_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.missQueue.io_out_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_ptw.ptw.missQueue.io_out_bits_req_info_vpn[37:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.state \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.enqPtrGenModule.enqPtrVec_0_flag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.enqPtrGenModule.enqPtrVec_0_value[7:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.deqPtrGenModule.deqPtrVec_0_flag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.deqPtrGenModule.deqPtrVec_0_value[7:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.io_commits_commitValid_0 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.io_commits_commitValid_1 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.io_commits_commitValid_2 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.io_commits_commitValid_3 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.io_commits_commitValid_4 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.io_commits_commitValid_5 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.io_commits_commitValid_6 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.io_commits_commitValid_7 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.io_commits_isCommit \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.hasWFI \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.io_frontend_toFtq_redirect_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.io_frontend_toFtq_redirect_bits_cfiUpdate_target[49:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.io_frontend_cfVec_0_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.io_frontend_cfVec_0_bits_instr[31:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_0.s3_in_nc \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_0.s3_in_mmio \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_0.s3_in_uop_robIdx_flag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_0.s3_in_uop_robIdx_value[7:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_0.s3_in_vaddr[49:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_0.s3_in_paddr[47:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_0.s3_exception \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_0.s3_mis_align_r \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_0.toMisalignBufferValid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_1.s3_in_nc \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_1.s3_in_mmio \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_1.s3_in_uop_robIdx_flag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_1.s3_in_uop_robIdx_value[7:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_1.s3_in_vaddr[49:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_1.s3_in_paddr[47:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_1.s3_exception \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_1.s3_mis_align_r \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_1.toMisalignBufferValid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_2.s3_in_nc \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_2.s3_in_mmio \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_2.s3_in_uop_robIdx_flag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_2.s3_in_uop_robIdx_value[7:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_2.s3_in_vaddr[49:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_2.s3_in_paddr[47:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_2.s3_exception \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_2.s3_mis_align_r \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_LoadUnit_2.toMisalignBufferValid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_stdExeUnits_0.io_out_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_stdExeUnits_0.io_out_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_stdExeUnits_0.io_out_bits_uop_fuType \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_stdExeUnits_0.io_out_bits_uop_fuOpType \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_stdExeUnits_0.io_out_bits_uop_robIdx_value \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_stdExeUnits_0.io_out_bits_uop_sqIdx_flag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_stdExeUnits_0.io_out_bits_uop_sqIdx_value \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_stdExeUnits_0.io_out_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_stdExeUnits_1.io_out_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_stdExeUnits_1.io_out_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_stdExeUnits_1.io_out_bits_uop_fuType \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_stdExeUnits_1.io_out_bits_uop_fuOpType \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_stdExeUnits_1.io_out_bits_uop_robIdx_value \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_stdExeUnits_1.io_out_bits_uop_sqIdx_flag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_stdExeUnits_1.io_out_bits_uop_sqIdx_value \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_stdExeUnits_1.io_out_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_0.s2_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_0.s2_in_uop_robIdx_flag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_0.s2_in_uop_robIdx_value \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_0.s2_in_vaddr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_0.s2_in_paddr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_0.s2_in_nc \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_0.s2_in_mmio \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_0.s2_pbmt \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_0.io_misalign_enq_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_0.s1_toMisalignBufferValid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_1.s2_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_1.s2_in_uop_robIdx_flag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_1.s2_in_uop_robIdx_value \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_1.s2_in_vaddr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_1.s2_in_paddr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_1.s2_in_nc \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_1.s2_in_mmio \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_1.s2_pbmt \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_1.io_misalign_enq_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_StoreUnit_1.s1_toMisalignBufferValid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_loadMisalignBuffer.bufferState[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_loadMisalignBuffer.req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_loadMisalignBuffer.req_uop_robIdx_flag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_loadMisalignBuffer.req_uop_robIdx_value[7:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_loadMisalignBuffer.io_splitLoadResp_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_storeMisalignBuffer.bufferState[2:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_storeMisalignBuffer.req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_storeMisalignBuffer.req_uop_robIdx_flag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_storeMisalignBuffer.req_uop_robIdx_value[7:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_storeMisalignBuffer.io_splitStoreResp_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_robIdx_flag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_robIdx_value \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_hasException \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_isEnqExcp \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_0 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_1 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_2 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_3 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_4 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_5 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_6 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_7 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_8 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_9 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_10 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_11 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_12 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_13 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_14 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_15 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_16 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_17 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_18 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_19 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_20 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_21 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_22 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_exceptionVec_23 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_isFetchMalAddr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_flushPipe \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_replayInst \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_singleStep \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_crossPageIPFFix \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.rob.exceptionGen.io_state_bits_trigger \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapEntryHSEvent.valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapEntryHSEvent.out_scause_bits_ExceptionCode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapEntryHSEvent.out_sepc_bits_epc \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapEntryHSEvent.out_stval_bits_ALL \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapEntryVSEvent.valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapEntryVSEvent.out_vsepc_bits_epc \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapEntryVSEvent.out_vscause_bits_ExceptionCode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapEntryVSEvent.out_vstval_bits_ALL \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.PRVM[1:0] \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.V \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_0_bits_uop_robIdx_value \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_0_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_0_bits_uop_exceptionVec_4 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_0_bits_uop_exceptionVec_5 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_0_bits_uop_exceptionVec_13 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_0_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_1_bits_uop_robIdx_value \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_1_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_1_bits_uop_exceptionVec_4 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_1_bits_uop_exceptionVec_5 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_1_bits_uop_exceptionVec_13 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_1_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_2_bits_uop_robIdx_value \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_2_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_2_bits_uop_exceptionVec_4 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_2_bits_uop_exceptionVec_5 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_2_bits_uop_exceptionVec_13 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackLda_2_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackSta_0_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackSta_0_bits_uop_robIdx_value \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackSta_0_bits_uop_robIdx_flag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackSta_0_bits_debug_isMMIO \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackSta_0_bits_debug_isNCIO \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackSta_0_bits_uop_exceptionVec_6 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackSta_0_bits_uop_exceptionVec_7 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackSta_0_bits_uop_exceptionVec_15 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackSta_1_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackSta_1_bits_uop_robIdx_value \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackSta_1_bits_uop_robIdx_flag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackSta_1_bits_debug_isMMIO \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackSta_1_bits_debug_isNCIO \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackSta_1_bits_uop_exceptionVec_6 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackSta_1_bits_uop_exceptionVec_7 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.io_mem_to_ooo_writebackSta_1_bits_uop_exceptionVec_15 \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_in_0_bits_vaddr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_in_0_bits_addr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_in_0_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_in_0_bits_mask \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_in_0_bits_vecValid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_in_0_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_in_0_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_in_1_bits_vaddr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_in_1_bits_addr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_in_1_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_in_1_bits_mask \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_in_1_bits_vecValid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_in_1_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_in_1_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_a_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_a_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_a_bits_source \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_a_bits_address \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_b_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_b_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_b_bits_param \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_b_bits_address \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_d_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_d_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_d_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_d_bits_size \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_d_bits_source \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_d_bits_corrupt \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.decode.decoders_0.isZimop \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.decode.decoders_1.isZimop \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.decode.decoders_2.isZimop \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.decode.decoders_3.isZimop \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.decode.decoders_4.isZimop \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_ctrlBlock.decode.decoders_5.isZimop \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.time_0.updated \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.time_0.mHPM_time_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.time_0.mHPM_time_bits \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.sstcIRGen.i_stime_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.sstcIRGen.i_stime_bits \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.sstcIRGen.i_vstime_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.sstcIRGen.i_vstime_bits \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.sstcIRGen.i_stimecmp_wen \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.sstcIRGen.i_stimecmp_rdata \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.sstcIRGen.i_vstimecmp_wen \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.sstcIRGen.i_vstimecmp_rdata \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.sstcIRGen.i_htimedeltaWen \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.sstcIRGen.i_menvcfg_wen \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.sstcIRGen.i_menvcfg_STCE \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.sstcIRGen.i_henvcfg_wen \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.sstcIRGen.i_henvcfg_STCE \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.sstcIRGen.o_STIP \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.sstcIRGen.o_VSTIP \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapHandleMod.io_in_trapInfo_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapHandleMod.io_in_trapInfo_bits_trapVec \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapHandleMod.io_in_trapInfo_bits_intrVec \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapHandleMod.io_in_trapInfo_bits_isInterrupt \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapHandleMod.io_in_trapInfo_bits_singleStep \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapHandleMod.io_in_trapInfo_bits_irToHS \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapHandleMod.io_in_trapInfo_bits_irToVS \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapHandleMod.io_in_privState_PRVM \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapHandleMod.io_out_entryPrivState_PRVM \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapHandleMod.io_out_entryPrivState_V \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapHandleMod.io_out_causeNO_Interrupt \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapHandleMod.io_out_causeNO_ExceptionCode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapHandleMod.io_out_dbltrpToMN \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapHandleMod.io_out_hasDTExcp \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.backend.inner_intExuBlock.exus_7.csr.csrMod.trapHandleMod.io_out_pcFromXtvec \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_a_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_c_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_c_bits_param \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_c_bits_size \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_c_bits_source \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_c_bits_address \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_c_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_client_out_d_bits_denied \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_uncache_in_a_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_uncache_in_a_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_uncache_in_a_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_uncache_in_a_bits_size \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_uncache_in_a_bits_source \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_uncache_in_a_bits_address \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_uncache_in_a_bits_mask \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_uncache_in_a_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_uncache_in_d_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_uncache_in_d_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_uncache_in_d_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_uncache_in_d_bits_size \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_uncache_in_d_bits_source \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_dcache.auto_uncache_in_d_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_dcache_req_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_dcache_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_dcache_req_bits_vaddr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_dcache_req_bits_addr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_dcache_req_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_dcache_req_bits_mask \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_dcache_req_bits_id \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_dcache_main_pipe_hit_resp_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_dcache_main_pipe_hit_resp_bits_id \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_dcache_replay_resp_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_sbuffer.io_dcache_replay_resp_bits_id \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_req_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_req_bits_robIdx_flag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_req_bits_robIdx_value \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_req_bits_addr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_req_bits_vaddr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_req_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_req_bits_mask \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_req_bits_id \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_req_bits_nc \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_req_bits_memBackTypeMM \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_idResp_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_idResp_bits_mid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_idResp_bits_nc \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_resp_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_resp_bits_nc \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_resp_bits_denied \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.core.memBlock.inner_lsq.storeQueue.io_uncache_resp_bits_corrupt \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_qos \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_tgtID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_txnID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_returnNID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_stashNIDValid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_returnTxnID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_size \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_addr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_ns \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_likelyshared \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_allowRetry \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_order \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_pCrdType \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_memAttr_allocate \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_memAttr_cacheable \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_memAttr_device \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_memAttr_ewa \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_snpAttr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_lpIDWithPadding \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_snoopMe \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_expCompAck \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_tagOp \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_traceTag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_mpam_perfMonGroup \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_mpam_partID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_mpam_mpamNS \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_req_bits_rsvdc \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_rsp_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_rsp_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_rsp_bits_qos \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_rsp_bits_tgtID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_rsp_bits_txnID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_rsp_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_rsp_bits_respErr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_rsp_bits_resp \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_rsp_bits_fwdState \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_rsp_bits_cBusy \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_rsp_bits_dbID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_rsp_bits_pCrdType \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_rsp_bits_tagOp \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_rsp_bits_traceTag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_qos \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_tgtID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_txnID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_homeNID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_respErr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_resp \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_dataSource \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_cBusy \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_dbID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_ccID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_dataID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_tagOp \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_tag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_tu \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_traceTag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_rsvdc \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_be \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_dataCheck \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_tx_dat_bits_poison \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_rsp_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_rsp_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_rsp_bits_qos \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_rsp_bits_tgtID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_rsp_bits_srcID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_rsp_bits_txnID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_rsp_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_rsp_bits_respErr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_rsp_bits_resp \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_rsp_bits_fwdState \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_rsp_bits_cBusy \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_rsp_bits_dbID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_rsp_bits_pCrdType \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_rsp_bits_tagOp \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_rsp_bits_traceTag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_qos \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_tgtID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_srcID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_txnID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_homeNID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_respErr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_resp \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_dataSource \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_cBusy \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_dbID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_ccID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_dataID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_tagOp \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_tag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_tu \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_traceTag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_rsvdc \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_be \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_dataCheck \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_dat_bits_poison \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_snp_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_snp_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_snp_bits_qos \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_snp_bits_srcID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_snp_bits_txnID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_snp_bits_fwdNID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_snp_bits_fwdTxnID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_snp_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_snp_bits_addr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_snp_bits_ns \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_snp_bits_doNotGoToSD \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_snp_bits_retToSrc \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_snp_bits_traceTag \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_snp_bits_mpam_perfMonGroup \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_snp_bits_mpam_partID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_in_rx_snp_bits_mpam_mpamNS \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_txsactive \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_rxsactive \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_syscoreq \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_syscoack \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_tx_linkactivereq \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_tx_linkactiveack \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_tx_req_flitpend \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_tx_req_flitv \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_tx_req_lcrdv \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_tx_rsp_flitpend \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_tx_rsp_flitv \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_tx_rsp_lcrdv \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_tx_dat_flitpend \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_tx_dat_flitv \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_tx_dat_lcrdv \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_rx_linkactivereq \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_rx_linkactiveack \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_rx_rsp_flitpend \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_rx_rsp_flitv \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_rx_rsp_lcrdv \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_rx_dat_flitpend \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_rx_dat_flitv \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_rx_dat_lcrdv \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_rx_snp_flitpend \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_rx_snp_flitv \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_out_rx_snp_lcrdv \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.inner_l2cache.linkMonitor.io_nodeID \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_out_d_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_out_d_bits_param \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_out_d_bits_size \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_out_d_bits_source \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_out_d_bits_sink \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_out_d_bits_denied \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_out_d_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_out_d_bits_corrupt \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_in_a_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_in_a_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_in_a_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_in_a_bits_param \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_in_a_bits_size \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_in_a_bits_source \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_in_a_bits_address \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_in_a_bits_user_memBackType_MM \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_in_a_bits_user_memPageType_NC \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_in_a_bits_mask \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_in_a_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_in_a_bits_corrupt \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_in_d_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_buffers_in_d_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_a_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_a_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_a_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_a_bits_param \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_a_bits_size \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_a_bits_source \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_a_bits_address \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_a_bits_user_alias \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_a_bits_user_reqSource \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_a_bits_user_needHint \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_a_bits_mask \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_a_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_a_bits_corrupt \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_d_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_d_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_d_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_d_bits_param \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_d_bits_size \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_d_bits_source \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_d_bits_sink \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_d_bits_denied \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_d_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_1_d_bits_corrupt \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_a_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_a_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_a_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_a_bits_param \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_a_bits_size \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_a_bits_source \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_a_bits_address \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_a_bits_user_alias \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_a_bits_user_vaddr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_a_bits_user_reqSource \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_a_bits_user_needHint \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_a_bits_echo_isKeyword \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_a_bits_mask \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_a_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_a_bits_corrupt \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_b_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_b_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_b_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_b_bits_param \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_b_bits_size \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_b_bits_source \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_b_bits_address \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_b_bits_mask \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_b_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_b_bits_corrupt \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_c_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_c_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_c_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_c_bits_param \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_c_bits_size \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_c_bits_source \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_c_bits_address \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_c_bits_user_alias \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_c_bits_user_vaddr \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_c_bits_user_reqSource \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_c_bits_user_needHint \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_c_bits_echo_isKeyword \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_c_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_c_bits_corrupt \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_d_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_d_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_d_bits_opcode \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_d_bits_param \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_d_bits_size \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_d_bits_source \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_d_bits_sink \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_d_bits_denied \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_d_bits_echo_isKeyword \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_d_bits_data \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_d_bits_corrupt \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_e_ready \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_e_valid \ +fpga_top_debug.core_def.U_CPU_TOP.u_XSTop.soc.core_with_l2.l2top.auto_inner_xbar_in_0_e_bits_sink \ +fpga_top_debug.core_def.io_host_ila_trigger \ +} +trigger_net -add -group test0 \ +-clock fpga_top_debug.core_def.sys_clk_i \ +-signal { \ +fpga_top_debug.core_def.io_host_ila_trigger \ +} diff --git a/fpga_diff/uvhs/compilation/shell_compat.sh b/fpga_diff/uvhs/compilation/shell_compat.sh new file mode 100755 index 00000000..f86587e8 --- /dev/null +++ b/fpga_diff/uvhs/compilation/shell_compat.sh @@ -0,0 +1,202 @@ +#!/usr/bin/env bash +set -euo pipefail + +usage() { + echo "Usage: $0 wait-module MODULE_MAKEFILE | patch-pnr PNR_DIR | patch-signoff SIGNOFF_DIR" >&2 + exit 2 +} + +patch_makefile() { + local makefile=$1 + + sed -E -i \ + -e 's/until[[:space:]]+sh[[:space:]]+-c/until bash -c/' \ + -e 's#(^|[[:space:]&;@])(/[^[:space:]]*/bin/uv_shell)([[:space:]])#\1bash \2\3#g' \ + -e 's#(^|[[:space:]&;@])(uv_shell)([[:space:]])#\1bash \2\3#g' \ + -e 's#(^|[[:space:]&;(@])(bash[[:space:]]+)+(/[^[:space:]]*/bin/uv_shell)#\1bash \3#g' \ + -e 's#(^|[[:space:]&;(@])(bash[[:space:]]+)+(uv_shell)#\1bash \3#g' \ + "$makefile" +} + +patch_signoff_worker() { + local worker=$1 + local helper=$2 + local marker='# fpga_diff UVHS signoff compatibility' + local temporary="${worker}.fpga-diff.$$" + + if grep -Fxq "$marker" "$worker"; then + return + fi + if ! awk -v marker="$marker" -v helper="$helper" ' + $0 == "if {[file exists $dumpPath/cstr.tcl]} {" { + print marker + print "exec bash {" helper "} patch-signoff $dumpPath" + inserted++ + } + { print } + END { if (inserted != 1) exit 1 } + ' "$worker" > "$temporary"; then + rm -f "$temporary" + echo "ERROR: unsupported generated signoff worker: $worker" >&2 + exit 1 + fi + chmod --reference="$worker" "$temporary" + mv "$temporary" "$worker" +} + +patch_signoff_constraints() { + local signoff_dir=$1 + local udc="$signoff_dir/cstr/FPGA_filtered.udc" + local clock_map="$signoff_dir/cstr.tcl" + local alias_count + local ddr_map_count + local ddr_master_clock + local identity_map_count + local master_clock_count + local reset_count + local multiplier_count_before + local multiplier_count_after + + [[ -f $udc && -f $clock_map ]] || { + echo "ERROR: signoff constraints not found under $signoff_dir" >&2 + exit 1 + } + + alias_count=$(grep -c '^create_generated_clock -name DDR_UI_CLK ' "$udc" || true) + ddr_map_count=$(grep -oE '\{DDR_UI_CLK [^}]+\}' "$clock_map" | wc -l || true) + identity_map_count=$(grep -cF '{DDR_UI_CLK DDR_UI_CLK}' "$clock_map" || true) + + ((alias_count <= 1 && ddr_map_count <= 1 && identity_map_count <= 1)) || { + echo "ERROR: ambiguous DDR signoff clock constraints in $signoff_dir" >&2 + exit 1 + } + if ((alias_count == 1)); then + ddr_master_clock=$(sed -nE ' + /^create_generated_clock -name DDR_UI_CLK .*\/ddr4ip_ddr4_user_clk]$/ { + s/.* -master_clock \[get_clocks ([^]]+)\] \[get_pins .*/\1/p + } + ' "$udc") + [[ $ddr_master_clock =~ ^[[:alnum:]_.:/-]+$ ]] || { + echo "ERROR: unsupported DDR signoff clock alias in $udc" >&2 + exit 1 + } + master_clock_count=$(grep -cF \ + "create_generated_clock -name $ddr_master_clock " "$udc" || true) + ((identity_map_count == 1 && ddr_map_count == 1 && + master_clock_count == 1)) || { + echo "ERROR: DDR signoff clock mapping has no unique MIG MMCM clock" >&2 + exit 1 + } + sed -i "s/{DDR_UI_CLK DDR_UI_CLK}/{DDR_UI_CLK $ddr_master_clock}/" \ + "$clock_map" + sed -i '/^create_generated_clock -name DDR_UI_CLK .*\/ddr4ip_ddr4_user_clk]$/d' \ + "$udc" + grep -Fq "{DDR_UI_CLK $ddr_master_clock}" "$clock_map" || { + echo "ERROR: failed to map DDR signoff clock to $ddr_master_clock" >&2 + exit 1 + } + fi + + reset_count=$(awk ' + /^set_multicycle_path / && / -reset_path / { count++ } + END { print count + 0 } + ' "$udc") + multiplier_count_before=$(grep -c ' -path_multiplier ' "$udc" || true) + if ((reset_count > 0)); then + sed -E -i ' + /^set_multicycle_path .* -reset_path .* [0-9]+$/ { + s/ -reset_path// + s/ ([0-9]+)$/ -path_multiplier \1/ + } + ' "$udc" + fi + multiplier_count_after=$(grep -c ' -path_multiplier ' "$udc" || true) + + ! grep -q '^create_generated_clock -name DDR_UI_CLK ' "$udc" || { + echo "ERROR: failed to remove DDR signoff clock alias" >&2 + exit 1 + } + ! grep -q '^set_multicycle_path .* -reset_path ' "$udc" || { + echo "ERROR: failed to translate Vivado reset-path constraints" >&2 + exit 1 + } + ((multiplier_count_after == multiplier_count_before + reset_count)) || { + echo "ERROR: incomplete multicycle-path translation in $udc" >&2 + exit 1 + } + echo "INFO: normalized UVHS signoff constraints: DDR aliases=$alias_count, reset paths=$reset_count" +} + +wait_for_module_makefile() { + local module_makefile=$1 + + for ((attempt = 0; attempt < 12000; attempt++)); do + if [[ -f $module_makefile ]]; then + patch_makefile "$module_makefile" + grep -Eq 'bash[[:space:]]+([^[:space:]]*/)?uv_shell[[:space:]]' \ + "$module_makefile" || { + echo "ERROR: failed to select Bash for $module_makefile" >&2 + exit 1 + } + echo "INFO: selected Bash for UVHS frontend workers: $module_makefile" + return + fi + sleep 0.05 + done + echo "ERROR: timed out waiting for $module_makefile" >&2 + exit 1 +} + +patch_pnr_scripts() { + local pnr_dir=$1 + local helper + local wrapper_count=0 + local makefile_count=0 + local worker_count=0 + + helper=$(realpath "$0") + + [[ -d $pnr_dir ]] || { + echo "ERROR: PnR script directory not found: $pnr_dir" >&2 + exit 1 + } + while IFS= read -r -d '' wrapper; do + sed -i '1s|^#!/bin/sh$|#!/bin/bash|' "$wrapper" + head -n 1 "$wrapper" | grep -Fxq '#!/bin/bash' || { + echo "ERROR: unsupported generated wrapper shell: $wrapper" >&2 + exit 1 + } + chmod 755 "$wrapper" + ((wrapper_count += 1)) + done < <(find "$pnr_dir" -type f -name uv_vivado_wrapper.sh -print0) + while IFS= read -r -d '' makefile; do + patch_makefile "$makefile" + ((makefile_count += 1)) + done < <(find "$pnr_dir" -type f -name Makefile -print0) + while IFS= read -r -d '' worker; do + patch_signoff_worker "$worker" "$helper" + ((worker_count += 1)) + done < <(find "$pnr_dir" -type f -name signoff_worker.tcl -print0) + + ((wrapper_count > 0)) || { + echo "ERROR: no generated Vivado wrapper found under $pnr_dir" >&2 + exit 1 + } + ((makefile_count > 0)) || { + echo "ERROR: no generated PnR Makefile found under $pnr_dir" >&2 + exit 1 + } + ((worker_count > 0)) || { + echo "ERROR: no generated signoff worker found under $pnr_dir" >&2 + exit 1 + } + echo "INFO: selected Bash in $wrapper_count wrappers and $makefile_count PnR Makefiles; patched $worker_count signoff workers" +} + +[[ $# -eq 2 ]] || usage +case $1 in + wait-module) wait_for_module_makefile "$2" ;; + patch-pnr) patch_pnr_scripts "$2" ;; + patch-signoff) patch_signoff_constraints "$2" ;; + *) usage ;; +esac diff --git a/fpga_diff/uvhs/compilation/timing.tcl b/fpga_diff/uvhs/compilation/timing.tcl new file mode 100644 index 00000000..649358a1 --- /dev/null +++ b/fpga_diff/uvhs/compilation/timing.tcl @@ -0,0 +1,34 @@ +################################################################################ +# Shared UVHS timing constraints for fpga_diff. +# UVHS records constraints before RTL elaboration, so protected ports need the +# elaborated top-level scope. +################################################################################ + +set fpga_diff_top fpga_top_debug +proc fpga_diff_top_port {name} { + set scoped_name "${::fpga_diff_top}.${name}" + if {[llength [get_ports -quiet $scoped_name]] == 1} { + return $scoped_name + } + return $name +} + +create_clock -name TMCLK -period 1000 [get_ports [fpga_diff_top_port clk8_p]] +create_clock -name ddr_ref_clk -period 12.5 [get_ports [fpga_diff_top_port clk7_p]] +create_clock -name CPU_CLK_IN -period 40 [get_ports [fpga_diff_top_port clk5_p]] +create_clock -name UART_CLK_IN -period 20 [get_ports [fpga_diff_top_port clk6_p]] +create_clock -name jtag_vclk -period 83.333 [get_ports [fpga_diff_top_port JTAG_TCK]] +create_clock -name pcie_ep_refclk -period 10 [get_ports [fpga_diff_top_port pcie_ep_gt_ref_clk_p]] + +proc fpga_diff_set_async_clock_groups {} { + set groups [list] + foreach clock {TMCLK ddr_ref_clk CPU_CLK_IN UART_CLK_IN jtag_vclk} { + lappend groups -group [get_clocks -include_generated_clocks $clock] + } + set pcie_clocks [concat \ + [get_clocks -include_generated_clocks pcie_ep_refclk] \ + [get_clocks -quiet XDMA_AXI_ACLK]] + lappend groups -group [lsort -unique $pcie_clocks] + set_clock_groups -asynchronous {*}$groups +} +fpga_diff_set_async_clock_groups diff --git a/fpga_diff/uvhs/compilation/vivado_pre_opt.tcl b/fpga_diff/uvhs/compilation/vivado_pre_opt.tcl new file mode 100644 index 00000000..ed393692 --- /dev/null +++ b/fpga_diff/uvhs/compilation/vivado_pre_opt.tcl @@ -0,0 +1,125 @@ +################################################################################ +# Vivado constraints that must be applied after the UVHS netlist is linked. +################################################################################ + +set fpga_diff_refclk_ports {} +foreach pattern { + pcie_ep_gt_ref_clk_p_pad_net_* + pcie_ep_gt_ref_clk_n_pad_net_* + pcie_ep_gt_ref_clk_p + pcie_ep_gt_ref_clk_n +} { + foreach port [get_ports -quiet $pattern] { + if {[lsearch -exact $fpga_diff_refclk_ports $port] < 0} { + lappend fpga_diff_refclk_ports $port + } + } +} +if {[llength $fpga_diff_refclk_ports]} { + # The imported XDMA IP owns the IBUFDS_GTE4. Prevent Vivado from inserting + # a fabric input/clock buffer in front of that primitive. + set_property IO_BUFFER_TYPE NONE $fpga_diff_refclk_ports + set_property CLOCK_BUFFER_TYPE NONE $fpga_diff_refclk_ports + puts "INFO: kept XDMA GT refclk pads unbuffered: $fpga_diff_refclk_ports" +} + +proc fpga_diff_mark_async_regs {label patterns} { + set cells {} + foreach pattern $patterns { + foreach cell [get_cells -hier -quiet \ + -filter "IS_SEQUENTIAL && NAME =~ $pattern"] { + if {[lsearch -exact $cells $cell] < 0} { + lappend cells $cell + } + } + } + if {[llength $cells]} { + set_property ASYNC_REG TRUE $cells + } + puts "INFO: XDMA CDC $label ASYNC_REG count=[llength $cells]" + return $cells +} + +set fpga_diff_xdma_cdc_cells {} +foreach {label patterns} { + axi_clock_converter { + */core_def/xdma_ep_i/axi_interconnect_0/*/auto_cc/inst/gen_clock_conv.gen_async_lite_conv*/clock_conv_lite_*/*_reg* + */core_def/xdma_ep_i/axi_interconnect_0/*/auto_cc/inst/gen_clock_conv.gen_async_lite_conv*/clock_conv_lite_*/handshake/*_reg* + */core_def/xdma_ep_i/axi_interconnect_0/*/auto_cc/*clock_conv_lite*/*_reg* + */core_def/xdma_ep_i/axi_interconnect_0/*/auto_cc/*handshake*/*_reg* + */core_def/xdma_ep_i/axi_interconnect_0/*/auto_cc/*cdc*/*_reg* + */core_def/xdma_ep_i/axi_interconnect_0/*/auto_cc/*sync*/*_reg* + } + axi_xpm_cdc { + */core_def/xdma_ep_i/axi_interconnect_0/*/auto_cc/inst/*xpm_cdc*/*_reg* + */core_def/xdma_ep_i/axi_interconnect_0/*/auto_cc/inst/*xpm_cdc*/inst/*_reg* + */core_def/xdma_ep_i/axi_interconnect_0/*/auto_cc/*xpm_cdc*/*_reg* + */core_def/xdma_ep_i/axi_interconnect_0/*/auto_cc/*xpm_cdc*/inst/*_reg* + } + xdma_reset_and_link { + */core_def/xdma_ep_i/xdma_0/inst/*/*cdc*/*_reg* + */core_def/xdma_ep_i/xdma_0/inst/*/*cdc*/inst/*_reg* + */core_def/xdma_ep_i/xdma_0/inst/*/xpm_cdc*/*_reg* + */core_def/xdma_ep_i/xdma_0/inst/*/xpm_cdc*/inst/*_reg* + */core_def/xdma_ep_i/xdma_0/inst/*/arststages_ff_reg* + */core_def/xdma_ep_i/xdma_0/inst/*/*user_rst*_reg* + */core_def/xdma_ep_i/xdma_0/inst/udma_wrapper/dma_top/user_rst*_reg* + */core_def/xdma_ep_i/xdma_0/inst/udma_wrapper/dma_top/*user_rst*_reg* + */core_def/xdma_ep_i/xdma_0/inst/pcie4c_ip_i/inst/*/*cdc*/*_reg* + */core_def/xdma_ep_i/xdma_0/inst/pcie4c_ip_i/inst/*/*cdc*/inst/*_reg* + */core_def/xdma_ep_i/xdma_0/inst/pcie4c_ip_i/inst/*/*sync*/*_reg* + */core_def/xdma_ep_i/xdma_0/inst/pcie4c_ip_i/inst/*/*sync*/inst/*_reg* + */core_def/xdma_ep_i/xdma_0/inst/pcie4c_ip_i/inst/*/*rst*sync*reg* + */core_def/xdma_ep_i/xdma_0/inst/pcie4c_ip_i/inst/*/*reset*sync*reg* + } +} { + foreach cell [fpga_diff_mark_async_regs $label $patterns] { + if {[lsearch -exact $fpga_diff_xdma_cdc_cells $cell] < 0} { + lappend fpga_diff_xdma_cdc_cells $cell + } + } +} +puts "INFO: XDMA CDC total ASYNC_REG count=[llength $fpga_diff_xdma_cdc_cells]" + +set fpga_diff_async_groups [list] +foreach fpga_diff_clock {TMCLK ddr_ref_clk CPU_CLK_IN jtag_vclk pcie_ep_refclk} { + lappend fpga_diff_async_groups -group \ + [get_clocks -include_generated_clocks $fpga_diff_clock] +} +set_clock_groups -asynchronous {*}$fpga_diff_async_groups + +# The DDR reset controller is clocked by the MIG MMCM. When partitioning puts +# its peripheral_aresetn consumer on another FPGA, UVHS inserts a TDM input +# synchronizer clocked by the GT TX clock. The MIG clock is not a DUT clock, so +# the generated DUT-to-TDM exceptions do not cover this reset-only crossing. +set fpga_diff_ddr_reset_regs [get_cells -hier -quiet -filter { + IS_SEQUENTIAL && + NAME =~ */core_def/U_UVHS_UVW_AXI4_TO_DDR4/*/proc_sys_reset_0/U0/ACTIVE_LOW_PR_OUT_DFF* +}] +if {[llength $fpga_diff_ddr_reset_regs]} { + set fpga_diff_tdm_tx_sync_candidates [get_pins -hier -quiet -filter { + REF_PIN_NAME == D && + NAME =~ */uvtdm_tx_ctrl_inst/sync_flop_0_reg*/D + }] + set fpga_diff_tdm_tx_sync_d_pins {} + if {[llength $fpga_diff_tdm_tx_sync_candidates]} { + set fpga_diff_ddr_reset_endpoints \ + [all_fanout -flat -endpoints_only -from $fpga_diff_ddr_reset_regs] + foreach fpga_diff_pin $fpga_diff_tdm_tx_sync_candidates { + if {[lsearch -exact $fpga_diff_ddr_reset_endpoints $fpga_diff_pin] >= 0} { + lappend fpga_diff_tdm_tx_sync_d_pins $fpga_diff_pin + } + } + } + if {[llength $fpga_diff_tdm_tx_sync_d_pins]} { + set_false_path -from $fpga_diff_ddr_reset_regs \ + -to $fpga_diff_tdm_tx_sync_d_pins + puts "INFO: constrained DDR reset-to-TDM CDC: \ + sources=[llength $fpga_diff_ddr_reset_regs] \ + destinations=[llength $fpga_diff_tdm_tx_sync_d_pins]" + } else { + puts "INFO: no DDR reset-to-TDM CDC endpoints on this FPGA" + } +} else { + puts "INFO: no DDR reset-to-TDM CDC sources on this FPGA" +} diff --git a/fpga_diff/uvhs/runtime/runtime_server.tcl b/fpga_diff/uvhs/runtime/runtime_server.tcl new file mode 100644 index 00000000..b76aed04 --- /dev/null +++ b/fpga_diff/uvhs/runtime/runtime_server.tcl @@ -0,0 +1,460 @@ +# Download a completed UVHS database and retain its owning runtime session. + +proc uvhs_temp_dir {} { + set path [file join $::uvhs_runtime_work_dir tmp] + file mkdir $path + return $path +} + +proc uvhs_prepare_uhd_root {} { + set path [file join $::uvhs_runtime_work_dir UHD] + set writable_path $path + if {![catch {file lstat $path attributes}] && + $attributes(type) eq "link"} { + set writable_path [file readlink $path] + if {[file pathtype $writable_path] ne "absolute"} { + set writable_path [file join [file dirname $path] $writable_path] + } + } + file mkdir $writable_path + file attributes $writable_path -permissions 00777 + return $path +} + +proc uvhs_parse_integer {name value} { + if {![string is wideinteger -strict $value]} { + error "$name is not an integer: $value" + } + return [expr {$value + 0}] +} + +proc uvhs_read_binary {path} { + set input [open $path rb] + fconfigure $input -translation binary -encoding binary + set data [read $input] + close $input + return $data +} + +proc uvhs_write_binary {path data} { + set output [open $path wb] + fconfigure $output -translation binary -encoding binary + puts -nonewline $output $data + close $output +} + +proc uvhs_write_atomic {path data} { + file mkdir [file dirname $path] + set temp_file "${path}.tmp.[pid]" + uvhs_write_binary $temp_file $data + file rename -force $temp_file $path +} + +proc uvhs_hold_soc_for_download {} { + foreach reset_name {rstn_sw6 rstn_sw5 rstn_sw4} { + reset -name $reset_name -value 0 + } + query -reset +} + +proc uvhs_release_soc_after_download {} { + foreach reset_name {rstn_sw6 rstn_sw5 rstn_sw4} { + reset -name $reset_name -value 0 + } + after 1000 + foreach reset_name {rstn_sw6 rstn_sw4} { + reset -name $reset_name -value 1 + } + after 1000 + reset -name rstn_sw5 -value 1 + after 1000 + query -reset +} + +proc uvhs_halt_soc {} { + reset -name rstn_sw5 -value 0 + query -reset +} + +proc uvhs_reset_cpu {} { + reset -name rstn_sw5 -value 0 + after 500 + reset -name rstn_sw5 -value 1 + after 500 + query -reset +} + +proc uvhs_hold_cpu_for_memory {} { + reset -name rstn_sw5 -value 0 + after 100 +} + +proc uvhs_release_cpu_after_memory {} { + reset -name rstn_sw5 -value 1 + after 500 + query -reset +} + +proc uvhs_find_gbus_endpoint {} { + set ip_info [query -ipinfo -tclobj] + set endpoints {} + foreach line [split $ip_info "\n"] { + if {[regexp -nocase {^\s*\S+\s+\S+\s+B([0-9]+)\.F([0-9]+)\s+[0-9]+\s+\S+\s+gbus\s+([0-9]+)} \ + $line -> board_index fpga_index instance]} { + lappend endpoints [list $board_index f$fpga_index $instance] + } + } + set endpoints [lsort -unique $endpoints] + if {[llength $endpoints] != 1} { + error "expected one generalBus endpoint, got [llength $endpoints]: $endpoints" + } + return [lindex $endpoints 0] +} + +proc uvhs_write_flash_gbus {input_file base capacity} { + if {![file isfile $input_file]} { + error "flash image not found: $input_file" + } + + lassign [uvhs_find_gbus_endpoint] board fpga instance + # The generated generalBus DCP has one internal AXI port and one channel. + # The port shown by query -ipinfo is its system-bus slot, not this port ID. + set port 0 + set channel 0 + set base [uvhs_parse_integer "flash base" $base] + set capacity [uvhs_parse_integer "flash capacity" $capacity] + set payload [uvhs_read_binary $input_file] + set payload_size [string length $payload] + if {$payload_size == 0} { + error "flash image is empty: $input_file" + } + if {$payload_size > $capacity} { + error "flash image is $payload_size bytes, capacity is $capacity bytes" + } + + set transfer_size [expr {($payload_size + 7) & ~7}] + if {$transfer_size > $capacity} { + error "8-byte-aligned flash transfer exceeds capacity: $transfer_size > $capacity" + } + append payload [string repeat "\x00" [expr {$transfer_size - $payload_size}]] + + set temp_dir [uvhs_temp_dir] + set write_file [file join $temp_dir [format "flash-write-%d.bin" [pid]]] + set read_file [file join $temp_dir [format "flash-read-%d.bin" [pid]]] + uvhs_write_binary $write_file $payload + file delete -force $read_file + + puts [format \ + "INFO: generalBus B%d.%s instance %d flash write 0x%llx, %d bytes" \ + $board $fpga $instance $base $transfer_size] + set status [catch { + gbus_dma_write -board $board -fpga $fpga -instance $instance -port $port \ + -addr $base -size $transfer_size -channel $channel -file $write_file + gbus_dma_read -board $board -fpga $fpga -instance $instance -port $port \ + -addr $base -size $transfer_size -channel $channel -file $read_file + set readback [uvhs_read_binary $read_file] + if {![string equal $payload $readback]} { + error "generalBus flash readback mismatch" + } + } message options] + file delete -force $write_file $read_file + if {$status != 0} { + return -options $options $message + } + puts "INFO: generalBus flash full readback passed: $input_file" +} + +proc uvhs_write_ddr_pairs {input_file rtl_path data_width} { + if {![file isfile $input_file]} { + error "DDR workload not found: $input_file" + } + if {![string is integer -strict $data_width] || $data_width ni {64 256}} { + error "unsupported DDR AXI data width: $data_width" + } + + set beat_bytes [expr {$data_width / 8}] + set beat_chars [expr {$data_width / 4}] + set input [open $input_file r] + set segment 0 + set line_number 0 + + while {[gets $input address_text] >= 0} { + incr line_number + if {[gets $input data_text] < 0} { + close $input + error "missing data line after line $line_number" + } + incr line_number + set address_text [string trim $address_text] + set data_text [string trim $data_text] + if {![regexp {^[0-9a-fA-F]+$} $address_text]} { + close $input + error "invalid DDR address on line [expr {$line_number - 1}]: $address_text" + } + if {![regexp {^[0-9a-fA-F]+$} $data_text]} { + close $input + error "invalid DDR data on line $line_number" + } + if {[expr {[string length $data_text] % $beat_chars}] != 0} { + close $input + error "DDR data on line $line_number is not aligned to $data_width bits" + } + if {[scan $address_text %llx byte_address] != 1 || + [expr {$byte_address % $beat_bytes}] != 0} { + close $input + error "DDR address is not aligned to $beat_bytes bytes: $address_text" + } + + set beat_count [expr {[string length $data_text] / $beat_chars}] + set start_word [expr {$byte_address / $beat_bytes}] + set end_word [expr {$start_word + $beat_count - 1}] + set temp_file [file join [uvhs_temp_dir] \ + [format "ddr-%d-%d.hex" [pid] $segment]] + incr segment + + set output [open $temp_file w] + for {set beat 0} {$beat < $beat_count} {incr beat} { + set first [expr {[string length $data_text] - ($beat + 1) * $beat_chars}] + puts $output [string range $data_text $first \ + [expr {$first + $beat_chars - 1}]] + } + close $output + + puts [format "INFO: DDR backdoor write %s words 0x%llx..0x%llx" \ + $beat_count $start_word $end_word] + set status [catch { + writemem -rtl $rtl_path -start $start_word -end $end_word \ + -file $temp_file -hex + } message options] + file delete -force $temp_file + if {$status != 0} { + close $input + return -options $options $message + } + } + close $input + puts "INFO: DDR backdoor write completed: $input_file" +} + +proc uvhs_ila_arm { + trigger_file position gated_clock gated_clock_frequency +} { + if {![file isfile $trigger_file]} { + error "trigger condition file not found: $trigger_file" + } + set position [uvhs_parse_integer "capture position" $position] + if {$position < 0 || $position > 100} { + error "capture position must be between 0 and 100: $position" + } + if {$gated_clock ne ""} { + set gated_clock_frequency [uvhs_parse_integer \ + "gated capture clock frequency" $gated_clock_frequency] + if {$gated_clock_frequency <= 0} { + error "gated capture clock frequency must be positive" + } + } + + unset -nocomplain ::uvhs_ila_position + trigger -clear + query -trigger + trigger -ini_check $trigger_file + if {$gated_clock ne ""} { + trigger -set -gatedclk $gated_clock \ + -frequency $gated_clock_frequency -polarity H + } + trigger -set -condition $trigger_file -position $position + capture -enable + trigger -enable + set ::uvhs_ila_position $position + puts "INFO: UVHS waveform capture armed at position $position" +} + +proc uvhs_ila_wait {output_name timeout depth clock} { + if {![info exists ::uvhs_ila_position]} { + error "UVHS waveform capture is not armed; run ila_arm first" + } + if {![regexp {^[A-Za-z0-9_.-]+$} $output_name]} { + error "capture output name contains unsupported characters: $output_name" + } + set timeout [uvhs_parse_integer "capture timeout" $timeout] + set depth [uvhs_parse_integer "capture depth" $depth] + if {$timeout <= 0 || $depth <= 0} { + error "capture timeout and depth must be positive" + } + + set trigger_status [trigger -status -wait 1 -timeout $timeout -tclobj] + puts "INFO: UVHS trigger status: $trigger_status" + if {![regexp -nocase {Waveform Data Ready\s+true} $trigger_status]} { + error "UVHS waveform data is not ready" + } + + set output_dir [file join [uvhs_prepare_uhd_root] $output_name] + file delete -force $output_dir + set upload_options [list -depth $depth \ + -position $::uvhs_ila_position] + if {$clock ne ""} { + lappend upload_options -clock $clock + } + lappend upload_options -out $output_name + upload_uhd {*}$upload_options + wavegen -bindir [file join UHD $output_name] + + set usdb [file join $output_dir UvData.usdb] + if {![file exists $usdb] || [file size $usdb] == 0} { + error "UVHS waveform database was not generated: $usdb" + } + puts "INFO: UVHS waveform database generated: $usdb" +} + +proc uvhs_ila_clear {} { + trigger -clear + unset -nocomplain ::uvhs_ila_position + puts "INFO: UVHS trigger conditions and capture are disabled" +} + +proc uvhs_execute_command {args} { + if {[llength $args] == 0} { + error "missing UVHS runtime command" + } + set command [lindex $args 0] + puts "INFO: executing UVHS runtime command: $command" + switch -- $command { + halt_soc { + if {[llength $args] != 1} { error "halt_soc expects no arguments" } + uvhs_halt_soc + } + reset_cpu { + if {[llength $args] != 1} { error "reset_cpu expects no arguments" } + uvhs_reset_cpu + } + write_ddr { + if {[llength $args] != 4} { error "write_ddr expects 3 arguments" } + uvhs_hold_cpu_for_memory + uvhs_write_ddr_pairs {*}[lrange $args 1 3] + } + write_flash { + if {[llength $args] != 4} { error "write_flash expects 3 arguments" } + uvhs_hold_cpu_for_memory + uvhs_write_flash_gbus {*}[lrange $args 1 3] + uvhs_release_cpu_after_memory + } + ila_arm { + if {[llength $args] != 5} { error "ila_arm expects 4 arguments" } + uvhs_ila_arm {*}[lrange $args 1 4] + } + ila_wait { + if {[llength $args] != 5} { error "ila_wait expects 4 arguments" } + uvhs_ila_wait {*}[lrange $args 1 4] + } + ila_clear { + if {[llength $args] != 1} { error "ila_clear expects no arguments" } + uvhs_ila_clear + } + stop { + if {[llength $args] != 1} { error "stop expects no arguments" } + set ::uvhs_keepalive 1 + } + default { + error "unknown UVHS runtime command: $command" + } + } + puts "INFO: completed UVHS runtime command: $command" +} + +proc uvhs_signal_runtime_ready {} { + uvhs_write_atomic $::uvhs_ready_file "[pid]\n" + puts "INFO: UVHS runtime command service is ready" +} + +proc uvhs_clear_runtime_ready {} { + file delete -force $::uvhs_ready_file +} + +proc uvhs_write_command_result {result_file status message} { + if {$result_file eq ""} { + return + } + uvhs_write_atomic $result_file "$status\n$message" +} + +proc uvhs_poll_command_file {} { + set command_file $::uvhs_command_file + if {[file exists $command_file]} { + set running_file "${command_file}.running" + set uvhs_result_file "" + set command_status [catch { + file rename -force $command_file $running_file + puts "INFO: sourcing UVHS runtime command: $running_file" + source $running_file + } command_message] + if {$command_status != 0} { + set command_message "UVHS runtime command failed: $command_message" + } + catch {file delete -force $running_file} + uvhs_write_command_result $uvhs_result_file $command_status $command_message + if {$command_status != 0} { + puts stderr "ERROR: $command_message" + } + } + after 500 uvhs_poll_command_file +} + +proc uvhs_serve_runtime_commands {} { + foreach variable { + UVHS_COMMAND_FILE UVHS_RUNTIME_READY_FILE UVHS_RUNTIME_WORK_DIR + } { + if {![info exists ::env($variable)] || $::env($variable) eq ""} { + error "$variable is not set" + } + } + set ::uvhs_command_file $::env(UVHS_COMMAND_FILE) + set ::uvhs_ready_file $::env(UVHS_RUNTIME_READY_FILE) + set ::uvhs_runtime_work_dir $::env(UVHS_RUNTIME_WORK_DIR) + set ::uvhs_keepalive 0 + uvhs_signal_runtime_ready + uvhs_poll_command_file + vwait ::uvhs_keepalive + uvhs_clear_runtime_ready +} + +proc uvhs_initialize_runtime {} { + query -user + query -fpgas -all + query -version + + if {[info exists ::env(UVHS_DB_PATH)] && $::env(UVHS_DB_PATH) ne ""} { + set db_path $::env(UVHS_DB_PATH) + } else { + set db_path [file normalize [file join [pwd] .. hw.dat]] + } + puts "INFO: loading runtime database $db_path" + load_db -db $db_path + + config -connector + query -connector -type fmc + query -voltage + + # A release database can lack sign-off defaults. In that case the replay + # clock values already stored in the database remain active. + if {[catch {query -clock -default} clock_error]} { + puts "WARN: retaining database replay clocks: $clock_error" + } else { + config -clock -default + } + # Keep clk5_p at the system sign-off frequency committed in this runtime DB. + # It varies with the partition and PnR result, so it must not be hard-coded. + config -clock -name clk6_p -frequency 50000000 + config -clock -commit + query -clock + + uvhs_hold_soc_for_download + download + query -ipinfo + initialize + after 1000 + uvhs_release_soc_after_download + query -fpgas -all +} + +uvhs_initialize_runtime +uvhs_serve_runtime_commands diff --git a/fpga_diff/uvhs/runtime/runtime_session.sh b/fpga_diff/uvhs/runtime/runtime_session.sh new file mode 100755 index 00000000..36b360d8 --- /dev/null +++ b/fpga_diff/uvhs/runtime/runtime_session.sh @@ -0,0 +1,218 @@ +#!/usr/bin/env bash +set -euo pipefail + +usage() { + cat >&2 <<'EOF' +usage: + runtime_session.sh start \ + [argument ...] + runtime_session.sh check [ready-file] + runtime_session.sh enqueue [argument ...] + runtime_session.sh wait +EOF + exit 64 +} + +read_pid() { + local pid_file=$1 + local pid + [[ -f $pid_file ]] || return 1 + IFS= read -r pid <"$pid_file" || return 1 + [[ $pid =~ ^[1-9][0-9]*$ ]] || return 1 + printf '%s\n' "$pid" +} + +process_is_alive() { + kill -0 "$1" 2>/dev/null +} + +write_pid() { + local pid_file=$1 + local pid=$2 + local temp_file="${pid_file}.tmp.$$" + printf '%s\n' "$pid" >"$temp_file" + mv -f "$temp_file" "$pid_file" +} + +validate_timeout() { + [[ $1 =~ ^[1-9][0-9]*$ ]] || { + echo "ERROR: UVHS runtime timeout must be a positive integer" >&2 + exit 64 + } +} + +show_log_tail() { + local log_file=$1 + if [[ -f $log_file ]]; then + echo "----- UVHS runtime log tail: $log_file -----" >&2 + tail -40 "$log_file" >&2 + fi +} + +tcl_quote() { + local value=$1 + value=${value//\\/\\\\} + value=${value//\"/\\\"} + value=${value//\$/\\\$} + value=${value//\[/\\[} + value=${value//\]/\\]} + printf '"%s"' "$value" +} + +action=${1:-} +[[ -n $action ]] || usage +shift + +case $action in + start) + (( $# >= 6 )) || usage + pid_file=$1 + ready_file=$2 + log_file=$3 + command_file=$4 + timeout=$5 + shift 5 + validate_timeout "$timeout" + + if pid=$(read_pid "$pid_file") && process_is_alive "$pid"; then + echo "ERROR: UVHS runtime is already active with PID $pid" >&2 + echo "Run make uvhs_runtime_stop before programming again." >&2 + exit 2 + fi + + mkdir -p "$(dirname "$pid_file")" "$(dirname "$ready_file")" \ + "$(dirname "$log_file")" "$(dirname "$command_file")" + rm -f "$pid_file" "$ready_file" "$command_file" "${command_file}.running" + + nohup "$@" "$log_file" 2>&1 & + pid=$! + write_pid "$pid_file" "$pid" + + deadline=$((SECONDS + timeout)) + while [[ ! -f $ready_file ]]; do + if ! process_is_alive "$pid"; then + set +e + wait "$pid" + status=$? + set -e + rm -f "$pid_file" "$ready_file" + show_log_tail "$log_file" + echo "ERROR: UVHS runtime exited before it became ready (status $status)" >&2 + exit 3 + fi + if (( SECONDS >= deadline )); then + kill "$pid" 2>/dev/null || true + wait "$pid" 2>/dev/null || true + rm -f "$pid_file" "$ready_file" + show_log_tail "$log_file" + echo "ERROR: timed out waiting for UVHS runtime after ${timeout}s" >&2 + exit 4 + fi + sleep 0.2 + done + + if ! runtime_pid=$(read_pid "$ready_file") || ! process_is_alive "$runtime_pid"; then + rm -f "$pid_file" "$ready_file" + show_log_tail "$log_file" + echo "ERROR: UVHS runtime published an invalid ready PID" >&2 + exit 5 + fi + write_pid "$pid_file" "$runtime_pid" + echo "INFO: UVHS runtime ready (PID $runtime_pid); log: $log_file" + ;; + check) + (( $# == 1 || $# == 2 )) || usage + pid_file=$1 + if ! pid=$(read_pid "$pid_file") || ! process_is_alive "$pid"; then + rm -f "$pid_file" + (( $# != 2 )) || rm -f "$2" + echo "ERROR: UVHS runtime is not active; run make uvhs_write_bitstream first" >&2 + exit 6 + fi + if (( $# == 2 )); then + ready_file=$2 + if ! ready_pid=$(read_pid "$ready_file") || [[ $ready_pid != "$pid" ]]; then + echo "ERROR: UVHS runtime PID $pid has no matching ready marker" >&2 + exit 7 + fi + echo "INFO: UVHS runtime is ready (PID $pid)" + else + echo "INFO: UVHS runtime process is active (PID $pid)" + fi + ;; + enqueue) + (( $# >= 3 )) || usage + command_file=$1 + timeout=$2 + shift 2 + validate_timeout "$timeout" + if [[ -e $command_file || -e $command_file.running ]]; then + echo "ERROR: a UVHS runtime command is already pending" >&2 + exit 9 + fi + + result_file="${command_file}.result.$$" + temp_file="${command_file}.tmp.$$" + mkdir -p "$(dirname "$command_file")" + trap 'rm -f "$temp_file" "$result_file"' EXIT + { + printf 'set uvhs_result_file ' + tcl_quote "$result_file" + printf '\nset argv [list' + for argument in "$@"; do + printf ' ' + tcl_quote "$argument" + done + printf ']\nuvhs_execute_command {*}$argv\n' + } >"$temp_file" + mv -n "$temp_file" "$command_file" + [[ ! -e $temp_file ]] || { + echo "ERROR: command file appeared while enqueueing: $command_file" >&2 + exit 10 + } + echo "INFO: enqueued UVHS runtime command: $command_file" + + deadline=$((SECONDS + timeout)) + while [[ ! -f $result_file ]]; do + if (( SECONDS >= deadline )); then + echo "ERROR: timed out waiting for UVHS runtime command after ${timeout}s" >&2 + exit 11 + fi + sleep 0.2 + done + status=$(sed -n '1p' "$result_file") + message=$(sed -n '2,$p' "$result_file") + rm -f "$result_file" + if [[ $status != 0 ]]; then + echo "ERROR: UVHS runtime command failed: $message" >&2 + exit 12 + fi + [[ -z $message ]] || echo "INFO: $message" + ;; + wait) + (( $# == 4 )) || usage + pid_file=$1 + ready_file=$2 + command_file=$3 + timeout=$4 + validate_timeout "$timeout" + + if ! pid=$(read_pid "$pid_file"); then + rm -f "$ready_file" "$command_file" "${command_file}.running" + exit 0 + fi + deadline=$((SECONDS + timeout)) + while process_is_alive "$pid"; do + if (( SECONDS >= deadline )); then + echo "ERROR: timed out waiting for UVHS runtime PID $pid to stop" >&2 + exit 8 + fi + sleep 0.2 + done + rm -f "$pid_file" "$ready_file" "$command_file" "${command_file}.running" + echo "INFO: UVHS runtime stopped" + ;; + *) + usage + ;; +esac diff --git a/fpga_diff/uvhs/runtime/trigger.ini b/fpga_diff/uvhs/runtime/trigger.ini new file mode 100644 index 00000000..7a3ff735 --- /dev/null +++ b/fpga_diff/uvhs/runtime/trigger.ini @@ -0,0 +1,7 @@ +[test0] +LOGIC = OR +fpga_top_debug.core_def.io_host_ila_trigger = R + +[UHD_FINAL_CONDITIONS_LOGIC] +LOGIC = OR +test0 diff --git a/fpga_diff/uvhs/runtime/uv_shell_exec_compat.sh b/fpga_diff/uvhs/runtime/uv_shell_exec_compat.sh new file mode 100755 index 00000000..ff0b23aa --- /dev/null +++ b/fpga_diff/uvhs/runtime/uv_shell_exec_compat.sh @@ -0,0 +1,61 @@ +#!/usr/bin/env bash +set -euo pipefail + +: "${UV_ROOT:?UV_ROOT is not set}" +: "${UVHS_RUNTIME_LIB_DIR:?UVHS_RUNTIME_LIB_DIR is not set}" + +find_library() { + ldconfig -p | awk -v soname="$1" '$1 == soname && !found { print $NF; found = 1 }' +} + +mkdir -p "$UVHS_RUNTIME_LIB_DIR" + +ffi=$(find_library libffi.so.6) +if [[ -z $ffi ]]; then + ffi=$(find_library libffi.so.8) +fi +[[ -n $ffi ]] || { + echo "ERROR: libffi.so.6 or libffi.so.8 is required by uv_shell_exec" >&2 + exit 1 +} +ln -sfn "$ffi" "$UVHS_RUNTIME_LIB_DIR/libffi.so.6" + +if ldd "$UV_ROOT/bin/uv_shell_exec" 2>/dev/null | grep -q 'libpcre[.]so[.]1 => not found'; then + pcre= + for candidate in \ + "$UVHS_RUNTIME_LIB_DIR/libpcre.so.1" \ + "$UV_ROOT/shlib_install/libpcre.so.1" \ + "$UV_ROOT/shlib/libpcre.so.1" \ + "$(find_library libpcre.so.3)"; do + if [[ -n $candidate && -f $candidate ]]; then + pcre=$candidate + break + fi + done + [[ -n $pcre ]] || { + echo "ERROR: uv_shell_exec needs PCRE1 (libpcre.so.1 or libpcre.so.3)" >&2 + exit 1 + } + if [[ $pcre != "$UVHS_RUNTIME_LIB_DIR/libpcre.so.1" ]]; then + ln -sfn "$pcre" "$UVHS_RUNTIME_LIB_DIR/libpcre.so.1" + fi +fi + +runtime_library_path=$UVHS_RUNTIME_LIB_DIR +if [[ -n ${UMI_LD_LIBRARY_PATH:-} ]]; then + runtime_library_path=$runtime_library_path:$UMI_LD_LIBRARY_PATH +fi +if [[ -n ${LD_LIBRARY_PATH:-} ]]; then + runtime_library_path=$runtime_library_path:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH=$runtime_library_path + +if [[ -n ${UVHS_COMPAT_BIN:-} ]]; then + export PATH=$UVHS_COMPAT_BIN:$PATH +fi + +executable="$UV_ROOT/bin/uv_shell_exec" +case ${0##*/} in + python|python3) executable="$UV_ROOT/lib/venv3.8/bin/${0##*/}" ;; +esac +exec "$executable" "$@" diff --git a/fpga_diff/uvhs/uvhs.mk b/fpga_diff/uvhs/uvhs.mk new file mode 100644 index 00000000..8ad06252 --- /dev/null +++ b/fpga_diff/uvhs/uvhs.mk @@ -0,0 +1,215 @@ +UVHS_ROOT_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))/..) +UVHS_COMPILATION_DIR := $(UVHS_ROOT_DIR)/uvhs/compilation +UVHS_RUNTIME_DIR := $(UVHS_ROOT_DIR)/uvhs/runtime + +UVHS_TEMPLATE_DIR ?= +UVHS_UVW_AXI4_TO_DDR4_SRC ?= +UVHS_PROBE_TCL ?= $(UVHS_COMPILATION_DIR)/probe_ila.tcl +UVHS_PROBE_PATH := $(if $(strip $(UVHS_PROBE_TCL)),$(abspath $(UVHS_PROBE_TCL)),) +UVHS_DDR_AXI_WIDTH := $(if $(filter nutshell,$(CPU)),64,256) +UVHS_WORK_DIR := $(ENV_SCRIPTS_HOME)/fpga_diff_uvhs_$(CPU)$(if $(strip $(SUFFIX)),-$(strip $(SUFFIX)),) +UVHS_FILELIST := $(UVHS_WORK_DIR)/rtl/filelist.f + +UVHS_EXPORT_IP_FORCE ?= 0 +UVHS_EXPORT_IP_JOBS := $(if $(strip $(VIVADO_JOBS)),$(VIVADO_JOBS),8) +UVHS_KEEP_FPGAS ?= b0.f0 b0.f1 b0.f2 +UVHS_LUT_FILL_RATE ?= $(if $(filter kmh,$(CPU)),70,) +UVHS_LUT6_FILL_RATE ?= $(if $(filter kmh,$(CPU)),35,) + +UVHS_DDR_RTL_INST := fpga_top_debug.core_def.U_UVHS_UVW_AXI4_TO_DDR4 +UVHS_RUNTIME_LIB_DIR := $(UVHS_WORK_DIR)/.uvhs-runtime-lib +UVHS_COMPAT_BIN := $(UVHS_WORK_DIR)/.uvhs-compat-bin +UVHS_RUNTIME_DB := $(UVHS_WORK_DIR)/hw.dat +UVHS_RUNTIME_WORK_DIR := $(UVHS_WORK_DIR)/runtime-work +UVHS_RUNTIME_COMMAND_FILE := $(UVHS_RUNTIME_WORK_DIR)/command.tcl +UVHS_RUNTIME_PID_FILE := $(UVHS_RUNTIME_WORK_DIR)/uv_shell.pid +UVHS_RUNTIME_READY_FILE := $(UVHS_RUNTIME_WORK_DIR)/uv_shell.ready +UVHS_RUNTIME_LOG := $(UVHS_RUNTIME_WORK_DIR)/uv_shell.log +UVHS_RUNTIME_TIMEOUT ?= 600 + +UVHS_ILA_TIMEOUT ?= 60 +UVHS_ILA_DEPTH ?= 1000000 +UVHS_ILA_POSITION ?= 0 +UVHS_ILA_CLOCK ?= +UVHS_ILA_GATED_CLOCK ?= +UVHS_ILA_GATED_CLOCK_FREQUENCY ?= 25000000 +UVHS_ILA_DIR := $(UVHS_RUNTIME_WORK_DIR)/UHD/uvhs_ila +UVHS_ILA_USDB := $(UVHS_ILA_DIR)/UvData.usdb +UVHS_ILA_VCD := $(UVHS_ILA_DIR)/UvData.vcd + +UVHS_TOOL_ENV = \ + PATH="$$UV_ROOT/bin:$$UV_ROOT/lib/venv3.8/bin:$$UV_ROOT/lib/gcc10.3/bin:$$PATH" \ + MAKEFLAGS="$${MAKEFLAGS:+$$MAKEFLAGS }SHELL=/bin/bash" \ + UVHS_RUNTIME_LIB_DIR="$(UVHS_RUNTIME_LIB_DIR)" \ + UVHS_COMPAT_BIN="$(UVHS_COMPAT_BIN)" \ + UVSHELL_EXEC_NAME="$(UVHS_RUNTIME_DIR)/uv_shell_exec_compat.sh" + +UVHS_FLOW_ENV = \ + $(UVHS_TOOL_ENV) \ + UVHS_FLOW=1 \ + UVHS_PROBE_TCL="$(UVHS_PROBE_PATH)" \ + XDMA_LINK_WIDTH="$(XDMA_LINK_WIDTH)" \ + UVHS_KEEP_FPGAS="$(UVHS_KEEP_FPGAS)" \ + UVHS_LUT_FILL_RATE="$(UVHS_LUT_FILL_RATE)" \ + UVHS_LUT6_FILL_RATE="$(UVHS_LUT6_FILL_RATE)" + +.PHONY: uvhs uvhs_preflight uvhs_prepare \ + uvhs_frontend uvhs_backend uvhs_clean uvhs_write_bitstream \ + uvhs_halt_soc uvhs_reset_cpu uvhs_write_ddr uvhs_write_flash \ + uvhs_ila_arm uvhs_ila uvhs_vcd uvhs_ila_clear \ + uvhs_runtime_status uvhs_runtime_stop + +# Validate host tools and external inputs before starting a multi-hour build. +uvhs_preflight: + @bash -c 'set -euo pipefail; \ + for variable in UV_ROOT UV_XILINX_VIVADO UV_LICENSE; do \ + [[ -n "$${!variable:-}" ]] || { echo "ERROR: $$variable is not set" >&2; exit 1; }; \ + done; \ + [[ -n "$(CPU)" ]] || { echo "ERROR: CPU is not set" >&2; exit 1; }; \ + for command in bash python3 gzip ldconfig; do \ + command -v "$$command" >/dev/null || { echo "ERROR: command not found: $$command" >&2; exit 1; }; \ + done; \ + for executable in \ + "$$UV_ROOT/bin/uv_shell" "$$UV_ROOT/bin/uv_shell_exec" \ + "$$UV_XILINX_VIVADO/bin/vivado" \ + "$(UVHS_RUNTIME_DIR)/uv_shell_exec_compat.sh" \ + "$(UVHS_COMPILATION_DIR)/shell_compat.sh" \ + "$(UVHS_COMPILATION_DIR)/prepare_ip.sh" \ + "$(UVHS_ROOT_DIR)/tools/update_core_flist.sh"; do \ + [[ -x "$$executable" ]] || { echo "ERROR: executable not found: $$executable" >&2; exit 1; }; \ + done; \ + for file in \ + "$(UVHS_COMPILATION_DIR)/vivado_pre_opt.tcl" \ + "$(UVHS_COMPILATION_DIR)/partition.tcl" \ + "$(UVHS_TEMPLATE_DIR)/Makefile" \ + "$(UVHS_TEMPLATE_DIR)/script/1B_4F_HGC_assemble.tcl"; do \ + [[ -f "$$file" ]] || { echo "ERROR: file not found: $$file" >&2; exit 1; }; \ + done; \ + for directory in "$(CORE_DIR)" "$(UVHS_TEMPLATE_DIR)/script" "$(UVHS_UVW_AXI4_TO_DDR4_SRC)"; do \ + [[ -d "$$directory" ]] || { echo "ERROR: directory not found: $$directory" >&2; exit 1; }; \ + done; \ + if [[ -n "$(UVHS_PROBE_PATH)" && ! -f "$(UVHS_PROBE_PATH)" ]]; then \ + echo "ERROR: UVHS probe script not found: $(UVHS_PROBE_PATH)" >&2; exit 1; \ + fi' + +uvhs_prepare: uvhs_preflight + test -n "$(UVHS_WORK_DIR)" + rm -rf "$(UVHS_WORK_DIR)/script" + mkdir -p "$(UVHS_WORK_DIR)" + mkdir -p "$(UVHS_COMPAT_BIN)" + ln -sfn "$(UVHS_RUNTIME_DIR)/uv_shell_exec_compat.sh" \ + "$(UVHS_COMPAT_BIN)/python" + ln -sfn "$(UVHS_RUNTIME_DIR)/uv_shell_exec_compat.sh" \ + "$(UVHS_COMPAT_BIN)/python3" + cp -a "$(UVHS_TEMPLATE_DIR)/script" "$(UVHS_WORK_DIR)/" + cp -f "$(UVHS_TEMPLATE_DIR)/Makefile" "$(UVHS_WORK_DIR)/Makefile" + mkdir -p "$(UVHS_WORK_DIR)/rtl/soc" "$(UVHS_WORK_DIR)/rtl/device/pcie" + $(UVHS_FLOW_ENV) bash "$(UVHS_COMPILATION_DIR)/prepare_ip.sh" \ + "$(UVHS_ROOT_DIR)" "$(UVHS_WORK_DIR)" "$(CORE_DIR)" \ + "$(UVHS_EXPORT_IP_JOBS)" "$(UVHS_EXPORT_IP_FORCE)" \ + "$(UVHS_UVW_AXI4_TO_DDR4_SRC)" "$(UVHS_DDR_AXI_WIDTH)" + +uvhs_frontend: uvhs_prepare + bash "$(UVHS_ROOT_DIR)/tools/update_core_flist.sh" uvhs \ + "$(CORE_DIR)" "$(UVHS_WORK_DIR)" "$(CPU)" "$(UVHS_FILELIST)" \ + -- $(RTL_INCLUDE) + bash -c 'set -euo pipefail; cd "$(UVHS_WORK_DIR)"; \ + $(UVHS_FLOW_ENV) \ + bash "$$UV_ROOT/bin/uv_shell" -bypass_vivado_version_check \ + -s "$(UVHS_COMPILATION_DIR)/frontend_run.tcl" |& tee frontend_run.log; \ + grep -Fxq UVHS_FRONTEND_SUCCESS frontend_run.log' + +# Keep frontend and backend serialized even when the caller enables parallel make. +uvhs: uvhs_frontend + $(MAKE) uvhs_backend + +uvhs_backend: + bash -c 'set -euo pipefail; cd "$(UVHS_WORK_DIR)"; \ + $(UVHS_FLOW_ENV) \ + bash "$$UV_ROOT/bin/uv_shell" -bypass_vivado_version_check \ + -s "$(UVHS_COMPILATION_DIR)/backend_run.tcl" |& tee backend_run.log; \ + grep -Fxq UVHS_BACKEND_SUCCESS backend_run.log' + +# The process that downloads the database must retain its runtime ownership. +uvhs_write_bitstream: + test -d "$(UVHS_RUNTIME_DB)" + test -f "$(UVHS_RUNTIME_DIR)/runtime_server.tcl" + test -x "$(UVHS_RUNTIME_DIR)/runtime_session.sh" + mkdir -p "$(UVHS_RUNTIME_WORK_DIR)" + $(UVHS_TOOL_ENV) UVHS_DB_PATH="$(UVHS_RUNTIME_DB)" \ + UVHS_RUNTIME_WORK_DIR="$(UVHS_RUNTIME_WORK_DIR)" \ + UVHS_COMMAND_FILE="$(UVHS_RUNTIME_COMMAND_FILE)" \ + UVHS_RUNTIME_READY_FILE="$(UVHS_RUNTIME_READY_FILE)" \ + bash "$(UVHS_RUNTIME_DIR)/runtime_session.sh" start \ + "$(UVHS_RUNTIME_PID_FILE)" "$(UVHS_RUNTIME_READY_FILE)" \ + "$(UVHS_RUNTIME_LOG)" "$(UVHS_RUNTIME_COMMAND_FILE)" \ + "$(UVHS_RUNTIME_TIMEOUT)" \ + bash "$$UV_ROOT/bin/uv_shell" -rt_shell \ + -workdir "$(UVHS_RUNTIME_WORK_DIR)" \ + -script "$(UVHS_RUNTIME_DIR)/runtime_server.tcl" + +uvhs_runtime_status: + bash "$(UVHS_RUNTIME_DIR)/runtime_session.sh" check \ + "$(UVHS_RUNTIME_PID_FILE)" "$(UVHS_RUNTIME_READY_FILE)" + @echo "UVHS_RUNTIME_LOG=$(UVHS_RUNTIME_LOG)" + +define uvhs_runtime_command + bash "$(UVHS_RUNTIME_DIR)/runtime_session.sh" check \ + "$(UVHS_RUNTIME_PID_FILE)" "$(UVHS_RUNTIME_READY_FILE)" + bash "$(UVHS_RUNTIME_DIR)/runtime_session.sh" enqueue \ + "$(UVHS_RUNTIME_COMMAND_FILE)" "$(UVHS_RUNTIME_TIMEOUT)" $(1) +endef + +uvhs_halt_soc: + $(call uvhs_runtime_command,halt_soc) + +uvhs_reset_cpu: + $(call uvhs_runtime_command,reset_cpu) + +uvhs_write_ddr: + test -f "$(WORKLOAD)" + $(call uvhs_runtime_command,write_ddr "$(abspath $(WORKLOAD))" "$(UVHS_DDR_RTL_INST)" "$(UVHS_DDR_AXI_WIDTH)") + +uvhs_write_flash: + test -f "$(WORKLOAD)" + $(call uvhs_runtime_command,write_flash "$(abspath $(WORKLOAD))" 0x0 0x8000) + +uvhs_ila_arm: + test -f "$(TRIGGER)" + $(call uvhs_runtime_command,ila_arm \ + "$(abspath $(TRIGGER))" "$(UVHS_ILA_POSITION)" \ + "$(UVHS_ILA_GATED_CLOCK)" \ + "$(UVHS_ILA_GATED_CLOCK_FREQUENCY)") + +uvhs_ila: + $(call uvhs_runtime_command,ila_wait uvhs_ila \ + "$(UVHS_ILA_TIMEOUT)" "$(UVHS_ILA_DEPTH)" \ + "$(UVHS_ILA_CLOCK)") + test -s "$(UVHS_ILA_USDB)" + $(MAKE) uvhs_vcd + @echo "UVHS_ILA_USDB=$(UVHS_ILA_USDB)" + +uvhs_vcd: + test -x "$$UV_ROOT/uvd/uvs/bin/usdb2vcd" + test -s "$(UVHS_ILA_USDB)" + rm -f "$(UVHS_ILA_VCD)" + $(UVHS_TOOL_ENV) "$$UV_ROOT/uvd/uvs/bin/usdb2vcd" \ + -i "$(UVHS_ILA_USDB)" -o "$(UVHS_ILA_VCD)" + test -s "$(UVHS_ILA_VCD)" + @echo "UVHS_ILA_VCD=$(UVHS_ILA_VCD)" + +uvhs_ila_clear: + $(call uvhs_runtime_command,ila_clear) + +uvhs_runtime_stop: + $(call uvhs_runtime_command,stop) + bash "$(UVHS_RUNTIME_DIR)/runtime_session.sh" wait \ + "$(UVHS_RUNTIME_PID_FILE)" "$(UVHS_RUNTIME_READY_FILE)" \ + "$(UVHS_RUNTIME_COMMAND_FILE)" "$(UVHS_RUNTIME_TIMEOUT)" + +uvhs_clean: + @! bash "$(UVHS_RUNTIME_DIR)/runtime_session.sh" check \ + "$(UVHS_RUNTIME_PID_FILE)" >/dev/null 2>&1 || \ + { echo "ERROR: stop the UVHS runtime before cleaning" >&2; exit 1; } + test -n "$(UVHS_WORK_DIR)" + rm -rf "$(UVHS_WORK_DIR)"