From 440b48df5b0da71dc8665f816e53394a21686875 Mon Sep 17 00:00:00 2001 From: rezado <1908819406@qq.com> Date: Mon, 1 Jun 2026 15:32:52 +0800 Subject: [PATCH] fix(dts): reserve gcpt memory in FPGA templates Add reserved-memory nodes to XiangShan FPGA DTS templates so Linux leaves the gcpt checkpoint buffer unused. Document the gcpt reservation requirement in the Linux workloads image layout section. --- README.md | 2 ++ dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in | 11 +++++++++++ dts/xiangshan-fpga-noAIA-mem24g.dts.in | 11 +++++++++++ dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in | 11 +++++++++++ dts/xiangshan-fpga-noAIA-mem64g.dts.in | 11 +++++++++++ dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in | 11 +++++++++++ dts/xiangshan-fpga-noAIA-mem8g.dts.in | 11 +++++++++++ dts/xiangshan-fpga-noAIA-novec.dts.in | 11 +++++++++++ dts/xiangshan-fpga-noAIA.dts.in | 11 +++++++++++ 9 files changed, 90 insertions(+) diff --git a/README.md b/README.md index 1f42f6a..f3aef2b 100644 --- a/README.md +++ b/README.md @@ -57,6 +57,8 @@ For Linux workloads, the image assumes that execution begins at `0x80000000`, an Multiple device trees are built for each workload, each corresponds to a specific NEMU configuration. The device tree files are placed under the `dt` directory in the build output directory of that workload. The "default" device tree built into the image is `dt/xiangshan.dtb`. To replace the device tree, the following command can be used: +For DTS files used with gcpt, the beginning of RAM must be reserved with a `reserved-memory` node so Linux does not allocate or map the gcpt checkpoint buffer. The XiangShan FPGA DTS templates reserve 1 MiB at `0x80000000` for this purpose. + ```shell dd conv=notrunc bs=1024 seek=1536 if=dt/some_device.dtb of=fw_payload.bin ``` diff --git a/dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in index 861ad1b..74c2f57 100644 --- a/dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in @@ -93,6 +93,17 @@ reg = <0x0 0x80000000 0x6 0x00000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + reserved0: buffer@0 { + no-map; + reg = <0x0 0x80000000 0x0 0x100000>; + }; + }; + soc { #address-cells = <2>; #size-cells = <2>; diff --git a/dts/xiangshan-fpga-noAIA-mem24g.dts.in b/dts/xiangshan-fpga-noAIA-mem24g.dts.in index df47ca2..57f61c2 100644 --- a/dts/xiangshan-fpga-noAIA-mem24g.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem24g.dts.in @@ -94,6 +94,17 @@ reg = <0x0 0x80000000 0x6 0x00000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + reserved0: buffer@0 { + no-map; + reg = <0x0 0x80000000 0x0 0x100000>; + }; + }; + soc { #address-cells = <2>; #size-cells = <2>; diff --git a/dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in index f0cc705..7e2eb26 100644 --- a/dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in @@ -93,6 +93,17 @@ reg = <0x0 0x80000000 0x10 0x00000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + reserved0: buffer@0 { + no-map; + reg = <0x0 0x80000000 0x0 0x100000>; + }; + }; + soc { #address-cells = <2>; #size-cells = <2>; diff --git a/dts/xiangshan-fpga-noAIA-mem64g.dts.in b/dts/xiangshan-fpga-noAIA-mem64g.dts.in index 5236aec..350b118 100644 --- a/dts/xiangshan-fpga-noAIA-mem64g.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem64g.dts.in @@ -94,6 +94,17 @@ reg = <0x0 0x80000000 0x10 0x00000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + reserved0: buffer@0 { + no-map; + reg = <0x0 0x80000000 0x0 0x100000>; + }; + }; + soc { #address-cells = <2>; #size-cells = <2>; diff --git a/dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in index 12e110a..dd51c7a 100644 --- a/dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in @@ -94,6 +94,17 @@ reg = <0x0 0x80000000 0x2 0x00000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + reserved0: buffer@0 { + no-map; + reg = <0x0 0x80000000 0x0 0x100000>; + }; + }; + soc { #address-cells = <2>; #size-cells = <2>; diff --git a/dts/xiangshan-fpga-noAIA-mem8g.dts.in b/dts/xiangshan-fpga-noAIA-mem8g.dts.in index 1b172ea..b0f7fd1 100644 --- a/dts/xiangshan-fpga-noAIA-mem8g.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem8g.dts.in @@ -95,6 +95,17 @@ reg = <0x0 0x80000000 0x2 0x00000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + reserved0: buffer@0 { + no-map; + reg = <0x0 0x80000000 0x0 0x100000>; + }; + }; + soc { #address-cells = <2>; #size-cells = <2>; diff --git a/dts/xiangshan-fpga-noAIA-novec.dts.in b/dts/xiangshan-fpga-noAIA-novec.dts.in index fc6ecf8..8af193d 100644 --- a/dts/xiangshan-fpga-noAIA-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-novec.dts.in @@ -94,6 +94,17 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + reserved0: buffer@0 { + no-map; + reg = <0x0 0x80000000 0x0 0x100000>; + }; + }; + soc { #address-cells = <2>; #size-cells = <2>; diff --git a/dts/xiangshan-fpga-noAIA.dts.in b/dts/xiangshan-fpga-noAIA.dts.in index abe653a..99d9661 100644 --- a/dts/xiangshan-fpga-noAIA.dts.in +++ b/dts/xiangshan-fpga-noAIA.dts.in @@ -95,6 +95,17 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + reserved0: buffer@0 { + no-map; + reg = <0x0 0x80000000 0x0 0x100000>; + }; + }; + soc { #address-cells = <2>; #size-cells = <2>;