From 1ef262d62712a480b1e0275113030b42651d85f8 Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Mon, 17 Nov 2025 03:55:49 +0000 Subject: [PATCH 1/6] Initial plan From 922236c5a12f9e932f22d5a0c3817b8a5c3aceed Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Mon, 17 Nov 2025 04:09:27 +0000 Subject: [PATCH 2/6] Add comprehensive help descriptions to Kconfig files in libcpu and components Co-authored-by: Rbb666 <64397326+Rbb666@users.noreply.github.com> --- components/Kconfig | 93 +++ components/mprotect/Kconfig | 140 ++++ libcpu/Kconfig | 1252 ++++++++++++++++++++++++++++++++++- libcpu/aarch64/Kconfig | 138 ++++ 4 files changed, 1616 insertions(+), 7 deletions(-) diff --git a/components/Kconfig b/components/Kconfig index 0b9b3ab9d0e..c30c2cde19c 100644 --- a/components/Kconfig +++ b/components/Kconfig @@ -3,27 +3,120 @@ menu "RT-Thread Components" config RT_USING_COMPONENTS_INIT bool default n + help + Enable automatic component initialization framework. + + When enabled, components marked with INIT_EXPORT() macros will be + automatically initialized during system startup in proper order. + + Initialization levels (in order): + - INIT_BOARD_EXPORT: Board-level initialization (pins, clocks) + - INIT_PREV_EXPORT: Early driver initialization + - INIT_DEVICE_EXPORT: Device driver initialization + - INIT_COMPONENT_EXPORT: Component initialization + - INIT_ENV_EXPORT: Environment initialization + - INIT_APP_EXPORT: Application initialization + + Benefits: + - Automatic dependency ordering + - Cleaner code (no manual init function calls) + - Consistent initialization across components + + Note: Most RT-Thread components rely on this. Usually enabled automatically + by build system. config RT_USING_USER_MAIN bool default n + help + Use user-defined main() function as entry point. + + When enabled, RT-Thread creates a main thread that calls your main() function, + allowing traditional C programming style entry point. + + Without this option: You must manually create threads from application + With this option: Your main() function runs in a dedicated main thread + + The main thread: + - Runs after system initialization + - Has configurable stack size and priority + - Can use RT-Thread APIs like any other thread + - Can create additional threads + + Enable this for easier application development and familiar entry point. if RT_USING_USER_MAIN config RT_MAIN_THREAD_STACK_SIZE int "Set main thread stack size" default 6144 if ARCH_CPU_64BIT default 2048 + help + Stack size in bytes for the main thread. + + Default values: + - 64-bit architectures: 6144 bytes (6KB) + - 32-bit architectures: 2048 bytes (2KB) + + Increase if: + - Deep recursion in main() + - Large local variables + - Stack overflow in main thread + - Complex initialization requiring more stack + + Decrease for memory-constrained systems if main() is simple. + + Note: Each thread's stack is separate. This only affects main thread. config RT_MAIN_THREAD_PRIORITY int "Set main thread priority" default 4 if RT_THREAD_PRIORITY_8 default 10 if RT_THREAD_PRIORITY_32 default 85 if RT_THREAD_PRIORITY_256 + help + Priority of the main thread (lower number = higher priority). + + Default values scale with priority levels: + - 8 levels: Priority 4 (middle-low priority) + - 32 levels: Priority 10 (medium priority) + - 256 levels: Priority 85 (medium-low priority) + + Lower values (higher priority) if: + - Main thread needs to preempt other tasks + - Time-critical initialization in main() + + Higher values (lower priority) if: + - Main thread is just coordination/monitoring + - Other threads need priority over main + + Note: Priority 0 is highest, maximum is configured by RT_THREAD_PRIORITY_MAX. endif config RT_USING_LEGACY bool "Support legacy version for compatibility" default n + help + Enable compatibility layer for legacy RT-Thread versions. + + Provides deprecated APIs and compatibility shims for older code, + allowing gradual migration to newer RT-Thread versions. + + Includes: + - Deprecated API wrappers + - Legacy component interfaces + - Backward-compatible behavior + + Enable if: + - Porting code from older RT-Thread versions + - Using third-party libraries requiring legacy APIs + - Gradual migration strategy + + Disable for: + - New projects (use modern APIs) + - Smaller code size + - Better performance (no compatibility overhead) + + Note: Legacy support may be removed in future versions. + Plan to migrate to current APIs. if RT_USING_CONSOLE rsource "finsh/Kconfig" diff --git a/components/mprotect/Kconfig b/components/mprotect/Kconfig index 82348cbd9bb..714a4b218ad 100644 --- a/components/mprotect/Kconfig +++ b/components/mprotect/Kconfig @@ -4,25 +4,165 @@ config RT_USING_MEM_PROTECTION bool "Enable memory protection" default n select RT_USING_HEAP + help + Enable memory protection framework using MPU (Memory Protection Unit). + + Provides hardware-based memory protection to prevent: + - Stack overflow and underflow + - Buffer overruns + - Unauthorized access to memory regions + - Corruption of kernel data structures + + Features: + - Per-thread memory protection + - Stack guard regions + - Configurable memory regions with access permissions + - Exclusive regions for sensitive data + + Requirements: + - CPU with MPU support (Cortex-M3/M4/M7/M33/R52, etc.) + - ARCH_MM_MPU or ARCH_ARM_MPU enabled + - RT_USING_HEAP (dynamic memory) + + Benefits: + - Catch memory bugs early (development) + - Improve system safety (production) + - Isolate thread memory spaces + + Costs: + - Context switch overhead (save/restore MPU regions) + - Configuration complexity + - Slight runtime overhead + + Ideal for safety-critical applications and debugging memory issues. config RT_USING_HW_STACK_GUARD bool "Enable hardware stack guard" default n select RT_USING_MEM_PROTECTION + help + Enable hardware-based stack overflow protection using MPU. + + Automatically creates guard regions at the end of each thread's stack + to detect stack overflow at the moment it occurs. + + How it works: + - Configures MPU region below stack as no-access + - Stack overflow triggers immediate MPU fault + - Exception handler identifies the overflowing thread + + Benefits: + - Immediate detection (vs periodic checks) + - Precise identification of overflow location + - No runtime overhead (hardware-based) + - Catches stack corruption before it spreads + + Requirements: + - RT_USING_MEM_PROTECTION enabled + - Sufficient MPU regions (at least 1 per thread) + + Recommended for: + - Development and debugging + - Safety-critical systems + - Systems with limited stack space + + Note: Requires one MPU region per thread. Check NUM_MEM_REGIONS configuration. if RT_USING_MEM_PROTECTION config USE_MEM_PROTECTION_EXAMPLES bool "Use memory protection examples" default y + help + Build and include memory protection example code. + + Provides demonstration code showing how to: + - Configure memory protection regions + - Set up stack guards + - Add exclusive regions + - Handle protection faults + + Useful for: + - Learning memory protection concepts + - Testing MPU functionality + - Debugging protection configurations + + Disable for production builds to save code space. config NUM_MEM_REGIONS int "Total number of memory protection regions supported by hardware" + help + Total number of MPU regions available in hardware. + + This depends on your CPU architecture: + - Cortex-M3/M4: Typically 8 regions + - Cortex-M7: 8 or 16 regions + - Cortex-M33/M85: 8 or 16 regions (configurable in silicon) + - Cortex-R52: 16 or 32 regions + + Check your MCU datasheet or reference manual for exact count. + + Usage breakdown: + - Stack guard per thread: 1 region per thread + - Exclusive regions: NUM_EXCLUSIVE_REGIONS + - Configurable per thread: NUM_CONFIGURABLE_REGIONS + + Formula: NUM_MEM_REGIONS = 1 (stack) + NUM_EXCLUSIVE_REGIONS + NUM_CONFIGURABLE_REGIONS + + Example for 8-region MPU with 2 threads: + - Thread 1 stack guard: 1 region + - Thread 2 stack guard: 1 region + - Shared exclusive regions: 2 regions + - Per-thread config: 2 regions per thread + Total: 2 + 2 + 4 = 8 regions config NUM_EXCLUSIVE_REGIONS int "Total number of exclusive memory regions added using rt_mprotect_add_exclusive_region API" + help + Number of shared exclusive memory protection regions. + + Exclusive regions are memory areas with specific access permissions + shared across all threads (e.g., peripheral registers, kernel data). + + Use cases: + - Protect peripheral registers from thread access + - Mark flash memory as read-only/execute-only + - Protect kernel data structures + - Define shared memory with specific permissions + + Example configurations: + - Peripheral protection: 1-2 regions + - Kernel data protection: 1 region + - Shared buffers: 0-2 regions + + Note: These regions are configured once and apply to all threads. + Set based on your system's protection requirements. config NUM_CONFIGURABLE_REGIONS int "Maximum number of configurable memory regions for each thread, excluding stack guard and exclusive regions added using rt_mprotect_add_exclusive_region API" + help + Per-thread configurable memory protection regions. + + These regions are specific to each thread and can be configured independently + for thread-specific memory protection needs. + + Use cases: + - Protect thread's private data buffers + - Restrict access to thread-local peripherals + - Define custom memory permissions per thread + + Calculation: + NUM_CONFIGURABLE_REGIONS = NUM_MEM_REGIONS - 1 (stack) - NUM_EXCLUSIVE_REGIONS + + Example for 8-region MPU with 2 exclusive regions: + NUM_CONFIGURABLE_REGIONS = 8 - 1 - 2 = 5 regions per thread + + More regions = more flexibility but: + - Increased configuration complexity + - Longer context switch time + - More memory for region descriptors + + Set based on your application's per-thread protection needs. + Typical values: 1-4 regions per thread. endif endmenu diff --git a/libcpu/Kconfig b/libcpu/Kconfig index b089b61725c..f3f50ffbe34 100644 --- a/libcpu/Kconfig +++ b/libcpu/Kconfig @@ -4,73 +4,395 @@ endif config ARCH_CPU_64BIT bool + help + Indicates that this architecture uses 64-bit addressing and data types. + When enabled, pointers and registers are 64-bit wide, providing access + to larger memory spaces (>4GB). This is automatically selected by 64-bit + architectures like AArch64, RISC-V64, and MIPS64. + + Impact: Affects memory layout, data structure sizes, and ABI conventions. config RT_USING_CACHE bool default n + help + Enable CPU cache support for data and instruction caches. + + When enabled, RT-Thread will provide cache management APIs (flush, invalidate) + and properly handle cache coherency during DMA operations and memory management. + This is essential for high-performance CPUs like Cortex-A and Cortex-M7. + + Typical use cases: + - DMA transfers requiring cache synchronization + - Memory-mapped I/O operations + - Multi-core systems requiring cache coherency + + Note: Automatically selected by architectures with cache support (e.g., Cortex-M7, + Cortex-A series, ARMv8). Improper cache management can lead to data corruption. config RT_USING_HW_ATOMIC bool default n + help + Enable hardware atomic operations support using CPU-specific instructions. + + When enabled, RT-Thread uses hardware atomic instructions (e.g., LDREX/STREX on ARM, + atomic instructions on RISC-V) for lock-free synchronization primitives, improving + performance and reducing interrupt latency compared to software implementations. + + Automatically selected by CPUs with atomic instruction support: + - ARM Cortex-M3 and above (LDREX/STREX) + - ARM Cortex-A series + - ARM Cortex-R series + - RISC-V with 'A' extension + + Benefits: Better performance for spinlocks, reference counting, and concurrent data structures. + No action required - this is automatically configured based on CPU architecture. config ARCH_CPU_BIG_ENDIAN bool + help + Indicates that this CPU uses big-endian byte ordering. + + In big-endian systems, the most significant byte is stored at the lowest memory address. + This affects how multi-byte data (integers, floats) are stored and accessed in memory. + + Most ARM, RISC-V, and x86 systems use little-endian. Big-endian is common in: + - Some PowerPC configurations + - MIPS systems (configurable) + - Network protocols (network byte order) + + Note: This must match your hardware configuration. Incorrect setting will cause + data corruption when accessing multi-byte values. config ARCH_ARM_BOOTWITH_FLUSH_CACHE bool default n + help + Flush and disable caches during system boot on ARM platforms. + + When enabled, the bootloader will flush and disable instruction and data caches + before jumping to RT-Thread kernel. This ensures clean cache state during initialization. + + Enable this when: + - Bootloader leaves caches in inconsistent state + - Transitioning from another OS or bootloader + - Debugging cache-related boot issues + + Note: Not needed for most configurations. Only enable if experiencing boot failures + related to stale cache data. config ARCH_CPU_STACK_GROWS_UPWARD bool default n + help + Indicates that the stack grows toward higher memory addresses (upward). + + Most architectures (ARM, RISC-V, x86, MIPS) use downward-growing stacks where + the stack pointer decreases as items are pushed. However, some architectures + like TI DSP C28x use upward-growing stacks. + + This setting affects: + - Stack pointer initialization and overflow detection + - Context switching and exception handling + - Stack boundary checking + + Note: This is architecture-specific and automatically configured. Do not change + unless porting to a new architecture with upward-growing stack. config RT_USING_CPU_FFS bool default n + help + Enable optimized Find First Set (FFS) implementation using CPU instructions. + + FFS finds the position of the first (least significant) bit set in a word. When enabled, + RT-Thread uses hardware instructions like CLZ (Count Leading Zeros) on ARM or equivalent + on other architectures for fast bit scanning operations. + + Used internally by: + - Scheduler for finding highest-priority ready thread + - Bitmap operations + - IPC mechanisms + + Automatically selected by CPUs with FFS support: + - ARM Cortex-M3 and above (CLZ instruction) + - ARM Cortex-A series + - ARM Cortex-R series + + Benefits: Significantly faster scheduler operation (O(1) vs O(n) thread selection). + No configuration needed - automatically enabled for supported CPUs. config ARCH_MM_MMU bool + help + Enable Memory Management Unit (MMU) support for virtual memory. + + MMU provides hardware-based virtual memory management, enabling: + - Virtual to physical address translation + - Memory protection between processes + - Demand paging and memory mapping + - Separate address spaces for different processes + + Required for: + - RT-Smart mode (user-space applications) + - Process isolation and protection + - Dynamic memory mapping (mmap) + - Copy-on-write mechanisms + + Automatically selected by MMU-capable architectures: + - ARM Cortex-A series + - AArch64 (ARMv8) + - RISC-V with Sv39/Sv48 paging + + Note: MMU requires proper page table setup and increases system complexity. + Only available on CPUs with hardware MMU support. config ARCH_MM_MPU bool + help + Enable Memory Protection Unit (MPU) support. + + MPU provides hardware-based memory protection without full virtual memory capabilities. + Unlike MMU, MPU works with physical addresses and has limited number of regions (typically 8-16). + + Features: + - Protect memory regions from unauthorized access + - Define region permissions (read, write, execute) + - Prevent stack overflow and buffer overruns + - Isolate kernel from user code + + Common use cases: + - Thread stack protection + - Peripheral register protection + - Code/data separation + - Safety-critical applications + + Available on: + - ARM Cortex-M0+/M3/M4/M7/M23/M33/M85 (with MPU option) + - ARM Cortex-R series + + Note: Less flexible than MMU but lower overhead. Suitable for microcontrollers + without MMU. Enable RT_USING_HW_STACK_GUARD for automatic stack protection. config ARCH_ARM bool + help + Select ARM architecture family support. + + ARM is a widely-used RISC architecture family for embedded systems and mobile devices. + This is automatically selected when choosing a specific ARM CPU variant. + + Supported ARM variants in RT-Thread: + - ARM9/ARM11: Legacy 32-bit ARM cores + - Cortex-M: Microcontroller profile (M0/M0+/M3/M4/M7/M23/M33/M85) + - Cortex-R: Real-time profile (R4/R52) + - Cortex-A: Application profile (A5/A7/A8/A9/A55) + - ARMv8: 64-bit architecture (Cortex-A53/A57/A72/A73) + + No direct configuration needed - select specific CPU type instead. config ARCH_ARM_CORTEX_M bool select ARCH_ARM + help + ARM Cortex-M microcontroller profile. + + Cortex-M is ARM's microcontroller-optimized architecture designed for low-power, + cost-sensitive embedded applications with deterministic interrupt handling. + + Features: + - Nested Vectored Interrupt Controller (NVIC) + - Low interrupt latency (typically 12-15 cycles) + - Thumb-2 instruction set for code density + - Optional MPU for memory protection + - Optional FPU (M4F/M7F variants) + + Variants: M0/M0+/M3/M4/M7/M23/M33/M85 + + Automatically selected when choosing specific Cortex-M CPU variant. config ARCH_ARM_CORTEX_R bool select ARCH_ARM + help + ARM Cortex-R real-time profile. + + Cortex-R is designed for high-performance real-time applications requiring + deterministic behavior and fault tolerance. + + Features: + - Tightly-coupled memory (TCM) for deterministic access + - Error detection and correction (ECC) + - Dual-core lockstep for safety-critical applications + - Low and deterministic interrupt latency + - Optional MPU or MMU + + Common applications: + - Automotive (ADAS, engine control) + - Industrial control systems + - Medical devices + - Hard real-time systems + + Variants: R4/R5/R52 + Automatically selected when choosing specific Cortex-R CPU variant. config ARCH_ARM_CORTEX_FPU bool + help + Enable Floating Point Unit (FPU) support for ARM Cortex processors. + + When enabled, RT-Thread will: + - Save/restore FPU registers during context switch + - Enable FPU coprocessor access + - Support hardware floating-point operations + + FPU variants: + - Cortex-M4F/M7F: Single-precision FPv4-SP + - Cortex-M7: Optional double-precision FPv5 + - Cortex-A: VFPv3/VFPv4/NEON + + Benefits: 10-100x performance improvement for floating-point math + Cost: Increased context switch time, larger stack frames + + Enable if your application requires: + - DSP operations + - Audio/video processing + - Scientific computations + - Graphics operations + + Note: Hardware must have FPU. Check your MCU datasheet. config ARCH_ARM_CORTEX_SECURE bool + help + Enable ARM TrustZone security extension support. + + TrustZone provides hardware-based isolation between secure and non-secure worlds, + enabling trusted execution environments (TEE). + + Features: + - Secure and non-secure memory regions + - Secure and non-secure peripheral access + - Secure state transitions + - Protection of cryptographic keys and sensitive data + + Available on: + - Cortex-M23/M33/M35P/M55/M85 (ARMv8-M) + - Cortex-A with Security Extensions + + Use cases: + - Secure boot + - Cryptographic operations + - Key storage + - Secure firmware updates + - Payment and DRM systems + + Note: Requires secure firmware and proper secure/non-secure memory partitioning. config ARCH_ARM_CORTEX_M0 bool select ARCH_ARM_CORTEX_M + help + ARM Cortex-M0 ultra-low-power microcontroller core. + + Smallest and most energy-efficient ARM processor, ideal for simple control applications. + + Features: + - ARMv6-M architecture + - 32-bit processor with Thumb instruction set (subset) + - Minimal interrupt latency + - No MPU, no FPU, no cache + - Very low gate count and power consumption + + Performance: ~0.9 DMIPS/MHz + Typical applications: Sensors, simple controllers, battery-powered devices + + Choose this for your BSP if using Cortex-M0 based MCU. config ARCH_ARM_CORTEX_M3 bool select ARCH_ARM_CORTEX_M select RT_USING_CPU_FFS select RT_USING_HW_ATOMIC + help + ARM Cortex-M3 mainstream microcontroller core. + + Balanced processor for general-purpose embedded applications with good performance + and energy efficiency. + + Features: + - ARMv7-M architecture + - Thumb-2 instruction set (full) + - Hardware divide instructions + - Optional MPU (8 regions) + - Atomic operations (LDREX/STREX) + - No FPU, no cache + + Performance: ~1.25 DMIPS/MHz + + Common use cases: + - Industrial control + - Consumer electronics + - Motor control + - IoT devices + + Examples: STM32F1xx, LPC17xx, EFM32 + Choose this for your BSP if using Cortex-M3 based MCU. config ARCH_ARM_MPU bool depends on ARCH_ARM select ARCH_MM_MPU + help + Enable Memory Protection Unit for ARM Cortex-M/R processors. + + Select this to enable MPU support on compatible ARM cores. The MPU provides + hardware-based memory protection with configurable regions. + + When enabled, you can: + - Protect thread stacks from overflow + - Restrict access to peripheral registers + - Enforce execute-never (XN) permissions + - Separate privileged and unprivileged memory + + Configuration: + - Number of regions: Typically 8 (Cortex-M3/M4) or 16 (Cortex-M7/M33) + - Region size: Must be power of 2, minimum 32 bytes (Cortex-M3/M4) or 256 bytes (ARMv8-M) + - Permissions: Read, write, execute, privileged/unprivileged + + Enable this along with RT_USING_HW_STACK_GUARD for automatic stack protection. + See components/mprotect/Kconfig for detailed MPU configuration. config ARCH_ARM_CORTEX_M4 bool select ARCH_ARM_CORTEX_M select RT_USING_CPU_FFS select RT_USING_HW_ATOMIC + help + ARM Cortex-M4 DSP-oriented microcontroller core. + + Enhanced version of M3 with DSP extensions and optional FPU, designed for + digital signal processing and motor control applications. + + Features: + - ARMv7E-M architecture + - DSP instructions (SIMD, saturating arithmetic, MAC) + - Optional single-precision FPU (FPv4-SP) + - Optional MPU (8 regions) + - Hardware divide and atomic operations + - No cache + + Performance: ~1.25 DMIPS/MHz (CPU), 10x faster for DSP operations with FPU + + Ideal for: + - Audio processing + - Motor control (FOC algorithms) + - Sensor fusion + - Real-time control loops + + Examples: STM32F4xx, K64F, nRF52, TM4C + Choose this for your BSP if using Cortex-M4 or M4F based MCU. config ARCH_ARM_CORTEX_M7 bool @@ -78,38 +400,223 @@ config ARCH_ARM_CORTEX_M7 select RT_USING_CPU_FFS select RT_USING_CACHE select RT_USING_HW_ATOMIC + help + ARM Cortex-M7 high-performance microcontroller core. + + Most powerful Cortex-M processor with superscalar architecture, cache, and + advanced features for demanding embedded applications. + + Features: + - ARMv7E-M architecture with 6-stage superscalar pipeline + - L1 instruction and data cache (configurable 0-64KB each) + - Optional single/double-precision FPU (FPv5) + - Tightly-coupled memory (TCM) for deterministic access + - Optional MPU (8 or 16 regions) + - DSP instructions and atomic operations + + Performance: ~2.14 DMIPS/MHz (up to 600MHz), 5 CoreMark/MHz + + Critical for cache management: + - Must flush cache before DMA reads from memory + - Must invalidate cache after DMA writes to memory + - Cache coherency APIs automatically enabled + + Ideal for: + - High-performance embedded systems + - Vision and image processing + - Advanced motor control + - Real-time communication protocols + + Examples: STM32F7xx/H7xx, i.MX RT, SAM V71 + Choose this for your BSP if using Cortex-M7 based MCU. config ARCH_ARM_CORTEX_M85 bool select ARCH_ARM_CORTEX_M select RT_USING_CPU_FFS select RT_USING_HW_ATOMIC + help + ARM Cortex-M85 next-generation high-performance microcontroller core. + + Latest and most powerful Cortex-M processor with AI/ML acceleration and + advanced security features (ARMv8.1-M architecture). + + Features: + - ARMv8.1-M architecture with Helium (M-Profile Vector Extension) + - TrustZone security + - L1 cache (optional) + - Optional single/double-precision FPU + - Optional MPU (8 or 16 regions) + - Pointer authentication and branch target identification + - DSP and atomic operations + + Performance: Up to 6.2 CoreMark/MHz + + Helium benefits: + - 5-15x performance for ML inference + - Enhanced DSP for signal processing + - Vector operations for parallel data processing + + Ideal for: + - Edge AI/ML applications + - Advanced image/audio processing + - Security-critical applications + - Next-generation IoT devices + + Examples: Future MCUs with Cortex-M85 + Choose this for your BSP if using Cortex-M85 based MCU. config ARCH_ARM_CORTEX_M23 bool select ARCH_ARM_CORTEX_M select RT_USING_HW_ATOMIC + help + ARM Cortex-M23 ultra-low-power core with TrustZone. + + Energy-efficient processor with security features, successor to Cortex-M0+. + + Features: + - ARMv8-M Baseline architecture + - TrustZone security extension + - Optional MPU (8 or 16 regions) + - Atomic operations (LDREX/STREX) + - Low power consumption + - No FPU, no cache + + Performance: ~1.0 DMIPS/MHz + + Key advantage: Hardware security with minimal area/power overhead + + Ideal for: + - Secure IoT devices + - Battery-powered secure sensors + - Payment terminals + - Smart cards + + Examples: Future secure IoT MCUs + Choose this for your BSP if using Cortex-M23 based MCU. config ARCH_ARM_CORTEX_M33 bool select ARCH_ARM_CORTEX_M select RT_USING_CPU_FFS select RT_USING_HW_ATOMIC + help + ARM Cortex-M33 mainstream core with TrustZone. + + Balanced processor combining Cortex-M4 performance with TrustZone security, + ideal for secure IoT and connected devices. + + Features: + - ARMv8-M Mainline architecture + - TrustZone security extension + - Optional single-precision FPU (FPv5) + - Optional MPU (8 or 16 regions) + - DSP instructions + - Atomic operations + - Optional cache (Cortex-M33 derivatives) + + Performance: ~1.5 DMIPS/MHz + + Security features: + - Secure/non-secure memory partitioning + - Secure function calls + - Stack limit checking + - Co-processor isolation + + Ideal for: + - Secure IoT gateways + - Industrial automation with security + - Connected consumer devices + - Secure bootloaders + + Examples: nRF91, LPC55xx, STM32L5xx + Choose this for your BSP if using Cortex-M33 based MCU. config ARCH_ARM_CORTEX_R bool select ARCH_ARM select RT_USING_HW_ATOMIC + help + ARM Cortex-R real-time processor family. + + High-performance real-time processors with deterministic behavior for + safety-critical and real-time systems. + + Common features across Cortex-R family: + - Low and deterministic interrupt latency + - Tightly-coupled memory (TCM) + - Error correction code (ECC) + - Optional MPU or MMU + - VFP floating-point + + Automatically selected when choosing specific Cortex-R variant (R4/R52). + See individual Cortex-R variant options for detailed specifications. config ARCH_ARM_CORTEX_R52 bool select ARCH_ARM_CORTEX_R + help + ARM Cortex-R52 safety-critical real-time core. + + Latest Cortex-R processor designed for ASIL-D automotive and IEC 61508 SIL-3 + industrial safety applications. + + Features: + - ARMv8-R architecture (32-bit) + - Dual-core lockstep for fault detection + - ECC on caches and TCM + - Optional MPU or MMU + - Virtualization extensions + - Single/double precision FPU + - NEON SIMD + + Performance: Up to 1.6 DMIPS/MHz per core + + Safety features: + - Redundant execution for error detection + - Memory protection and ECC + - Built-in self-test (BIST) + + Ideal for: + - Automotive ADAS and autonomous driving + - Industrial safety controllers (SIL-3) + - Medical devices + - Aerospace applications + + Choose this for your BSP if using Cortex-R52 based SoC. config ARCH_ARM_MMU bool select RT_USING_CACHE select ARCH_MM_MMU depends on ARCH_ARM + help + Enable MMU support for ARM Cortex-A processors. + + Provides full virtual memory management with page-based address translation. + Automatically selected by Cortex-A variants. + + Features: + - 4KB/16KB/64KB page sizes + - Two-level (LPAE: three-level) page tables + - Virtual memory for multiple processes + - Memory attributes (cacheable, bufferable, shareable) + - Access permissions (privileged, user, read-only, execute-never) + + Enables: + - RT-Smart user-space applications + - Memory protection between processes + - Demand paging and swapping + - Memory-mapped files (mmap) + - Shared memory between processes + + Performance impact: + - TLB (Translation Lookaside Buffer) misses add latency + - Page table walks on TLB miss + - Requires proper cache and TLB management + + Note: Automatically enabled for Cortex-A. Required for RT-Smart mode. if RT_USING_SMART config KERNEL_VADDR_START @@ -119,21 +626,89 @@ if RT_USING_SMART default 0xffffffc000000000 if ARCH_RISCV && ARCH_REMAP_KERNEL default 0x80000000 if ARCH_RISCV depends on ARCH_MM_MMU + help + Starting virtual address for kernel space in RT-Smart mode. + + This defines where the kernel is mapped in the virtual address space. + The kernel typically resides in the upper half of the address space to + separate it from user-space applications. + + Default values: + - ARMv8 (64-bit): 0xffff000000000000 (upper 256TB) + - ARM (32-bit): 0xc0000000 (upper 1GB, Linux-compatible) + - RISC-V with remap: 0xffffffc000000000 + - RISC-V standard: 0x80000000 (2GB mark) + + User-space applications use addresses below this value. + + Note: Must be aligned to architecture's virtual memory requirements. + Changing this requires recompiling all kernel and user-space code. config RT_IOREMAP_LATE bool "Support to create IO mapping in the kernel address space after system initlalization." default n depends on ARCH_ARM_CORTEX_A depends on ARCH_MM_MMU + help + Enable dynamic I/O memory remapping after system initialization. + + When enabled, allows mapping device I/O memory into kernel virtual address + space at runtime using rt_ioremap(). This is useful for: + - Hot-pluggable devices + - Runtime device discovery (device tree) + - Drivers loaded after boot + - Flexible peripheral address mapping + + Without this option, all I/O mappings must be established during early boot. + + Impact: + - Slightly increased memory overhead for dynamic mapping tables + - Additional TLB entries for I/O regions + + Enable if you need runtime flexibility for device driver loading or + working with device tree-based systems. endif config ARCH_ARM_ARM9 bool select ARCH_ARM + help + ARM9 processor family (legacy ARMv4T/ARMv5 architecture). + + Classic ARM architecture used in many embedded systems from the 2000s. + Now largely superseded by Cortex-A for application processors. + + Features: + - 5-stage pipeline + - MMU for virtual memory + - Separate instruction and data caches + - ARM and Thumb instruction sets + + Performance: ~1.1 DMIPS/MHz + + Examples: ARM926EJ-S (NXP i.MX, Atmel AT91SAM9) + Choose this if your BSP uses ARM9-based SoC. config ARCH_ARM_ARM11 bool select ARCH_ARM + help + ARM11 processor family (ARMv6 architecture). + + Enhanced ARM architecture with improved performance and SIMD extensions. + Bridges the gap between ARM9 and Cortex-A. + + Features: + - 8-stage pipeline + - MMU with improved TLB + - SIMD instructions + - Unaligned access support + - Hardware divide (some variants) + + Performance: ~1.25 DMIPS/MHz + + Examples: ARM1176JZF-S (Raspberry Pi 1, BCM2835) + Choose this if your BSP uses ARM11-based SoC. config ARCH_ARM_CORTEX_A bool @@ -141,54 +716,279 @@ config ARCH_ARM_CORTEX_A select ARCH_ARM_MMU select RT_USING_CPU_FFS select RT_USING_HW_ATOMIC + help + ARM Cortex-A application processor family. + + High-performance processors designed for complex operating systems and + rich applications (Linux, Android, RT-Smart). + + Common features: + - MMU for virtual memory (required) + - Multi-level caches (L1/L2/L3) + - VFP floating-point and NEON SIMD + - TrustZone security extensions + - Multi-core configurations (SMP) + - GIC (Generic Interrupt Controller) + + Typical applications: + - Industrial HMI and gateways + - Multimedia devices + - Automotive infotainment + - Edge computing + - RT-Smart mixed-criticality systems + + Variants: A5/A7/A8/A9/A15/A17/A35/A53/A55/A57/A72/A73 + + Automatically selected when choosing specific Cortex-A variant. if ARCH_ARM_CORTEX_A config RT_SMP_AUTO_BOOT bool default n + help + Automatically boot secondary CPU cores at system startup. + + When enabled, RT-Thread will start all available CPU cores during + initialization for symmetric multiprocessing (SMP). + + If disabled, secondary cores remain in reset/low-power state until + explicitly started by application code. + + Enable for: + - Multi-core load distribution + - Parallel task execution + - Maximum system performance + + Disable for: + - Power-sensitive applications + - Asymmetric multiprocessing (AMP) + - Single-core debugging + + Note: Requires RT_USING_SMP to be enabled. config RT_USING_GIC_V2 bool default n + help + Use ARM Generic Interrupt Controller version 2 (GICv2). + + GICv2 is the interrupt controller for Cortex-A processors, providing: + - Up to 1020 interrupt sources + - Interrupt priority and masking + - CPU interface for each core + - Distributor for routing interrupts to cores + - Software-generated interrupts (SGI) for inter-core communication + + Used in: + - Cortex-A5/A7/A8/A9/A15/A17 + - Single and multi-core SMP systems + + Mutually exclusive with GICv3. Select based on your SoC hardware. config RT_USING_GIC_V3 bool default n + help + Use ARM Generic Interrupt Controller version 3/4 (GICv3/GICv4). + + GICv3 is the enhanced interrupt controller for newer ARM processors: + - Improved scalability (supports more cores) + - System register access (no memory-mapped CPU interface) + - Locality-specific peripheral interrupts (LPI) + - Message-based interrupts + - GICv4: Direct injection of virtual interrupts + + Used in: + - Cortex-A55/A57/A72/A73 and newer + - ARMv8 (AArch64) systems + - Large SMP systems (>8 cores) + + Mutually exclusive with GICv2. Select based on your SoC hardware. config RT_NO_USING_GIC bool default y if !RT_USING_GIC_V2 && !RT_USING_GIC_V3 + help + No GIC interrupt controller in use. + + Automatically set when neither GICv2 nor GICv3 is selected. + This may indicate: + - Custom interrupt controller + - Legacy interrupt controller + - Configuration error + + Most Cortex-A systems require either GICv2 or GICv3. endif config ARCH_ARM_CORTEX_A5 bool select ARCH_ARM_CORTEX_A + help + ARM Cortex-A5 energy-efficient application processor. + + Entry-level Cortex-A processor offering lower cost and power than A9 + while maintaining application-class capabilities. + + Features: + - ARMv7-A architecture + - 1-4 cores, in-order execution + - Optional NEON SIMD and VFPv4 + - TrustZone security + - L1 cache, optional L2 + - GICv2 + + Performance: ~1.57 DMIPS/MHz + + Ideal for: Cost-sensitive IoT gateways, industrial HMI + Examples: Vybrid VF6xx (Cortex-A5 + Cortex-M4) + Choose this if your BSP uses Cortex-A5 based SoC. config ARCH_ARM_CORTEX_A7 bool select ARCH_ARM_CORTEX_A + help + ARM Cortex-A7 power-efficient application processor. + + Most power-efficient ARMv7-A processor, often paired with A15 in big.LITTLE + configurations or used standalone for cost-effective systems. + + Features: + - ARMv7-A architecture with hardware virtualization + - 1-4 cores, in-order execution + - VFPv4 and NEON standard + - TrustZone security + - L1 and L2 cache + - GICv2 + + Performance: ~1.9 DMIPS/MHz + Power: 40% lower than Cortex-A9 at same performance + + Ideal for: IoT gateways, set-top boxes, entry-level tablets + Examples: BCM2836 (Raspberry Pi 2), i.MX6UL, Allwinner A33 + Choose this if your BSP uses Cortex-A7 based SoC. config ARCH_ARM_CORTEX_A8 bool select ARCH_ARM_CORTEX_A + help + ARM Cortex-A8 general-purpose application processor. + + First Cortex-A processor, designed for multimedia and mobile applications. + + Features: + - ARMv7-A architecture + - Single core, 13-stage superscalar pipeline + - VFPv3 and NEON + - TrustZone security + - L1 and L2 cache + + Performance: ~2.0 DMIPS/MHz + + Ideal for: Industrial automation, multimedia systems + Examples: TI AM335x (BeagleBone), OMAP3 + Choose this if your BSP uses Cortex-A8 based SoC. config ARCH_ARM_CORTEX_A9 bool select ARCH_ARM_CORTEX_A + help + ARM Cortex-A9 high-performance application processor. + + Popular multi-core processor balancing performance and power efficiency. + + Features: + - ARMv7-A architecture + - 1-4 cores, out-of-order execution + - VFPv3 and NEON + - TrustZone security + - L1 cache per core, shared L2 + - GICv2 + + Performance: ~2.5 DMIPS/MHz per core + + Ideal for: Industrial gateways, automotive, network equipment + Examples: Zynq-7000 (A9 + FPGA), i.MX6, NVIDIA Tegra 2/3 + Choose this if your BSP uses Cortex-A9 based SoC. config ARCH_ARM_CORTEX_A55 bool select ARCH_ARM_CORTEX_A + help + ARM Cortex-A55 ultra-efficient 64-bit processor (ARMv8.2-A). + + DynamIQ-enabled processor for modern SMP and big.LITTLE configurations, + designed for power efficiency and AI/ML workloads. + + Features: + - ARMv8.2-A architecture (64-bit) + - 1-8 cores in DynamIQ cluster + - Dot product instructions for ML + - TrustZone and pointer authentication + - L1 and L2 cache, optional L3 + - GICv3 + + Performance: ~1.8 DMIPS/MHz (better IPC than A53) + + Ideal for: Mobile, automotive ADAS, edge AI + Examples: MediaTek Helio, Qualcomm Snapdragon 7xx/6xx + Choose this if your BSP uses Cortex-A55 based SoC. config ARCH_ARM_SECURE_MODE bool "Running in secure mode [ARM Cortex-A]" default n depends on ARCH_ARM_CORTEX_A + help + Run RT-Thread in ARM secure mode (TrustZone secure world). + + TrustZone divides the system into two execution environments: + - Secure world: Access to all resources, runs trusted code + - Non-secure world: Restricted access, runs normal applications + + Enable this when: + - RT-Thread acts as secure monitor or trusted OS + - Implementing secure boot chain + - Running in EL3 (ARMv8) or secure state (ARMv7) + - Providing secure services to non-secure OS + + Disable when: + - Running as normal OS in non-secure world + - No TrustZone partitioning needed + - Booting directly without secure monitor + + Impact: + - Changes memory access permissions + - Affects SCR (Secure Configuration Register) settings + - Influences interrupt routing + + Note: Most applications run in non-secure mode. Only enable if you're + implementing secure firmware or trusted execution environment. config RT_BACKTRACE_FUNCTION_NAME bool "To show function name when backtrace." default n depends on ARCH_ARM_CORTEX_A + help + Display function names in backtrace/call stack dumps. + + When enabled, exception handlers and assertion failures will show + symbolic function names in addition to addresses, making debugging easier. + + Requires: + - Debug symbols in the binary + - Symbol table in memory or accessible + - Additional processing during backtrace + + Benefits: + - Easier identification of crash location + - Better error reports + - Faster debugging + + Costs: + - Slightly larger binary (symbol information) + - Increased backtrace processing time + + Recommended for development builds. May be disabled for production + to save space and improve backtrace speed. config ARCH_ARMV8 bool @@ -197,69 +997,351 @@ config ARCH_ARMV8 select RT_USING_CPU_FFS select ARCH_USING_ASID select ARCH_USING_IRQ_CTX_LIST + help + ARM 64-bit architecture (ARMv8-A / AArch64). + + Modern 64-bit ARM architecture for high-performance application processors. + Represents major architectural evolution from ARMv7 with enhanced features. + + Key features: + - 64-bit addressing and registers (can also run 32-bit code in AArch32 mode) + - Exception levels (EL0-EL3) for privilege separation + - Enhanced virtual memory (48-bit addressing, up to 256TB) + - ASID (Address Space ID) for efficient context switching + - Improved SIMD (Advanced SIMD / NEON) + - Hardware virtualization support + - Scalable Vector Extension (SVE) on some variants + + Advantages over ARMv7: + - More registers (31 general-purpose 64-bit registers) + - Larger addressable memory (>4GB) + - Better performance and efficiency + - Enhanced security features + + Processors: Cortex-A53/A57/A72/A73/A75/A76, Neoverse, Apple M-series + + Automatically selected by AArch64 BSP configurations. + Required for RT-Smart on 64-bit ARM platforms. config ARCH_MIPS bool + help + MIPS (Microprocessor without Interlocked Pipeline Stages) architecture. + + Classic RISC architecture used in embedded systems, networking equipment, + and consumer electronics. + + Features: + - Simple load/store RISC design + - Configurable endianness (big or little) + - Optional FPU and DSP extensions + - Hardware multithreading (MIPS MT) + + Common applications: + - Network routers and switches + - Set-top boxes + - Gaming consoles + - Embedded Linux systems + + Variants: MIPS32, MIPS64, microMIPS + Choose this if your BSP uses MIPS-based SoC. config ARCH_MIPS64 bool select ARCH_CPU_64BIT + help + MIPS 64-bit architecture. + + 64-bit extension of MIPS architecture providing: + - 64-bit addressing and registers + - Backward compatible with MIPS32 code + - Enhanced performance for 64-bit operations + - Access to larger memory spaces + + Applications: High-end networking equipment, servers + Examples: Cavium OCTEON, Loongson processors + Choose this if your BSP uses MIPS64-based SoC. config ARCH_MIPS_XBURST bool select ARCH_MIPS + help + Ingenic XBurst MIPS-based processor family. + + Customized MIPS architecture optimized for mobile and multimedia applications + by Ingenic Semiconductor. + + Features: + - MIPS32-compatible core with enhancements + - Low power consumption + - Integrated multimedia accelerators + + Common applications: Handheld devices, e-readers, IoT + Examples: JZ47xx series SoCs + Choose this if your BSP uses Ingenic XBurst processor. config ARCH_ANDES bool + help + Andes RISC-V based architecture. + + Custom RISC-V implementation by Andes Technology with proprietary extensions + for enhanced performance and features. + + Features: + - RISC-V ISA with Andes-specific extensions + - CoDense (16-bit instruction compression) + - StackSafe for stack protection + - PowerBrake for power management + + Applications: AIoT, storage controllers, automotive + Choose this if your BSP uses Andes processor core. config ARCH_CSKY bool + help + C-SKY CPU architecture. + + Chinese-designed processor architecture (now part of Alibaba's T-Head). + + Features: + - 16/32-bit RISC architecture + - Low power and small code size + - DSP extensions + + Applications: IoT devices, consumer electronics + Choose this if your BSP uses C-SKY based processor. config ARCH_POWERPC bool + help + PowerPC architecture. + + High-performance RISC architecture traditionally used in embedded and + server applications. + + Features: + - Big-endian (configurable to little-endian on some models) + - AltiVec SIMD on some variants + - Strong memory consistency model + + Applications: Networking equipment, aerospace, industrial control + Examples: MPC5xxx, QorIQ series + Choose this if your BSP uses PowerPC processor. config ARCH_RISCV bool + help + RISC-V open standard instruction set architecture. + + Modern, modular, open-source ISA designed for efficiency and extensibility. + Gaining rapid adoption in embedded systems, IoT, and AI/ML applications. + + Key advantages: + - Open standard (no licensing fees) + - Modular design (choose only needed extensions) + - Simple and clean architecture + - Growing ecosystem and vendor support + + Base ISAs: RV32I (32-bit), RV64I (64-bit) + Common extensions: + - M: Integer multiplication/division + - A: Atomic instructions + - F: Single-precision floating-point + - D: Double-precision floating-point + - C: Compressed 16-bit instructions + - V: Vector operations + + Examples: SiFive, Allwinner D1, ESP32-C3/C6, GigaDevice GD32V + + Automatically selected when choosing RV32 or RV64 variant. config ARCH_RISCV_FPU bool + help + RISC-V floating-point unit support. + + Enable hardware floating-point operations using RISC-V F and/or D extensions. + Automatically selected by ARCH_RISCV_FPU_S or ARCH_RISCV_FPU_D. + + When enabled: + - FPU registers (f0-f31) saved/restored during context switch + - Hardware FP instructions used by compiler + - Significant performance improvement for floating-point math + + Note: CPU must have F and/or D extension support. config ARCH_RISCV_VECTOR bool + help + RISC-V Vector Extension (RVV) support. + + Enable RISC-V Vector Extension for SIMD operations, ideal for data-parallel + workloads like DSP, image processing, and AI/ML inference. + + Features: + - Vector registers with configurable length (VLEN) + - Vector arithmetic, logic, and memory operations + - Predication and masking + - Auto-vectorization by compiler + + Benefits: + - 4-10x performance for vectorizable workloads + - Efficient memory access patterns + - Scalable across different vector lengths + + Applications: Signal processing, multimedia, ML inference + + Note: Requires CPU with V extension (ratified v1.0). + Select VLEN based on your hardware specification. if ARCH_RISCV_VECTOR choice ARCH_VECTOR_VLEN prompt "RISCV Vector Vlen" default ARCH_VECTOR_VLEN_128 + help + Select the vector register length (VLEN) for RISC-V Vector Extension. + + VLEN defines the width of vector registers in bits. This must match + your hardware's vector implementation. + + Common VLEN values: + - 128-bit: Entry-level vector implementations, good balance + - 256-bit: Higher throughput, more aggressive vectorization + + Larger VLEN: + + More data processed per instruction + + Better performance for vector operations + - Larger context switch overhead + - More silicon area required + + Check your CPU documentation for supported VLEN. config ARCH_VECTOR_VLEN_128 bool "128" + help + 128-bit vector register length. + + Standard choice for embedded RISC-V processors with vector support. + Provides good performance/area balance. + + Choose this for most RISC-V vector implementations. + config ARCH_VECTOR_VLEN_256 bool "256" + help + 256-bit vector register length. + + Wider vector registers for higher throughput in data-parallel workloads. + Requires more silicon area and increases context switch time. + + Choose this only if your CPU supports 256-bit VLEN. endchoice endif config ARCH_RISCV_FPU_S select ARCH_RISCV_FPU bool + help + RISC-V single-precision floating-point (F extension). + + Enable support for 32-bit (float) floating-point operations in hardware. + + Features: + - 32 single-precision FP registers (f0-f31) + - IEEE 754 single-precision arithmetic + - FP load/store, arithmetic, conversion instructions + + Sufficient for many embedded applications requiring FP without the + overhead of double-precision. + + Automatically selected by BSP when CPU has F extension. config ARCH_RISCV_FPU_D select ARCH_RISCV_FPU bool + help + RISC-V double-precision floating-point (D extension). + + Enable support for 64-bit (double) floating-point operations in hardware. + Includes F extension functionality. + + Features: + - 32 double-precision FP registers (f0-f31, 64-bit wide) + - IEEE 754 double-precision arithmetic + - Both single and double-precision operations + + Required for: + - High-precision scientific computations + - Financial calculations + - Applications requiring >7 significant digits + + Note: D extension requires F extension as prerequisite. + Automatically selected by BSP when CPU has D extension. config ARCH_RISCV32 select ARCH_RISCV bool + help + RISC-V 32-bit architecture (RV32). + + 32-bit RISC-V implementation optimized for resource-constrained + embedded systems and microcontrollers. + + Features: + - 32-bit addressing (4GB address space) + - 32 general-purpose 32-bit registers + - Compact code size with C extension + - Lower power consumption + + Ideal for: + - Microcontrollers and IoT devices + - Cost-sensitive applications + - Battery-powered systems + + Common variants: RV32IMAC, RV32IMAFC + Examples: ESP32-C3, GigaDevice GD32VF103, Nuclei Bumblebee + + Choose this if your BSP uses 32-bit RISC-V processor. config ARCH_RISCV64 select ARCH_RISCV select ARCH_CPU_64BIT bool + help + RISC-V 64-bit architecture (RV64). + + 64-bit RISC-V implementation for high-performance embedded systems + and application processors. + + Features: + - 64-bit addressing (16 exabyte address space) + - 32 general-purpose 64-bit registers + - Backward compatible with RV32 software (with proper toolchain) + - Better performance for 64-bit arithmetic + + Ideal for: + - Application processors + - RT-Smart user-space applications + - Systems requiring >4GB memory + - High-performance embedded Linux + + Common variants: RV64IMAC, RV64GC + Examples: SiFive U74, Allwinner D1 (C906), Kendryte K210 + + Choose this if your BSP uses 64-bit RISC-V processor. if ARCH_RISCV64 config ARCH_USING_NEW_CTX_SWITCH bool default y + help + Use optimized context switch implementation for RISC-V 64-bit. + + Enables improved context switching with better performance and + smaller code size. This is the recommended implementation for RV64. + + Automatically enabled for RISC-V 64-bit. No manual configuration needed. config ARCH_USING_RISCV_COMMON64 bool @@ -267,43 +1349,199 @@ if ARCH_RISCV64 select RT_USING_CPUTIME select ARCH_USING_NEW_CTX_SWITCH help - Using the common64 implementation under ./libcpu/risc-v + Use common 64-bit RISC-V implementation under ./libcpu/risc-v/common64. + + Provides unified, optimized implementation for 64-bit RISC-V cores: + - Standard context switch routines + - Exception and interrupt handling + - MMU/PMP management + - CPU time measurement + + Benefits: + - Code reuse across different RV64 cores + - Well-tested implementation + - Consistent behavior + + Enable this for standard RV64 cores (SiFive U74, T-Head C906, etc.) + unless you have specific custom requirements. endif config ARCH_REMAP_KERNEL bool depends on RT_USING_SMART help - Remapping kernel image to high virtual address region + Remap kernel image to high virtual address region. + + In RT-Smart mode, move kernel to upper virtual memory region to separate + it from user-space, similar to Linux kernel layout. + + Benefits: + - Clear separation between kernel and user address spaces + - User applications can use lower addresses (0x0 upward) + - Prevents accidental user access to kernel memory + - Compatible with standard executable loaders + + Memory layout with remapping: + - User space: 0x00000000 - KERNEL_VADDR_START + - Kernel space: KERNEL_VADDR_START - 0xFFFFFFFF... + + Required for: Full RT-Smart user-space isolation + Note: Increases boot time slightly due to remapping overhead. config ARCH_USING_ASID bool depends on RT_USING_SMART help - Using ASID support from architecture + Enable Address Space ID (ASID) support from architecture. + + ASID is a hardware feature that tags TLB (Translation Lookaside Buffer) + entries with process identifiers, avoiding TLB flushes on context switch. + + Benefits: + - Faster context switches between processes + - Better TLB utilization (multiple processes' translations cached) + - Reduced MMU overhead + + Without ASID: TLB must be flushed on every context switch (expensive) + With ASID: TLB entries for multiple processes coexist (efficient) + + Performance impact: Can reduce context switch time by 50-70% + + Automatically enabled for: + - ARMv8 (8-bit or 16-bit ASID) + - Some ARMv7-A implementations + - RISC-V with ASID support + + Note: Requires MMU with ASID support. Automatically selected by + compatible architectures. config ARCH_IA32 bool + help + Intel IA-32 (x86 32-bit) architecture. + + 32-bit x86 architecture for PC-compatible systems and embedded x86 platforms. + + Features: + - CISC architecture + - Segmented memory model (legacy) or flat model + - x87 FPU, MMX, SSE extensions + - Paging and segmentation + + Applications: Industrial PCs, legacy embedded systems, virtualization hosts + Examples: Intel Atom, AMD Geode + + Choose this if your BSP uses x86 32-bit processor. config ARCH_TIDSP bool + help + Texas Instruments DSP architecture family. + + Specialized processors for digital signal processing applications. + + Features: + - Optimized for real-time signal processing + - Harvard architecture (separate program/data memory) + - Hardware multipliers and MAC units + - Low-latency interrupt handling + + Applications: Motor control, audio processing, power electronics + + Automatically selected by specific TI DSP variant (e.g., C28x). config ARCH_TIDSP_C28X bool select ARCH_TIDSP select ARCH_CPU_STACK_GROWS_UPWARD + help + Texas Instruments C28x DSP architecture. + + Fixed-point DSP optimized for real-time control applications, + especially motor control and power conversion. + + Features: + - 32-bit fixed-point architecture + - Upward-growing stack (unusual characteristic) + - Single-cycle MAC operations + - Fast interrupt response (<50ns) + - Floating-point unit (C28x+FPU variants) + + Ideal for: + - Digital motor control (FOC, vector control) + - Power inverters and converters + - Solar inverters + - Industrial drives + + Examples: TMS320F28xxx series + + Note: Stack grows upward unlike most architectures. + Choose this if your BSP uses TI C28x DSP. config ARCH_HOST_SIMULATOR bool - -config ARCH_CPU_STACK_GROWS_UPWARD - bool - default n + help + Host machine simulator (running RT-Thread on development PC). + + Allows running RT-Thread as a user-space application on Linux, Windows, + or macOS for development, testing, and debugging without physical hardware. + + Features: + - Rapid prototyping and testing + - Debugger-friendly (use GDB, Visual Studio debugger) + - File system access to host files + - Network simulation + + Use cases: + - Algorithm development and testing + - Application logic verification + - CI/CD automated testing + - Learning RT-Thread without hardware + + Note: Timing behavior differs from real hardware. Not suitable for + real-time performance validation. + + Choose this for simulator-based BSP (e.g., qemu-vexpress-a9, simulator). config ARCH_USING_HW_THREAD_SELF bool default n + help + Use hardware register to identify current thread (thread self-identification). + + Some architectures provide dedicated registers or instructions to identify + the currently executing thread without memory access. + + Benefits: + - Faster rt_thread_self() operation (single register read) + - Reduced memory bandwidth + - Better performance in multi-core systems + + Examples: + - ARM: TPIDRURO/TPIDR_EL0 register + - x86: FS/GS segment registers + - RISC-V: Some implementations use tp register + + Automatically enabled by architectures supporting this feature. + No manual configuration needed. config ARCH_USING_IRQ_CTX_LIST bool default n + help + Use interrupt context list for nested interrupt handling. + + Maintains a list of interrupt contexts for proper nested interrupt + management, especially important for complex interrupt scenarios. + + Benefits: + - Correct handling of deeply nested interrupts + - Proper context tracking in multi-level interrupt systems + - Better debugging of interrupt-related issues + + Overhead: + - Slight increase in interrupt entry/exit time + - Small memory overhead for context list + + Automatically enabled by architectures requiring it (e.g., ARMv8). + No manual configuration needed. diff --git a/libcpu/aarch64/Kconfig b/libcpu/aarch64/Kconfig index 5429751d3a1..222052a21ff 100644 --- a/libcpu/aarch64/Kconfig +++ b/libcpu/aarch64/Kconfig @@ -2,24 +2,162 @@ menu "AArch64 Architecture Configuration" config ARCH_TEXT_OFFSET hex "Text offset" default 0x200000 + help + Offset of kernel text section from start of RAM. + + Defines where the kernel code (.text section) is located relative to + the beginning of physical RAM. This space before the kernel is typically + reserved for: + - Bootloader and device tree blob (DTB) + - Initial page tables + - Boot-time data structures + + Default 0x200000 (2MB): + - Provides 2MB for bootloader and DTB + - Aligns with common ARM64 configurations + - Compatible with 2MB page granularity + + Only change if you have specific bootloader requirements or memory layout. + config ARCH_RAM_OFFSET hex "RAM offset" default 0 + help + Physical address offset of the RAM start. + + Defines the starting physical address of system RAM. On many systems, + RAM doesn't start at address 0x0. + + Common values: + - 0x00000000: RAM starts at address 0 (some SoCs) + - 0x40000000: Common for many ARM SoCs + - 0x80000000: Some development boards + + This must match your hardware memory map. Check your SoC datasheet + or bootloader configuration. + + Default 0 means RAM starts at physical address 0x0. + config ARCH_SECONDARY_CPU_STACK_SIZE int "Secondary CPU stack size" default 4096 + help + Stack size for secondary CPU cores in multi-core (SMP) systems. + + Each secondary CPU core (CPU1, CPU2, etc.) needs its own stack for + initialization and exception handling before the scheduler starts. + + Default 4096 bytes (4KB): + - Sufficient for standard initialization + - Handles nested exceptions during boot + + Increase if: + - Experiencing secondary CPU boot failures + - Complex initialization routines + - Deep call chains during CPU startup + + Total memory used: (Number of secondary cores) × stack size + + Note: After scheduler starts, each thread has its own stack. + config ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS bool default y + help + ARMv8 supports efficient unaligned memory access. + + ARMv8 architecture can access unaligned memory addresses (addresses not + aligned to word boundaries) without performance penalty or exceptions. + + Benefits: + - Simpler code (no manual alignment required) + - Network packet processing (headers often unaligned) + - Reduced padding in data structures + + This is automatically enabled for ARMv8 - no configuration needed. + + Note: Some embedded systems may disable this for deterministic timing + or to catch alignment bugs, but ARMv8 handles it efficiently in hardware. + config ARCH_USING_GENERIC_CPUID bool "Using generic cpuid implemenation" select ARCH_USING_HW_THREAD_SELF default y if RT_USING_OFW default n + help + Use generic CPU identification implementation for multi-core systems. + + Provides standardized method to identify which CPU core is currently + executing, essential for SMP (Symmetric Multi-Processing). + + When enabled: + - Reads MPIDR_EL1 register for CPU ID + - Maps hardware CPU IDs to logical CPU numbers + - Enables proper per-CPU data structures + + Required for: + - SMP systems with multiple cores + - Per-CPU statistics and profiling + - CPU affinity and core-specific operations + + Automatically enabled when using OpenFirmware/Device Tree (RT_USING_OFW). + + Enable if you have multi-core ARMv8 system. Disable for single-core + to save minimal overhead. + config ARCH_HEAP_SIZE hex "Size of system heap" default 0x4000000 + help + Size of system heap for dynamic memory allocation. + + Defines the amount of memory available for rt_malloc() and related + dynamic allocation functions. + + Default 0x4000000 (64MB): + - Suitable for application-class systems with RT-Smart + - Supports moderate number of dynamic allocations + + Adjust based on: + - Available RAM in your system + - Application memory requirements + - Static vs dynamic allocation strategy + + Smaller values for resource-constrained systems. + Larger values for systems with abundant RAM and heavy dynamic allocation. + + Note: Actual available memory depends on total RAM size. + + Example configurations: + - 128MB RAM system: 0x4000000 (64MB) or less + - 256MB RAM system: 0x8000000 (128MB) or more + - 1GB+ RAM system: 0x20000000 (512MB) or more + config ARCH_INIT_PAGE_SIZE hex "Size of init page region" default 0x200000 + help + Size of initial page table region for early boot. + + Reserves memory for page tables used during system initialization + before the full memory management is set up. + + Default 0x200000 (2MB): + - Sufficient for initial kernel mappings + - Covers typical early boot requirements + - Aligns with 2MB page granularity + + This memory is used for: + - Initial MMU page table entries + - Early kernel virtual memory mappings + - Temporary boot-time allocations + + Increase if: + - Experiencing boot failures related to page tables + - Large kernel image + - Extensive early I/O mappings + + Decrease for memory-constrained systems (minimum ~1MB). + + Note: After full MM initialization, regular page allocation takes over. endmenu From 0978768baeec1e455359fd267a2655694a7083b3 Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Mon, 17 Nov 2025 08:48:41 +0000 Subject: [PATCH 3/6] Enhance Kconfig help for finsh and dfs components Co-authored-by: Rbb666 <64397326+Rbb666@users.noreply.github.com> --- components/dfs/Kconfig | 287 ++++++++++++++++++++++++++++++++++++++- components/finsh/Kconfig | 233 ++++++++++++++++++++++++++++++- 2 files changed, 516 insertions(+), 4 deletions(-) diff --git a/components/dfs/Kconfig b/components/dfs/Kconfig index 23799d1b44e..bc92c698c9e 100644 --- a/components/dfs/Kconfig +++ b/components/dfs/Kconfig @@ -5,16 +5,72 @@ config RT_USING_DFS select RT_USING_MUTEX default y help - The device file system is a light weight virtual file system. + DFS (Device File System) is RT-Thread's lightweight virtual file system. + + Provides unified file system abstraction layer supporting: + - Multiple file system types (FAT, ROM-FS, RAM-FS, NFS, etc.) + - POSIX-like file operations (open, read, write, close) + - Device file access (/dev/uart1, /dev/spi0, etc.) + - Mount points for different file systems + - Working directory support + + Features: + - Small footprint (~5-10KB depending on configuration) + - POSIX API compatibility for easier porting + - Multiple file systems can coexist + - Thread-safe operations with mutex protection + + Typical use cases: + - File logging and data storage + - Configuration file management + - Device access abstraction + - Network file systems (NFS) + + Enable for applications requiring file system support. + Disable for simple applications to save ~10-15KB ROM. if RT_USING_DFS config DFS_USING_POSIX bool "Using posix-like functions, open/read/write/close" default y + help + Enable POSIX-compliant file I/O API functions. + + Provides standard POSIX file operations: + - open(), close(), read(), write() + - lseek(), stat(), fstat() + - opendir(), readdir(), closedir() + - mkdir(), rmdir(), unlink(), rename() + + Benefits: + - Easier code porting from Linux/POSIX systems + - Familiar API for developers + - Better compatibility with third-party libraries + + Required for most applications using file operations. + Disable only if using custom file I/O API. config DFS_USING_WORKDIR bool "Using working directory" default y + help + Enable working directory (current directory) support. + + Features: + - Each thread can have its own working directory + - chdir() to change current directory + - Relative paths resolved from working directory + - getcwd() to get current directory path + + Essential for: + - Shell commands (cd, pwd) + - Relative path operations + - Multi-threaded file access with different contexts + + Memory cost: ~256 bytes per thread for path storage + + Recommended to keep enabled for convenience. + Disable to save minimal RAM if only using absolute paths. if RT_USING_DFS_V1 config RT_USING_DFS_MNTTABLE @@ -33,36 +89,138 @@ endif config DFS_FD_MAX int "The maximal number of opened files" default 16 + help + Maximum number of file descriptors that can be opened simultaneously + across all threads in the system. + + Default: 16 + + Each open file descriptor uses ~40-60 bytes of RAM. + Total memory: DFS_FD_MAX × ~50 bytes + + Increase if: + - Application opens many files concurrently + - Multiple threads access files simultaneously + - Getting "too many open files" errors + + Decrease to save RAM on memory-constrained systems (minimum ~4). + + Note: This is system-wide limit, not per-thread. choice RT_USING_DFS_VERSION prompt "The version of DFS" default RT_USING_DFS_V1 default RT_USING_DFS_V2 if RT_USING_SMART + help + Select DFS version for your system. + + DFS v1.0: + - Traditional DFS implementation + - Stable and well-tested + - Suitable for most embedded applications + - Lower memory overhead + + DFS v2.0: + - Enhanced for RT-Smart user-space applications + - Page cache support for better performance + - Memory-mapped file support (mmap) + - Required for RT-Smart mode + + Choose v1.0 for standard RT-Thread applications. + Choose v2.0 for RT-Smart with user-space processes. config RT_USING_DFS_V1 bool "DFS v1.0" depends on !RT_USING_SMART + help + DFS version 1.0 - traditional implementation. + + Stable version for standard RT-Thread applications without + user-space process support. config RT_USING_DFS_V2 bool "DFS v2.0" select RT_USING_DEVICE_OPS + help + DFS version 2.0 - enhanced for RT-Smart. + + Advanced features: + - Page cache for improved performance + - Memory-mapped files (mmap) + - Better integration with RT-Smart processes + - Enhanced POSIX compliance + + Required for RT-Smart mode. endchoice if RT_USING_DFS_V1 config DFS_FILESYSTEMS_MAX int "The maximal number of mounted file system" default 4 + help + Maximum number of file systems that can be mounted simultaneously. + + Default: 4 mount points + + Each mount point uses ~40-60 bytes. + Examples: + - "/" - root file system (FAT/ROM/RAM) + - "/sdcard" - SD card FAT + - "/dev" - device file system + - "/tmp" - temporary file system + + Increase if you need more mount points. + Decrease to save RAM on simple systems (minimum 1). config DFS_FILESYSTEM_TYPES_MAX int "The maximal number of file system type" default 4 + help + Maximum number of different file system types registered. + + Default: 4 types + + Common file system types: + - elm (FAT/exFAT) + - romfs (Read-Only Memory FS) + - ramfs (RAM FS) + - devfs (Device FS) + - nfs (Network FS) + - tmpfs (Temporary FS) + + Each type registration uses ~20-30 bytes. + Set based on number of file system types you plan to use. endif config RT_USING_DFS_ELMFAT bool "Enable elm-chan fatfs" default n help - FatFs is a generic FAT/exFAT file system module for small embedded systems. + Enable elm-chan's FAT file system implementation. + + FatFs is a generic FAT/exFAT file system module designed for + embedded systems with limited resources. + + Supported file systems: + - FAT12, FAT16, FAT32 + - exFAT (with RT_DFS_ELM_USE_EXFAT enabled) + + Features: + - Long File Name (LFN) support + - Unicode file names (UTF-8/UTF-16/UTF-32) + - Thread-safe operations + - Multiple volumes + + Use cases: + - SD card file storage + - USB flash drives + - Internal flash storage + - Data logging + + ROM overhead: ~15-25KB depending on features enabled. + + Enable for FAT-formatted storage devices. + Disable if not using FAT file systems. if RT_USING_DFS_ELMFAT menu "elm-chan's FatFs, Generic FAT Filesystem Module" @@ -161,6 +319,29 @@ endif config RT_USING_DFS_DEVFS bool "Using devfs for device objects" default y + help + Enable device file system (devfs) for accessing devices as files. + + Devfs provides /dev directory containing device nodes: + - /dev/uart1, /dev/uart2 - Serial ports + - /dev/spi0, /dev/i2c0 - Bus devices + - /dev/sd0, /dev/sd1 - Block devices + - /dev/rtc - Real-time clock + + Benefits: + - Unified device access via open/read/write + - POSIX-compliant device operations + - Better abstraction and portability + - Required for many device drivers + + Essential for: + - Device access from user applications + - RT-Smart user-space processes + - Shell device operations + + Minimal overhead (~1-2KB ROM, ~100 bytes RAM). + + Recommended to keep enabled for device access convenience. if RT_USING_DFS_V1 config RT_USING_DFS_ISO9660 @@ -172,6 +353,31 @@ endif menuconfig RT_USING_DFS_ROMFS bool "Enable ReadOnly file system on flash" default n + help + Enable ROM File System for read-only data stored in flash memory. + + ROMFS stores read-only files directly in program flash, useful for: + - Static web pages for web servers + - Configuration files + - Font files and graphics resources + - Help files and documentation + - Initial file system bootstrap + + Features: + - Very small footprint (~2-3KB) + - No RAM required for file data (executes from flash) + - Files embedded in firmware binary + - Fast access (no erase/write delays) + + Files included at compile time using romfs generator tool. + + Use cases: + - Web server static content + - Resource files for GUI applications + - Read-only configuration defaults + + Enable if you need embedded read-only files. + Disable to save ~2-3KB ROM if not needed. if RT_USING_DFS_ROMFS config RT_USING_DFS_ROMFS_USER_ROOT @@ -194,6 +400,32 @@ endif bool "Enable ReadOnly compressed file system on flash" default n # select PKG_USING_ZLIB + help + Enable Compressed ROM File System for compressed read-only data. + + CROMFS is similar to ROMFS but with compression, providing: + - Reduced flash usage (typically 30-70% compression) + - Read-only access to compressed files + - Automatic decompression on read + - Files embedded in firmware binary + + Trade-offs: + + Saves flash space (important for large resource files) + - Higher CPU usage for decompression + - Slower file access than ROMFS + - Requires ZLIB for decompression + + Best for: + - Large resource files (fonts, graphics, web content) + - Flash-constrained systems + - Files accessed infrequently + + Not recommended for: + - Frequently accessed files + - CPU-constrained systems + - Files already compressed (JPEG, PNG, MP3) + + Note: Requires ZLIB package for decompression support. if RT_USING_DFS_V1 config RT_USING_DFS_RAMFS @@ -206,12 +438,63 @@ endif bool "Enable TMP file system" default y if RT_USING_SMART default n + help + Enable temporary file system (tmpfs) in RAM. + + Tmpfs provides a RAM-based file system for temporary files: + - Files stored entirely in RAM + - Very fast read/write performance + - Files lost on reboot/power-off + - Dynamic size (grows/shrinks with usage) + + Typical mount point: /tmp + + Use cases: + - Temporary file storage during runtime + - Fast cache for processed data + - Inter-process communication via temp files + - Build/compile temporary files + - RT-Smart /tmp directory + + Memory usage: + - Grows with file content + - Files consume RAM directly + + Automatically enabled for RT-Smart (required for POSIX /tmp). + + Enable if you need fast temporary file storage. + Disable to save RAM if temporary files not needed. config RT_USING_DFS_MQUEUE bool "Enable MQUEUE file system" select RT_USING_DEV_BUS default y if RT_USING_SMART default n + help + Enable POSIX message queue file system. + + Provides POSIX message queues as files in /dev/mqueue: + - mq_open(), mq_send(), mq_receive() + - Named message queues + - File descriptor based operations + - Process-safe IPC mechanism + + Features: + - POSIX-compliant message queue API + - Multiple processes can communicate + - Priority-based message delivery + - Blocking and non-blocking modes + + Use cases: + - Inter-process communication in RT-Smart + - POSIX application porting + - Priority message passing + + Required for RT-Smart POSIX message queues. + Automatically enabled in RT-Smart mode. + + Enable for POSIX message queue support. + Disable if not using POSIX IPC (~2-3KB ROM savings). if RT_USING_DFS_V1 config RT_USING_DFS_NFS diff --git a/components/finsh/Kconfig b/components/finsh/Kconfig index 67a50a28d7e..e8b507868da 100644 --- a/components/finsh/Kconfig +++ b/components/finsh/Kconfig @@ -3,95 +3,324 @@ menuconfig RT_USING_MSH default n if RT_USING_NANO default y select RT_USING_SEMAPHORE + help + MSH (Module SHell) is RT-Thread's command-line interface (CLI) shell. + + Provides interactive command execution for: + - System debugging and monitoring + - Runtime configuration and testing + - File system operations + - Network diagnostics + - Custom application commands + + Features: + - Tab completion for commands and file paths + - Command history with arrow keys + - Built-in commands (ls, ps, free, etc.) + - Custom command registration via MSH_CMD_EXPORT() + - Authentication support for secure access + + Typical use cases: + - Development and debugging + - Production diagnostics + - Interactive testing + - System administration + + Note: Disable for headless embedded systems to save ~8-16KB ROM. + Automatically disabled in RT_USING_NANO configuration. if RT_USING_MSH config RT_USING_FINSH bool default y + help + Internal configuration for finsh shell support. + Automatically enabled when RT_USING_MSH is selected. + Do not modify directly. config FINSH_USING_MSH bool default y + help + Use MSH (Module SHell) mode instead of traditional C-expression shell. + MSH provides a more familiar POSIX-like command interface. + Automatically enabled when RT_USING_MSH is selected. + Do not modify directly. config FINSH_THREAD_NAME string "The msh thread name" default "tshell" + help + Name of the MSH shell thread visible in thread list. + + Default: "tshell" + + Change this to avoid name conflicts or for identification purposes. + Thread name length limited by RT_NAME_MAX (default 8 chars). config FINSH_THREAD_PRIORITY int "The priority level value of thread" default 20 + help + Priority of MSH shell thread (lower number = higher priority). + + Default: 20 (low priority) + + Recommendations: + - Keep at low priority (15-25) to avoid blocking real-time tasks + - Increase priority if shell responsiveness is critical + - Must be less than RT_THREAD_PRIORITY_MAX + + Note: Shell executes user commands which may have high CPU usage. config FINSH_THREAD_STACK_SIZE int "The stack size for thread" default 4096 + help + Stack size in bytes for the MSH shell thread. + + Default: 4096 bytes (4KB) + + Increase if: + - Shell commands use deep recursion or large local variables + - Running complex scripts + - Stack overflow errors occur + + Decrease to save RAM on memory-constrained systems (minimum ~2KB). + + Note: Each command execution may require additional stack space. config FINSH_USING_HISTORY bool "Enable command history feature" default y + help + Enable command history buffer with up/down arrow key navigation. + + Features: + - Recall previous commands with up arrow + - Navigate forward with down arrow + - Configurable number of history lines + + Memory cost: ~80 bytes × FINSH_HISTORY_LINES + + Enable for improved user experience during interactive sessions. + Disable to save minimal RAM (~400 bytes with default 5 lines). if FINSH_USING_HISTORY config FINSH_HISTORY_LINES int "The command history line number" default 5 + help + Number of command lines stored in history buffer. + + Default: 5 lines + + Each line uses ~80 bytes (FINSH_CMD_SIZE). + Total memory: FINSH_HISTORY_LINES × FINSH_CMD_SIZE + + Increase for longer history (up to ~10-20 lines reasonable). + Decrease to save RAM on constrained systems. endif config FINSH_USING_WORD_OPERATION bool "Enable word-based cursor operations" default n help - Enable Ctrl+Backspace to delete words and Ctrl+Arrow to move cursor by word + Enable Ctrl+Backspace to delete words and Ctrl+Arrow to move cursor by word. + + Provides enhanced editing with word-boundary operations: + - Ctrl+Backspace: Delete word before cursor + - Ctrl+Left/Right Arrow: Move cursor by word + + Improves command-line editing efficiency for long commands. + Minimal memory overhead (~100 bytes). config FINSH_USING_FUNC_EXT bool "Enable function extension home end ins del" default n help - Enable function extension home end ins del. + Enable extended function keys for cursor movement and editing. + + Supported keys: + - Home: Move cursor to start of line + - End: Move cursor to end of line + - Insert: Toggle insert/overwrite mode + - Delete: Delete character at cursor + + Provides familiar editing experience from standard terminals. + Minimal memory overhead (~100 bytes). config FINSH_USING_SYMTAB bool "Using symbol table for commands" default y + help + Use symbol table to store and lookup shell commands. + + When enabled: + - Commands registered via MSH_CMD_EXPORT() are stored in symbol table + - Supports command name lookup and auto-completion + - Enables help command to list all available commands + + Required for most shell functionality. Only disable for minimal + configurations where commands are hard-coded. + + Disabling saves ~1-2KB depending on number of commands. config FINSH_CMD_SIZE int "The command line size for shell" default 80 + help + Maximum length of a single command line including arguments. + + Default: 80 characters + + Increase if you need to: + - Enter long file paths + - Pass many arguments to commands + - Use complex command pipelines + + Decrease to save RAM (minimum ~40 chars recommended). + + Memory impact: FINSH_CMD_SIZE bytes per command buffer + + FINSH_CMD_SIZE × FINSH_HISTORY_LINES for history config MSH_USING_BUILT_IN_COMMANDS bool "Enable built-in commands, such as list_thread" default y + help + Include standard built-in shell commands. + + Built-in commands include: + - System: help, version, reboot + - Threads: list_thread (ps), list_sem, list_mutex, list_timer + - Memory: free, memcheck, memtrace + - File system: ls, cd, pwd, cat, rm, mkdir, etc. + + Disabling removes these commands but allows custom implementations. + Saves ~4-8KB ROM depending on enabled features. + + Recommended to keep enabled unless implementing custom command set. config FINSH_USING_DESCRIPTION bool "Keeping description in symbol table" default y + help + Store command descriptions in symbol table for help text. + + When enabled: + - 'help' command shows detailed description for each command + - MSH_CMD_EXPORT() macro can include description parameter + + Cost: ~20-50 bytes per command for description strings + + Disable to save ROM if help text not needed in production. + Keep enabled during development for better usability. config FINSH_ECHO_DISABLE_DEFAULT bool "Disable the echo mode in default" default n + help + Disable character echo by default when shell starts. + + When disabled (echo off): + - Typed characters not displayed (useful for password input) + - Can be toggled at runtime with 'echo' command + + Normal configuration: Keep disabled (echo enabled by default) + + Enable this option to start with echo off, useful for: + - Security-sensitive applications + - Non-interactive serial protocols + - Automated test scripts config FINSH_USING_AUTH bool "shell support authentication" default n + help + Enable password authentication for shell access. + + Security features: + - Password prompt on shell connection + - Configurable password and length requirements + - Locks shell until correct password entered + + Use cases: + - Production systems with console access + - Security-critical applications + - Preventing unauthorized access via UART/Telnet + + Note: Password stored in plain text in firmware. + For strong security, combine with encrypted communication. if FINSH_USING_AUTH config FINSH_DEFAULT_PASSWORD string "The default password for shell authentication" default "rtthread" + help + Default password required to access the shell. + + Default: "rtthread" + + Security recommendations: + - Change from default in production systems + - Use strong passwords (mix of letters, numbers, symbols) + - Length between FINSH_PASSWORD_MIN and FINSH_PASSWORD_MAX + + Note: Password stored as plain text in firmware binary. + Anyone with firmware access can extract the password. config FINSH_PASSWORD_MIN int "The password min length" default 6 + help + Minimum password length in characters. + + Default: 6 characters + + Enforces minimum password strength. Increase for better security + (recommended: 8+ characters for production). config FINSH_PASSWORD_MAX int "The password max length" default RT_NAME_MAX + help + Maximum password length in characters. + + Default: RT_NAME_MAX (typically 8) + + Limited by password buffer size. Increase RT_NAME_MAX if you + need longer passwords, but consider memory constraints. endif config FINSH_ARG_MAX int "The number of arguments for a shell command" default 10 + help + Maximum number of arguments (including command name) that can be + passed to a single shell command. + + Default: 10 arguments + + Increase if you have commands that need many parameters. + Each argument slot uses ~4 bytes (pointer size). + + Total memory: FINSH_ARG_MAX × sizeof(char*) config FINSH_USING_OPTION_COMPLETION bool "command option completion enable" default y + help + Enable tab completion for command options and arguments. + + Features: + - Press Tab to auto-complete command names + - Complete file paths when using file system commands + - Show list of matches if multiple options available + + Greatly improves usability and reduces typing errors. + Minimal memory overhead (~200 bytes). + + Recommended to keep enabled for interactive shells. endif From e6166a17e9f27b40f6466289f9d44e63665cc1f1 Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Mon, 17 Nov 2025 08:51:35 +0000 Subject: [PATCH 4/6] Add comprehensive help for lwp and net/sal Kconfig files Co-authored-by: Rbb666 <64397326+Rbb666@users.noreply.github.com> --- components/lwp/Kconfig | 293 ++++++++++++++++++++++++++++++++++++- components/net/sal/Kconfig | 151 ++++++++++++++++++- 2 files changed, 438 insertions(+), 6 deletions(-) diff --git a/components/lwp/Kconfig b/components/lwp/Kconfig index 4a83405d8a0..62848a5d806 100644 --- a/components/lwp/Kconfig +++ b/components/lwp/Kconfig @@ -3,12 +3,61 @@ menuconfig RT_USING_LWP depends on RT_USING_SMART default y help - The lwP is a light weight process running in user mode. + LWP (Light Weight Process) provides user-space process support in RT-Smart mode. + + Features: + - User-space and kernel-space separation + - Process isolation with MMU/MPU + - POSIX process APIs (fork, exec, waitpid, etc.) + - Inter-process communication (IPC) + - Signal handling + - Dynamic linking and loading (LDSO) + + Benefits: + - Memory protection between processes + - Fault isolation (process crash doesn't affect kernel) + - Multi-user application support + - Better security and stability + + Requirements: + - RT_USING_SMART must be enabled + - CPU with MMU or MPU support + - DFS v2.0 for file system access + + Use cases: + - Running untrusted user applications + - Mixed-criticality systems + - Applications requiring process isolation + - POSIX application porting + + Note: LWP is the foundation of RT-Smart user-space support. + Required for running user-space applications. if RT_USING_LWP menuconfig LWP_DEBUG bool "Enable debugging features of LwP" default n + help + Enable debugging and tracing features for LWP processes. + + Debug features: + - Process state transitions logging + - Memory allocation tracking + - IPC operation tracing + - Signal delivery monitoring + + Useful for: + - Development and debugging + - Troubleshooting process issues + - Performance analysis + - System behavior understanding + + Overhead: + - Increased log output + - Slightly slower process operations + - Additional ROM for debug strings (~2-4KB) + + Enable during development, disable in production for performance. if LWP_DEBUG config LWP_DEBUG_INIT @@ -16,56 +65,231 @@ if RT_USING_LWP bool "Enable debug mode of init process" depends on LWP_USING_RUNTIME default y + help + Enable detailed debugging for init process (PID 1). + + Traces init process activities: + - Boot script execution + - Child process spawning + - Signal handling + - Shutdown sequence + + Useful for debugging system startup and shutdown issues. + Requires LWP_USING_RUNTIME enabled. endif config LWP_USING_RUNTIME bool "Using processes runtime environment (INIT process)" default y help - Runtime environment provide by init process including boot scripts, - poweroff, shutdown, reboot, etc. + Enable init process and runtime environment for user-space. + + Provides Linux-like init system (PID 1) that: + - Starts as first user process + - Executes boot scripts (/etc/rc.local, /etc/init.d/*) + - Manages system lifecycle + - Handles orphaned processes + - Provides system commands (poweroff, reboot, shutdown) + + Features: + - Boot script support for auto-starting applications + - Graceful shutdown handling + - Process reaping (zombie cleanup) + - System service management + + Required for: + - Complete RT-Smart user-space environment + - Automatic application startup + - System lifecycle management + + Disable only for minimal systems without init process. config RT_LWP_MAX_NR int "The max number of light-weight process" default 30 + help + Maximum number of processes that can run simultaneously. + + Default: 30 processes + + Each process uses: + - ~200-400 bytes for process control block + - Separate page tables (MMU systems) + - Individual memory spaces + + Total memory: RT_LWP_MAX_NR × ~300 bytes (minimum) + + Increase for: + - Systems running many concurrent applications + - Multi-user environments + + Decrease to save memory on constrained systems. + Minimum recommended: 8-10 processes. config LWP_TASK_STACK_SIZE int "The lwp thread kernel stack size" default 16384 + help + Kernel stack size for each LWP thread in bytes. + + Default: 16384 bytes (16KB) + + This is the kernel-mode stack used when process enters kernel via: + - System calls + - Exception handling + - Interrupt processing + + Stack usage depends on: + - System call complexity + - Nested interrupt depth + - Kernel function call chains + + Increase if: + - Kernel stack overflow errors + - Deep system call nesting + - Complex device drivers + + Decrease to save RAM (minimum ~8KB for basic operations). + Each LWP thread requires this much kernel stack. config RT_CH_MSG_MAX_NR int "The maximum number of channel messages" default 1024 + help + Maximum number of messages in channel IPC message pool. + + Default: 1024 messages + + Channels provide RT-Thread's native IPC mechanism for LWP: + - Higher performance than POSIX IPC + - Direct memory-mapped communication + - Zero-copy message passing + + Each message slot uses ~32-64 bytes depending on message size. + + Increase for: + - High-frequency IPC between processes + - Many concurrent channel communications + + Decrease to save memory if channel IPC not heavily used. config LWP_TID_MAX_NR int "The maximum number of lwp thread id" default 64 + help + Maximum number of thread IDs available for LWP threads. + + Default: 64 thread IDs + + Each process can create multiple threads. This limits total + thread IDs across all processes. + + Typical usage: + - Single-threaded processes: 1 TID each + - Multi-threaded processes: N TIDs per process + + Total threads = sum of threads in all processes + + Increase for: + - Applications creating many threads + - Many multi-threaded processes + + Decrease if applications mostly single-threaded. config LWP_ENABLE_ASID bool "The switch of ASID feature" depends on ARCH_ARM_CORTEX_A default y + help + Enable Address Space ID (ASID) for Cortex-A processors. + + ASID provides hardware-based process identification: + - Tags TLB entries with process ID + - Avoids TLB flush on context switch + - Significantly faster process switching + + Performance impact: + - 50-70% faster context switch between processes + - Better TLB hit rate + - Reduced MMU overhead + + Automatically enabled for Cortex-A (recommended). + Only disable for debugging TLB-related issues. + + Note: Requires CPU with ASID support (ARMv7-A and above). if ARCH_MM_MMU config RT_LWP_SHM_MAX_NR int "The maximum number of shared memory" default 64 + help + Maximum number of shared memory segments for inter-process communication. + + Default: 64 segments + + Shared memory provides: + - Fastest IPC method (direct memory access) + - POSIX shm_open()/shm_unlink() APIs + - mmap() for memory-mapped sharing + + Each segment descriptor uses ~40-60 bytes. + + Increase for: + - Applications using extensive shared memory + - Multiple processes sharing data + - High-performance IPC requirements + + Decrease to save memory if shared memory rarely used. config LWP_USING_MPROTECT bool default n help - ARCH has the support of mprotect + Architecture has mprotect() support for memory protection. + + mprotect() allows changing memory region permissions: + - Read, write, execute permissions + - Guard pages for stack overflow detection + - Memory region isolation + + Automatically enabled by architecture support. + User does not configure directly. endif if ARCH_MM_MPU config RT_LWP_MPU_MAX_NR int "The maximum number of mpu region" default 2 + help + Maximum number of MPU regions per process. + + Default: 2 regions per process + + MPU provides memory protection without full MMU: + - Limited number of protection regions + - Simpler than MMU but less flexible + + Regions typically used for: + - Code region (read-execute) + - Data region (read-write) + - Stack guard region + + Limited by hardware MPU region count. + Check your CPU MPU capabilities. config RT_LWP_USING_SHM bool "Enable shared memory" default y + help + Enable shared memory support for MPU-based systems. + + Provides shared memory IPC even without MMU: + - Processes can share memory regions + - Requires careful MPU configuration + - More limited than MMU-based sharing + + Enable for IPC in MPU-only systems (Cortex-M with MPU). + Disable if not using shared memory to save ~1-2KB ROM. endif menuconfig RT_USING_LDSO @@ -73,15 +297,76 @@ if RT_USING_LWP depends on RT_USING_DFS_V2 select RT_USING_PAGECACHE default y + help + Enable dynamic linker/loader for shared libraries and executables. + + LDSO (LD.SO - Link editor, Shared Object) provides: + - Dynamic linking of shared libraries (.so files) + - Runtime loading of executables (ELF files) + - Symbol resolution and relocation + - Lazy binding for faster startup + + Features: + - Load executables from file system + - Share library code between processes (saves RAM) + - Update libraries without recompiling applications + - Standard ELF binary support + + Requirements: + - DFS v2.0 for file system access + - Page cache for performance + + Use cases: + - Running standard Linux binaries + - Modular application architecture + - Shared library usage + - Dynamic plugin loading + + Essential for RT-Smart user-space applications. + ROM overhead: ~10-15KB for LDSO implementation. if RT_USING_LDSO config ELF_DEBUG_ENABLE bool "Enable ldso debug" default n + help + Enable debugging output for dynamic linker/loader operations. + + Debug information includes: + - Library loading and unloading + - Symbol resolution process + - Relocation details + - Memory mapping operations + + Useful for: + - Troubleshooting loading failures + - Understanding dependency chains + - Debugging symbol resolution issues + + Disable in production for reduced log output and smaller ROM. config ELF_LOAD_RANDOMIZE bool "Enable random load address" default n + help + Enable ASLR (Address Space Layout Randomization) for loaded binaries. + + Security feature that randomizes: + - Executable base address + - Shared library load addresses + - Stack and heap positions + + Benefits: + - Harder to exploit buffer overflows + - Prevents return-to-libc attacks + - Increases security against memory exploits + + Overhead: + - Slightly slower loading + - More complex debugging (non-deterministic addresses) + + Enable for security-critical applications. + Disable for easier debugging or deterministic behavior. endif rsource "terminal/Kconfig" diff --git a/components/net/sal/Kconfig b/components/net/sal/Kconfig index 57d9e7215ef..b4edbebcd45 100644 --- a/components/net/sal/Kconfig +++ b/components/net/sal/Kconfig @@ -2,6 +2,35 @@ menuconfig RT_USING_SAL bool "SAL: socket abstraction layer" select RT_USING_NETDEV default n + help + SAL (Socket Abstraction Layer) provides unified BSD socket API for multiple network stacks. + + Features: + - Standard BSD socket API (socket, bind, connect, send, recv, etc.) + - Support multiple protocol stacks simultaneously + - Network stack independence for applications + - Automatic routing between different network interfaces + + Supported protocol stacks: + - LwIP (full TCP/IP stack) + - AT commands (for cellular/WiFi modules) + - TLS/SSL (via MbedTLS) + - Custom protocol stacks + + Benefits: + - Write once, run on any supported network stack + - Easy switching between WiFi, Ethernet, cellular + - Multiple network connections concurrently + - Standard POSIX socket compatibility + + Use cases: + - Applications requiring network connectivity + - Multi-interface systems (WiFi + Ethernet) + - IoT devices with multiple network options + - Network stack abstraction + + Enable for any application using network sockets. + Overhead: ~4-6KB ROM, ~1KB RAM + socket buffers. if RT_USING_SAL @@ -15,19 +44,107 @@ if RT_USING_SAL config SOCKET_TABLE_STEP_LEN int "Configure socket table step length" default 4 + help + Growth step size for dynamic socket table expansion. + + Default: 4 sockets + + When socket table is full, it grows by this many entries: + - Initial size: SAL_SOCKETS_NUM + - Grows by: SOCKET_TABLE_STEP_LEN when full + + Smaller values: + + Less wasted memory + - More frequent reallocations + + Larger values: + + Fewer reallocations + - More unused memory + + Recommended: 4-8 for most applications. menu "Docking with protocol stacks" config SAL_USING_LWIP bool "Docking with lwIP stack" default n + help + Integrate LwIP (Lightweight IP) TCP/IP stack with SAL. + + LwIP provides full-featured TCP/IP protocol stack: + - TCP, UDP, ICMP, IGMP protocols + - IPv4 and IPv6 support + - DHCP client and server + - DNS resolution + - Raw socket support + + When enabled, applications can use BSD sockets backed by LwIP. + + Required for: + - Ethernet networking + - WiFi with full TCP/IP + - Complex network protocols + + Enable if using LwIP as network stack. config SAL_USING_AT bool "Docking with AT commands stack" default n + help + Integrate AT command-based network modules with SAL. + + AT commands provide network connectivity through: + - Cellular modules (2G/3G/4G/5G/NB-IoT) + - WiFi modules (ESP8266, ESP32, etc.) + - Bluetooth modules + + Features: + - BSD socket API over AT commands + - Transparent to applications + - Supports multiple AT devices + - Hardware offload (module handles TCP/IP) + + Advantages: + - Lower MCU resource usage + - Faster time-to-market + - Leverages module's TCP/IP stack + + Use cases: + - IoT devices with cellular connectivity + - Low-power WiFi applications + - Systems with network co-processors + + Enable for AT command-based network modules. config SAL_USING_TLS bool "Docking with MbedTLS protocol" default n + help + Integrate MbedTLS for SSL/TLS secure communication. + + MbedTLS provides: + - SSL/TLS encryption (TLS 1.0-1.3) + - X.509 certificate handling + - Secure sockets (HTTPS, MQTTS, etc.) + - Cryptographic primitives + + Features: + - Transparent SSL/TLS layer over SAL + - Certificate verification + - Multiple cipher suites + - Session resumption + + Use cases: + - HTTPS web clients/servers + - Secure MQTT (MQTTS) + - Encrypted data transmission + - Cloud service connections (AWS, Azure, etc.) + + Requirements: + - MbedTLS package + - Network stack (LwIP or AT) + - Sufficient RAM for TLS buffers (~20-40KB) + + Enable for secure network communications. endmenu config SAL_USING_POSIX @@ -35,12 +152,42 @@ if RT_USING_SAL depends on DFS_USING_POSIX default y help - Enable BSD socket operated by file system API - Let BSD socket operated by file system API, such as read/write and involveed in select/poll POSIX APIs. + Enable BSD socket operations via file system API. + + When enabled, sockets can be used like files: + - open/close for socket creation/destruction + - read/write for send/receive + - select/poll for I/O multiplexing + - File descriptor sharing with regular files + + Benefits: + - Unified I/O model (files + sockets) + - Compatible with POSIX I/O functions + - Works with select/poll + - Easier application porting from Linux + + Automatically enabled when DFS with POSIX is available. + Required for RT-Smart user-space socket access. config SAL_SOCKETS_NUM int "the maximum number of sockets" depends on !SAL_USING_POSIX default 16 + help + Maximum number of sockets that can be created simultaneously. + + Default: 16 sockets + + Each socket uses: + - ~100-200 bytes for socket structure + - Send/receive buffers (protocol stack dependent) + + Increase for: + - Server applications with many concurrent connections + - Applications opening multiple sockets + + Decrease to save memory on constrained systems. + + Note: Not used when SAL_USING_POSIX enabled (uses DFS_FD_MAX instead). endif From 560deecceca8141319a2975c4181909d02d3a84b Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Mon, 17 Nov 2025 10:04:41 +0000 Subject: [PATCH 5/6] Add comprehensive help for POSIX layer Kconfig files Co-authored-by: Rbb666 <64397326+Rbb666@users.noreply.github.com> --- components/libc/posix/Kconfig | 417 ++++++++++++++++++++++++++++++ components/libc/posix/ipc/Kconfig | 105 ++++++++ 2 files changed, 522 insertions(+) diff --git a/components/libc/posix/Kconfig b/components/libc/posix/Kconfig index 8a4a3843cbd..cae76f7af46 100644 --- a/components/libc/posix/Kconfig +++ b/components/libc/posix/Kconfig @@ -5,51 +5,223 @@ config RT_USING_POSIX_FS select RT_USING_DFS select DFS_USING_POSIX default n + help + Enable POSIX-compliant file system and I/O APIs. + + Provides standard POSIX file operations: + - File I/O: open(), read(), write(), close(), lseek() + - Directory: opendir(), readdir(), closedir() + - File control: fcntl(), ioctl() + - File status: stat(), fstat(), access() + - File operations: unlink(), rename(), chmod() + + Benefits: + - Source code compatibility with Linux/Unix + - Easier porting of existing applications + - Standard API familiar to developers + - Better integration with third-party libraries + + Requirements: + - RT_USING_DFS must be enabled + - File system support (FAT, ROM-FS, etc.) + + Enable for applications requiring POSIX file I/O compatibility. + Essential for porting Linux/Unix applications to RT-Thread. if RT_USING_POSIX_FS config RT_USING_POSIX_DEVIO bool "Enable devices as file descriptors" select RT_USING_DFS_DEVFS default n + help + Access devices through file descriptors like regular files. + + Allows opening devices in /dev using standard file operations: + - fd = open("/dev/uart1", O_RDWR) + - read(fd, buffer, size) / write(fd, buffer, size) + - ioctl(fd, cmd, arg) for device control + - close(fd) + + Benefits: + - Unified I/O model for files and devices + - Compatible with select/poll for device I/O + - Easier application design + + Automatically enables devfs (/dev filesystem). + + Enable for POSIX-style device access. + Required for RT_USING_POSIX_STDIO. config RT_USING_POSIX_STDIO bool "Enable standard I/O devices, e.g. STDOUT_FILENO" select RT_USING_POSIX_DEVIO default n + help + Enable standard POSIX I/O file descriptors. + + Provides standard file descriptors: + - STDIN_FILENO (0): Standard input + - STDOUT_FILENO (1): Standard output + - STDERR_FILENO (2): Standard error + + Allows using printf, scanf, fprintf with standard streams. + + Benefits: + - Compatible with standard C library I/O + - Easier debugging with stderr + - Standard input/output redirection + + Requires RT_USING_POSIX_DEVIO (device file descriptors). + + Enable for applications using stdin/stdout/stderr. config RT_USING_POSIX_POLL bool "Enable I/O Multiplexing poll() " default y if RT_USING_SMART default n + help + Enable POSIX poll() for I/O multiplexing. + + poll() monitors multiple file descriptors for I/O events: + - Wait for data available on sockets/files + - Detect when writing won't block + - Error and hangup conditions + - Timeout support + + Use cases: + - Network servers handling multiple connections + - Monitoring multiple devices simultaneously + - Event-driven I/O programming + + More portable than select() (no FD_SETSIZE limit). + + Automatically enabled in RT-Smart mode. + Enable for I/O multiplexing applications. config RT_USING_POSIX_SELECT bool "Enable I/O Multiplexing select() " select RT_USING_POSIX_POLL default y if RT_USING_SMART default n + help + Enable POSIX select() for I/O multiplexing. + + select() monitors file descriptors for I/O readiness: + - Check multiple sockets/files for data + - Wait with timeout + - Detect errors and exceptions + + Compatible with BSD sockets and standard POSIX API. + + Advantages over poll(): + + More widely known API + + Compatible with older code + + Disadvantages: + - Limited to FD_SETSIZE file descriptors (typically 1024) + - Less efficient for large numbers of FDs + + Automatically enables poll() (implementation uses poll). + + Enable for applications using select() API. config RT_USING_POSIX_EVENTFD bool "Enable I/O event eventfd " select RT_USING_POSIX_POLL default y if RT_USING_SMART default n + help + Enable Linux-style eventfd for event notification. + + eventfd provides a file descriptor for event notification: + - Create event object: eventfd(initval, flags) + - Signal event: write(efd, &value, 8) + - Wait for event: read(efd, &value, 8) + - Integrates with poll/select/epoll + + Features: + - Semaphore-style counting (EFD_SEMAPHORE) + - Non-blocking mode (EFD_NONBLOCK) + - Cloexec flag support (EFD_CLOEXEC) + + Use cases: + - Thread/process notification + - Event-driven architectures + - Integrating with poll/epoll event loops + + Lighter weight than pipes for simple notifications. + + Enable for Linux-compatible event notification. if RT_USING_SMART config RT_USING_POSIX_EPOLL bool "Enable I/O Multiplexing epoll " select RT_USING_POSIX_POLL default y + help + Enable Linux epoll for scalable I/O multiplexing. + + epoll is designed for handling large numbers of file descriptors: + - No FD_SETSIZE limit (unlike select) + - O(1) performance (vs O(n) for select/poll) + - Edge-triggered and level-triggered modes + - One-shot mode support + + API: + - epoll_create(): Create epoll instance + - epoll_ctl(): Add/modify/remove file descriptors + - epoll_wait(): Wait for I/O events + + Benefits: + - Scales to thousands of connections + - Better performance for large FD sets + - More flexible event notification + + Use cases: + - High-performance network servers + - Event-driven applications + - Systems with many concurrent I/O operations + + Required for RT-Smart. Recommended for server applications. config RT_USING_POSIX_SIGNALFD bool "Enable Signalfd " select RT_USING_POSIX_POLL default y + help + Enable signalfd for receiving signals via file descriptor. + + signalfd converts signal delivery into file I/O: + - Create: signalfd(fd, &mask, flags) + - Read signal info: read(sfd, &siginfo, sizeof(siginfo)) + - Integrate with poll/select/epoll + + Benefits: + - Unified event handling (signals + I/O) + - Avoid signal handler race conditions + - Easier signal processing in event loops + + Use cases: + - Event-driven applications handling signals + - Integrating signals with epoll event loops + - Safe signal handling without signal handlers + + Required for RT-Smart signal handling integration. if RT_USING_POSIX_SIGNALFD config RT_SIGNALFD_MAX_NUM int "signaled The maximum number of concurrent firing signals" range 1 20 default 10 + help + Maximum number of signals that can be queued in signalfd. + + Default: 10 signals + + Limits memory usage for signal buffering. + Increase if applications generate many concurrent signals. + + Each signal uses ~128 bytes for siginfo structure. endif endif @@ -57,62 +229,307 @@ if RT_USING_POSIX_FS bool "Enable I/O timerfd " default y if RT_USING_SMART default n + help + Enable timerfd for timer notification via file descriptor. + + timerfd provides timer expiration as file I/O events: + - Create: timerfd_create(clockid, flags) + - Set timer: timerfd_settime(fd, flags, &spec, NULL) + - Read expiration: read(tfd, &expirations, 8) + - Integrate with poll/select/epoll + + Features: + - One-shot and periodic timers + - Absolute and relative timeouts + - Can be monitored with epoll + + Benefits: + - Unified event handling (timers + I/O) + - Multiple independent timers + - Compatible with event-driven design + + Use cases: + - Event loop timers + - Timeout handling in servers + - Periodic tasks in event-driven apps + + Enable for file-descriptor-based timer notification. config RT_USING_POSIX_SOCKET bool "Enable BSD Socket I/O " select RT_USING_POSIX_SELECT select RT_USING_SAL default n + help + Enable POSIX BSD socket API for network programming. + + Provides standard socket APIs: + - socket(), bind(), listen(), accept(), connect() + - send(), recv(), sendto(), recvfrom() + - setsockopt(), getsockopt() + - getaddrinfo(), gethostbyname() + + Requires SAL (Socket Abstraction Layer) for network stack. + + Enables network application development with standard API. + See Network -> SAL configuration for protocol stack selection. config RT_USING_POSIX_TERMIOS bool "Enable Terminal I/O " select RT_USING_POSIX_STDIO default n + help + Enable POSIX terminal I/O control (termios). + + Provides terminal control APIs: + - tcgetattr(), tcsetattr(): Get/set terminal attributes + - cfsetispeed(), cfsetospeed(): Set baud rates + - tcdrain(), tcflush(), tcflow(): Terminal flow control + + Features: + - Raw and canonical mode control + - Baud rate configuration + - Character size and parity settings + - Flow control (hardware/software) + + Use cases: + - Serial terminal configuration + - Raw mode for binary protocols + - Terminal emulation applications + + Requires RT_USING_POSIX_STDIO (standard I/O). + + Enable for POSIX terminal control compatibility. config RT_USING_POSIX_AIO bool "Enable Asynchronous I/O " default n + help + Enable POSIX Asynchronous I/O APIs. + + Provides async I/O operations: + - aio_read(), aio_write(): Asynchronous read/write + - aio_fsync(): Asynchronous file sync + - aio_suspend(): Wait for async operations + - aio_error(), aio_return(): Check status + + Benefits: + - Non-blocking I/O operations + - Better CPU utilization + - Overlap I/O with computation + + Use cases: + - High-performance file I/O + - Database systems + - Large file operations + + Note: Requires careful memory management. + Overhead: ~200-400 bytes per async operation. config RT_USING_POSIX_MMAN bool "Enable Memory-Mapped I/O " default n + help + Enable POSIX memory mapping (mmap). + + Provides memory mapping APIs: + - mmap(): Map files or devices into memory + - munmap(): Unmap memory regions + - mprotect(): Set memory protection + - msync(): Synchronize memory with file + + Benefits: + - Efficient file I/O (no read/write calls) + - Shared memory between processes + - Large file handling + + Use cases: + - Large file access + - Shared memory IPC + - Memory-mapped device registers + + Requires MMU or MPU support. + Available in RT-Smart with proper hardware support. endif config RT_USING_POSIX_DELAY select RT_USING_KTIME bool "Enable delay APIs, sleep()/usleep()/msleep() etc" default n + help + Enable POSIX delay/sleep functions. + + Provides standard delay APIs: + - sleep(seconds): Sleep for seconds + - usleep(microseconds): Sleep for microseconds + - msleep(milliseconds): Sleep for milliseconds + - nanosleep(timespec): High-precision sleep + + Based on RT-Thread's kernel time (ktime) for accuracy. + + Benefits: + - Standard POSIX API for delays + - Better code portability + - Microsecond precision + + Enable for POSIX-compatible delay functions. + Automatically selected by RT_USING_POSIX_CLOCK. config RT_USING_POSIX_CLOCK bool "Enable clock/time APIs, clock_gettime()/clock_settime() etc" select RT_USING_POSIX_DELAY default n + help + Enable POSIX clock and time APIs. + + Provides standard time functions: + - clock_gettime(): Get clock time + - clock_settime(): Set clock time + - clock_getres(): Get clock resolution + + Supported clocks: + - CLOCK_REALTIME: System-wide real-time clock + - CLOCK_MONOTONIC: Monotonic time (doesn't jump) + - CLOCK_PROCESS_CPUTIME_ID: Process CPU time + - CLOCK_THREAD_CPUTIME_ID: Thread CPU time + + Benefits: + - Standard time API + - High-resolution timestamps + - Monotonic time for intervals + + Required by pthreads and POSIX timers. + Enable for POSIX time functionality. config RT_USING_POSIX_TIMER select RT_USING_KTIME select RT_USING_RESOURCE_ID bool "Enable timer APIs, timer_create()/timer_gettime() etc" default n + help + Enable POSIX interval timers. + + Provides POSIX timer APIs: + - timer_create(): Create a timer + - timer_settime(): Arm/disarm timer + - timer_gettime(): Get timer status + - timer_delete(): Delete timer + + Features: + - Per-process timers + - One-shot and periodic modes + - Signal-based or thread-based notification + - Absolute and relative timeouts + + Use cases: + - Periodic task execution + - Timeout handling + - Watchdog timers + - Scheduled events + + Requires KTIME and resource ID management. + Enable for POSIX timer functionality. config RT_USING_PTHREADS bool "Enable pthreads APIs" select RT_USING_POSIX_CLOCK default n + help + Enable POSIX threads (pthreads) API. + + Provides standard threading APIs: + - Thread management: pthread_create(), pthread_join(), pthread_exit() + - Mutex: pthread_mutex_lock(), pthread_mutex_unlock() + - Condition variables: pthread_cond_wait(), pthread_cond_signal() + - Read-write locks: pthread_rwlock_*() + - Barriers: pthread_barrier_*() + - Thread-specific data: pthread_key_create(), pthread_setspecific() + + Benefits: + - Standard threading API for portability + - Compatible with Linux/Unix applications + - Rich synchronization primitives + + Implementation: + - Maps to RT-Thread native threads + - Full POSIX thread attribute support + - Detached and joinable threads + + Essential for porting multi-threaded POSIX applications. + + Configure maximum threads with PTHREAD_NUM_MAX. if RT_USING_PTHREADS config PTHREAD_NUM_MAX int "Maximum number of pthreads" default 8 + help + Maximum number of POSIX threads (pthreads) that can exist simultaneously. + + Default: 8 threads + + Each pthread uses: + - Thread control block (~100-200 bytes) + - Stack (configured per thread) + - pthread-specific data storage + + Increase for applications creating many threads. + Decrease to save memory on constrained systems. + + Note: This is separate from RT-Thread native thread limit. endif config RT_USING_MODULE bool "Enable dynamic module APIs, dlopen()/dlsym()/dlclose() etc" default n + help + Enable POSIX dynamic module loading (dlopen/dlsym). + + Provides dynamic library APIs: + - dlopen(): Load shared library + - dlsym(): Get symbol address from library + - dlclose(): Unload library + - dlerror(): Get error string + + Features: + - Runtime loading of .so files + - Symbol resolution + - Lazy and immediate binding + - RTLD_GLOBAL and RTLD_LOCAL scope + + Use cases: + - Plugin architectures + - Optional feature loading + - Runtime extensibility + - Reduce initial memory footprint + + Requires: + - DFS for file system access + - Module support in build system + + Note: Increases complexity and security considerations. + Enable for dynamic module/plugin support. if RT_USING_MODULE config RT_USING_CUSTOM_DLMODULE bool "Enable load dynamic module by custom" default n + help + Enable custom dynamic module loader. + + Allows implementing custom module loading logic: + - Custom file format support + - Special initialization sequences + - Security checks and validation + - Custom symbol resolution + + Use cases: + - Proprietary module formats + - Enhanced security validation + - Special loading requirements + + Disable for standard ELF module loading. + Enable only if custom loader needed. endif rsource "ipc/Kconfig" diff --git a/components/libc/posix/ipc/Kconfig b/components/libc/posix/ipc/Kconfig index 2bec2077546..c295ad7143c 100644 --- a/components/libc/posix/ipc/Kconfig +++ b/components/libc/posix/ipc/Kconfig @@ -7,11 +7,52 @@ config RT_USING_POSIX_PIPE select RT_USING_POSIX_POLL select RT_USING_RESOURCE_ID default n + help + Enable POSIX pipes and FIFOs for inter-process communication. + + Provides: + - Anonymous pipes: pipe(pipefd) + - Named pipes (FIFOs): mkfifo(path, mode) + - Unidirectional byte streams + - Blocking and non-blocking I/O + + Features: + - Simple producer-consumer pattern + - Works with select/poll for multiplexing + - File descriptor based (can use read/write) + + Use cases: + - Parent-child process communication + - Shell command pipelines + - Simple message passing + - Event notification + + Buffer size: RT_USING_POSIX_PIPE_SIZE + + Enable for POSIX pipe/FIFO support. + Essential for shell pipeline and process IPC. config RT_USING_POSIX_PIPE_SIZE int "Set pipe buffer size" depends on RT_USING_POSIX_PIPE default 512 + help + Size of pipe buffer in bytes. + + Default: 512 bytes + + Trade-offs: + Larger buffer: + + More data can be buffered + + Better performance for burst writes + - More memory per pipe + + Smaller buffer: + + Less memory usage + - More frequent blocking on writes + + Typical values: 512-4096 bytes + Adjust based on typical message sizes and memory constraints. # We have't implement of 'systemv ipc', so hide it firstly. # @@ -28,11 +69,75 @@ config RT_USING_POSIX_MESSAGE_QUEUE select RT_USING_MESSAGEQUEUE_PRIORITY select RT_USING_DFS_MQUEUE default n + help + Enable POSIX message queues for IPC. + + Provides POSIX message queue APIs: + - mq_open(): Open/create message queue + - mq_send()/mq_receive(): Send/receive messages + - mq_timedsend()/mq_timedreceive(): With timeout + - mq_notify(): Async notification + - mq_getattr()/mq_setattr(): Queue attributes + + Features: + - Priority-based message delivery + - Named queues (visible in /dev/mqueue) + - Blocking and non-blocking modes + - Timeout support + - Asynchronous notification + + vs. Pipes: + + Message boundaries preserved + + Priority-based delivery + + Can be used with select/poll + - More overhead per message + + Use cases: + - Process communication with priorities + - Event notification systems + - Service request queues + - RT-Smart IPC + + Requires DFS with MQUEUE support. + Enable for POSIX message queue IPC. config RT_USING_POSIX_MESSAGE_SEMAPHORE bool "Enable posix semaphore " select RT_USING_POSIX_CLOCK default n + help + Enable POSIX named and unnamed semaphores. + + Provides semaphore APIs: + - sem_init()/sem_destroy(): Unnamed semaphores + - sem_open()/sem_close()/sem_unlink(): Named semaphores + - sem_wait()/sem_trywait()/sem_timedwait(): Acquire + - sem_post(): Release + - sem_getvalue(): Get current value + + Types: + - Unnamed (memory-based): For thread synchronization + - Named (file-based): For process synchronization + + Features: + - Counting semaphore (value > 1) + - Binary semaphore (value = 0 or 1) + - Timeout support + - Non-blocking try operation + + Use cases: + - Thread/process synchronization + - Resource counting + - Producer-consumer patterns + - Mutual exclusion + + vs. Mutex: + + Can be used for signaling (sem_post from any thread) + + Counting capability + - No ownership tracking + + Enable for POSIX semaphore support. + Essential for POSIX synchronization. comment "Socket is in the 'Network' category" From fdb16a407f379d892b381f2475d5bb930414ea4e Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Mon, 17 Nov 2025 10:06:50 +0000 Subject: [PATCH 6/6] Add comprehensive help for PIC and OFW driver Kconfig files Co-authored-by: Rbb666 <64397326+Rbb666@users.noreply.github.com> --- components/drivers/ofw/Kconfig | 130 +++++++++++++++++++++++++ components/drivers/pic/Kconfig | 171 ++++++++++++++++++++++++++++++++- 2 files changed, 300 insertions(+), 1 deletion(-) diff --git a/components/drivers/ofw/Kconfig b/components/drivers/ofw/Kconfig index 5d6f12bf9fb..e893a839f62 100755 --- a/components/drivers/ofw/Kconfig +++ b/components/drivers/ofw/Kconfig @@ -6,24 +6,154 @@ menuconfig RT_USING_OFW select RT_USING_MEMBLOCK depends on RT_USING_DM default n + help + Enable Open Firmware (Device Tree) support. + + OFW/Device Tree provides hardware description separate from code: + - Flattened Device Tree (FDT/DTB) parsing + - Hardware discovery and configuration + - Platform-independent device drivers + - Runtime hardware detection + + Features: + - Standard device tree bindings + - Property parsing and access + - Node traversal and searching + - Phandle reference resolution + - Address translation + - Interrupt mapping + + Benefits: + - Single kernel binary for multiple boards + - Easier board porting (just change DTB) + - Better hardware abstraction + - Industry-standard hardware description + + Use cases: + - ARM/RISC-V systems with complex hardware + - Supporting multiple board variants + - Dynamic hardware configuration + - PCI, USB, network device enumeration + + Requires: + - RT_USING_DM (Device Model) + - Memory block allocator + - Abstract Data Types (ADT) support + + Essential for modern ARM Cortex-A and RISC-V systems. + Enable for device tree-based hardware discovery. config RT_USING_BUILTIN_FDT bool "Using builtin fdt in kernel" depends on RT_USING_OFW default n + help + Embed Flattened Device Tree (FDT) binary into kernel image. + + When enabled: + - DTB file linked into kernel binary + - No need for bootloader to pass DTB + - DTB always available at boot + + Advantages: + + Simpler boot process + + No DTB location dependencies + + Guaranteed DTB availability + + Disadvantages: + - Larger kernel image + - Must rebuild kernel to change DTB + - Less flexible than bootloader-provided DTB + + Typical use: + - Systems without proper bootloader + - Debugging and development + - Single-board configurations + + Alternative: Have bootloader pass DTB address to kernel. + + Enable for embedded DTB in kernel image. config RT_BUILTIN_FDT_PATH string "Builtin fdt path, will rebuild if have dts" depends on RT_USING_BUILTIN_FDT default "rtthread.dtb" + help + Path to the compiled Device Tree Blob (DTB) file to embed. + + Default: "rtthread.dtb" + + This file is included in the kernel binary during linking. + + Workflow: + 1. Write device tree source (.dts file) + 2. Compile to DTB: dtc -I dts -O dtb -o rtthread.dtb rtthread.dts + 3. Set this path to the DTB location + 4. Rebuild kernel (DTB will be embedded) + + Path can be: + - Relative to build directory + - Absolute path + + Kernel will automatically rebuild if DTS changes (if build system configured). config RT_FDT_EARLYCON_MSG_SIZE int "Earlycon message buffer size (KB)" depends on RT_USING_OFW default 128 + help + Size of early console message buffer in kilobytes. + + Default: 128 KB + + Early console (earlycon) provides debug output before full console initialization: + - Available during early boot + - Before full UART driver loads + - Critical for debugging boot failures + + Buffer stores messages when: + - Console not yet available + - Output faster than transmission + + Larger buffer: + + More boot messages captured + + Better for verbose debugging + - More memory usage + + Smaller buffer: + + Less memory overhead + - May lose early messages + + Increase for detailed boot debugging. + Decrease to save memory if earlycon not critical. config RT_USING_OFW_BUS_RANGES_NUMBER int "Max bus ranges number" depends on RT_USING_OFW default 8 if ARCH_CPU_64BIT default 4 + help + Maximum number of bus address ranges for device tree translation. + + Default: + - 64-bit systems: 8 ranges + - 32-bit systems: 4 ranges + + Bus ranges define address space mappings: + - CPU address to device bus address + - PCI memory/IO spaces + - Different bus protocols (AHB, APB, AXI) + + Each range describes a memory window mapping. + + Typical usage: + - PCI: 2-3 ranges (prefetchable mem, non-prefetchable mem, I/O) + - Complex SoCs: 4-8 ranges for different buses + + Increase for: + - Complex bus hierarchies + - Multiple PCI buses + - Systems with many address spaces + + Each range uses ~32-48 bytes of memory. + Set based on your SoC's bus complexity. diff --git a/components/drivers/pic/Kconfig b/components/drivers/pic/Kconfig index 448818fab7c..d04942e7488 100755 --- a/components/drivers/pic/Kconfig +++ b/components/drivers/pic/Kconfig @@ -4,6 +4,33 @@ menuconfig RT_USING_PIC select RT_USING_ADT_BITMAP depends on RT_USING_DM default n + help + Enable Platform Interrupt Controller (PIC) framework. + + PIC provides unified interrupt controller abstraction for: + - ARM GIC (Generic Interrupt Controller) v1/v2/v3 + - Platform-specific interrupt controllers + - MSI/MSI-X (Message Signaled Interrupts) + - Interrupt hierarchy and cascading + + Features: + - Device model integration + - Device tree support (OFW) + - Multiple interrupt controller support + - Interrupt routing and affinity + - Statistics and profiling + + Use cases: + - ARM Cortex-A systems with GIC + - SMP systems requiring interrupt affinity + - Systems using device tree + - Complex interrupt hierarchies + + Requires: + - RT_USING_DM (Device Model) + - Abstract Data Types (ADT) support + + Enable for advanced interrupt management with GIC or complex IRQ routing. config RT_USING_PIC_STATISTICS bool "Enable ISR execution time statistics" @@ -11,35 +38,153 @@ config RT_USING_PIC_STATISTICS depends on RT_USING_KTIME depends on RT_USING_INTERRUPT_INFO default n + help + Enable interrupt service routine (ISR) execution time tracking. + + Provides statistics for each interrupt: + - Total execution time + - Minimum/maximum execution time + - Average execution time + - Interrupt count + + Benefits: + - Performance profiling + - Identify slow interrupt handlers + - Optimize ISR performance + - Debug interrupt latency issues + + Requirements: + - KTIME for high-resolution timing + - RT_USING_INTERRUPT_INFO for interrupt tracking + + Overhead: + - Minimal per-interrupt timing overhead + - Memory for statistics (~40 bytes per IRQ) + + Enable for interrupt performance analysis. + Disable in production to save memory and overhead. config MAX_HANDLERS int "IRQ max handlers" depends on RT_USING_PIC range 1 4294967294 default 256 + help + Maximum number of interrupt handlers supported by PIC. + + Default: 256 handlers + + This limits the total number of IRQ lines the system can handle. + + Typical values: + - Small systems: 64-128 IRQs + - Medium systems: 256-512 IRQs + - Large systems: 512-1024 IRQs + + Memory usage: ~16-32 bytes per handler slot + + Set based on your SoC's interrupt controller capabilities. + Check GIC documentation for maximum SPIs (Shared Peripheral Interrupts). config RT_PIC_ARM_GIC bool "ARM GICv2/v1" depends on RT_USING_PIC select RT_USING_OFW default n + help + Enable ARM Generic Interrupt Controller version 1/2 (GICv1/GICv2). + + GICv2 features: + - Up to 1020 interrupt sources + - Support for SGIs (Software Generated Interrupts) + - Support for PPIs (Private Peripheral Interrupts) + - Support for SPIs (Shared Peripheral Interrupts) + - CPU interfaces for each core + - Distributor for routing interrupts + + Used in: + - ARM Cortex-A5/A7/A8/A9/A15/A17 + - Many ARM-based SoCs + + Requires device tree (OFW) for configuration. + + Enable for ARM Cortex-A systems with GICv2. config RT_PIC_ARM_GIC_V2M bool "ARM GIC V2M" if RT_PIC_ARM_GIC && RT_PCI_MSI depends on RT_USING_OFW default n + help + Enable GICv2m MSI (Message Signaled Interrupts) support. + + GICv2m provides: + - MSI support for GICv2 (which lacks native MSI) + - PCIe device interrupt handling + - Doorbell-style interrupt delivery + + Allows PCIe devices to use MSI with GICv2. + + Requirements: + - RT_PIC_ARM_GIC enabled + - RT_PCI_MSI for PCI MSI support + - Device tree configuration + + Enable for PCIe systems with GICv2 requiring MSI support. config RT_PIC_ARM_GIC_V3 bool "ARM GICv3" depends on RT_USING_PIC select RT_USING_OFW default n + help + Enable ARM Generic Interrupt Controller version 3 (GICv3). + + GICv3 enhancements over GICv2: + - Better scalability (supports more cores) + - System register access (no memory-mapped CPU interface) + - Affinity routing for flexible interrupt routing + - Locality-specific peripheral interrupts (LPI) + - ITS (Interrupt Translation Service) for MSI + - Support for GICv4 virtualization extensions + + Used in: + - ARM Cortex-A53/A55/A57/A72/A73/A76 + - ARMv8 and ARMv9 systems + - Modern ARM SoCs + + Requires device tree (OFW) for configuration. + + Enable for ARM Cortex-A systems with GICv3. config RT_PIC_ARM_GIC_V3_ITS bool "ARM GICv3 ITS (Interrupt Translation Service)" if RT_PIC_ARM_GIC_V3 && RT_PCI_MSI depends on RT_USING_OFW select RT_USING_ADT_REF default n + help + Enable GICv3 ITS for MSI/MSI-X support. + + ITS (Interrupt Translation Service) provides: + - Native MSI support for PCIe and other devices + - LPI (Locality-specific Peripheral Interrupts) management + - Efficient interrupt routing for thousands of devices + - Scalable to large systems + + Features: + - Translates MSI writes to LPIs + - Device and interrupt ID management + - Interrupt collection for CPU targeting + + Required for: + - PCIe MSI/MSI-X on GICv3 + - Large-scale systems with many devices + - Modern ARM servers and complex SoCs + + Memory overhead: + - ITS tables for device/interrupt mapping + - LPI configuration tables + + Enable for GICv3 systems with PCIe requiring MSI support. config RT_PIC_ARM_GIC_V3_ITS_IRQ_MAX int "IRQ maximum used" @@ -47,7 +192,23 @@ config RT_PIC_ARM_GIC_V3_ITS_IRQ_MAX default 127 if ARCH_CPU_64BIT default 63 help - Recommended to be based on the bit length (full bits) of maximum usage. + Maximum number of ITS-managed LPIs (Locality-specific Peripheral Interrupts). + + Recommended to be based on the bit length (full bits) of maximum usage. + + Default values: + - 64-bit systems: 127 (uses 7 bits) + - 32-bit systems: 63 (uses 6 bits) + + LPI IDs typically start from 8192 and can go very high. + This setting affects ITS table allocation. + + Increase for: + - Systems with many PCIe devices + - MSI-X devices using multiple vectors + + Each LPI uses memory in ITS configuration tables. + Set based on actual device count to balance memory usage. config RT_PIC_ARM_GIC_MAX_NR int @@ -55,6 +216,14 @@ config RT_PIC_ARM_GIC_MAX_NR depends on RT_PIC_ARM_GIC default 2 if SOC_REALVIEW default 1 + help + Maximum number of GIC instances in the system. + + Most systems have 1 GIC. + Some systems may have cascaded GICs or multiple interrupt controllers. + + Automatically configured based on SoC type. + Users typically don't need to modify this. if RT_USING_PIC osource "$(SOC_DM_PIC_DIR)/Kconfig"