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Commit 28976ea

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Ian Seyler
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Add MSI helper functions
- add msi.asm - add os_bus_cap_check function
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4 files changed

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‎src/drivers.asm‎

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; Internal
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%include "drivers/apic.asm"
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%include "drivers/ioapic.asm"
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%include "drivers/msi.asm"
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%include "drivers/ps2.asm"
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%include "drivers/serial.asm"
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%include "drivers/timer.asm"

‎src/drivers/msi.asm‎

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; =============================================================================
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; BareMetal -- a 64-bit OS written in Assembly for x86-64 systems
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; Copyright (C) 2008-2025 Return Infinity -- see LICENSE.TXT
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;
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; Message Signaled Interrupts (MSI-X and MSI)
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; =============================================================================
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; -----------------------------------------------------------------------------
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; Initialize MSI-X for a device
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; IN: RDX = Packed Bus address (as per syscalls/bus.asm)
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; AL = Start Vector
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msix_init:
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push r8
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push rdx
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push rcx
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push rbx
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push rax
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mov r8b, al
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; Check for MSI-X in PCI Capabilities
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mov cl, 0x11 ; PCI Capability ID for MSI-X
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call os_bus_cap_check
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jc msix_init_error
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; Enable MSI-X
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msix_init_enable:
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push rdx
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; Enable MSI-X, Mask it, Get Table Size
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; Example MSI-X Entry (From QEMU xHCI Controller)
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; 000FA011 <- Cap ID 0x11 (MSI-X), next ptr 0xA0, message control 0x000F - Table size is bits 10:0 so 0x0F
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; 00003000 <- BIR (2:0) is 0x0 so BAR0, Table Offset (31:3) - 8-byte aligned so clear low 3 bits - 0x3000 in this case
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; 00003800 <- Pending Bit BIR (2:0) and Pending Bit Offset (31:3) - 0x3800 in this case
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; Message Control - Enable (15), Function Mask (14), Table Size (10:0)
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call os_bus_read
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mov ecx, eax ; Save for Table Size
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bts eax, 31 ; Enable MSI-X
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bts eax, 30 ; Set Function Mask
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call os_bus_write
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shr ecx, 16 ; Shift Message Control to low 16-bits
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and cx, 0x7FF ; Keep bits 10:0
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; Read the BIR and Table Offset
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push rdx
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add dl, 1
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call os_bus_read
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mov ebx, eax ; EBX for the Table Offset
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and ebx, 0xFFFFFFF8 ; Clear bits 2:0
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and eax, 0x00000007 ; Keep bits 2:0 for the BIR
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add al, 0x04 ; Add offset to start of BARs
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mov dl, al
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call os_bus_read ; Read the BAR address
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add rax, rbx ; Add offset to base
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sub rax, 0x04
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mov rdi, rax
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pop rdx
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; Configure MSI-X Table
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add cx, 1 ; Table Size is 0-indexed
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mov ebx, 0x00004000 ; Trigger Mode (15), Level (14), Delivery Mode (10:8), Vector (7:0)
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mov bl, r8b ; Store start vector
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msix_init_create_entry:
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mov rax, [os_LocalAPICAddress] ; 0xFEE for bits 31:20, Dest (19:12), RH (3), DM (2)
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stosd ; Store Message Address Low
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shr rax, 32 ; Rotate the high bits to EAX
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stosd ; Store Message Address High
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mov eax, ebx
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inc ebx
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stosd ; Store Message Data
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xor eax, eax ; Bits 31:1 are reserved, Masked (0) - 1 for masked
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stosd ; Store Vector Control
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dec cx
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cmp cx, 0
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jne msix_init_create_entry
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; Unmask MSI-X via bus
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pop rdx
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call os_bus_read
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btr eax, 30 ; Clear Function Mask
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call os_bus_write
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pop rax
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pop rbx
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pop rcx
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pop rdx
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pop r8
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clc ; Clear the carry flag
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ret
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msix_init_error:
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pop rax
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pop rbx
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pop rcx
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pop rdx
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pop r8
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stc ; Set the carry flag
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ret
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; -----------------------------------------------------------------------------
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; -----------------------------------------------------------------------------
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; Initialize MSI for a device
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; IN: RDX = Packed Bus address (as per syscalls/bus.asm)
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; AL = Start Vector
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msi_init:
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push rdx
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push rcx
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push rbx
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push rax
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mov bl, al
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; Check for MSI in PCI Capabilities
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mov cl, 0x05 ; PCI Capability ID for MSI
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call os_bus_cap_check
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jc msi_init_error
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; Enable MSI
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msi_init_enable:
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push rdx
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; Enable MSI
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; Example MSI Entry (From Intel test system)
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; 00869005 <- Cap ID 0x05 (MSI), next ptr 0x90, message control 0x0x0086 (64-bit, MMC 8)
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; 00000000 <- Message Address Low
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; 00000000 <- Message Address High
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; 00000000 <- Message Data (15:0)
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; 00000000 <- Mask (only exists if Per-vector masking is enabled)
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; 00000000 <- Pending (only exists if Per-vector masking is enabled)
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; Message Control - Per-vector masking (8), 64-bit (7), Multiple Message Enable (6:4), Multiple Message Capable (3:1), Enable (0)
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; MME/MMC 000b = 1, 001b = 2, 010b = 4, 011b = 8, 100b = 16, 101b = 32
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; Todo - Test bit 7, Check Multiple Message Capable, copy to Multiple Message Enable
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add dl, 1
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mov rax, [os_LocalAPICAddress] ; 0xFEE for bits 31:20, Dest (19:12), RH (3), DM (2)
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call os_bus_write ; Store Message Address Low
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add dl, 1
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shr rax, 32 ; Rotate the high bits to EAX
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call os_bus_write ; Store Message Address High
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add dl, 1
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mov eax, 0x00004000 ; Trigger Mode (15), Level (14), Delivery Mode (10:8), Vector (7:0)
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mov al, bl ; Store start vector
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call os_bus_write ; Store Message Data
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sub dl, 3
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call os_bus_read ; Get Message Control
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bts eax, 21 ; Debug - See MME to 8
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bts eax, 20 ; Debug - See MME to 8
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bts eax, 16 ; Set Enable
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call os_bus_write ; Update Message Control
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; Unmask MSI via bus
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pop rdx
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call os_bus_read
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btr eax, 30 ; Clear Function Mask
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call os_bus_write
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msi_init_done:
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pop rax
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pop rbx
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pop rcx
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pop rdx
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clc ; Clear the carry flag
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ret
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msi_init_error:
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pop rax
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pop rbx
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pop rcx
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pop rdx
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stc ; Set the carry flag
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ret
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; -----------------------------------------------------------------------------
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; =============================================================================
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; EOF

‎src/drivers/net/virtio-net.asm‎

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@@ -575,6 +575,27 @@ net_virtio_poll_nodata:
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; -----------------------------------------------------------------------------
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; -----------------------------------------------------------------------------
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; Virtio-net Interrupt
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align 8
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net_virtio_int:
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push rcx
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push rax
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; Clear pending interrupt (if set)
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; Acknowledge the interrupt
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mov ecx, APIC_EOI
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xor eax, eax
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call os_apic_write
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pop rax
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pop rcx
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iretq
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; -----------------------------------------------------------------------------
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; Variables
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virtio_net_notify_offset: dq 0
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virtio_net_notify_offset_multiplier: dq 0

‎src/syscalls/bus.asm‎

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@@ -139,5 +139,45 @@ os_bus_read_bar_io:
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; -----------------------------------------------------------------------------
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; -----------------------------------------------------------------------------
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; Check for a device capability
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; IN: RDX = Packed Bus address (as per syscalls/bus.asm)
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; CL = Capability
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; OUT: RDX = Packed Bus address
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; Carry clear = Capability found
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; Carry set = Capability not found
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os_bus_cap_check:
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push rax
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mov dl, 1
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call os_bus_read ; Read register 1 for Status/Command
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bt eax, 20 ; Check bit 4 of the Status word (31:16)
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jnc os_bus_cap_check_error ; If if doesn't exist then bail out
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mov dl, 13
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call os_bus_read ; Read register 13 for the Capabilities Pointer (7:0)
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and al, 0xFC ; Clear the bottom two bits as they are reserved
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os_bus_cap_check_next:
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shr al, 2 ; Quick divide by 4
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mov dl, al
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call os_bus_read
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cmp al, cl
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je os_bus_cap_check_done
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os_bus_cap_check_next_offset:
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shr eax, 8 ; Shift pointer to AL
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cmp al, 0x00 ; End of linked list?
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jne os_bus_cap_check_next ; If not, continue reading, otherwise fall through to error
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os_bus_cap_check_error:
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pop rax
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stc ; Set the carry flag
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ret
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os_bus_cap_check_done:
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pop rax
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clc ; Clear the carry flag
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ret
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; -----------------------------------------------------------------------------
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; =============================================================================
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; EOF

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