Add tests for verilog_domain_yosys global setting

Signed-off-by: Robert Winkler <rwinkler@antmicro.com>

Author: rw1nkler

.travis.yml

@@ -22,6 +22,12 @@ jobs:
         - source env/conda/bin/activate sphinxcontrib-verilog-diagrams
         - cd tests && python3 -m unittest test.TestYosysScript
 
+    - stage: Tests
+      name: "Test verilog_diagram_yosys config variable"
+      script:
+        - source env/conda/bin/activate sphinxcontrib-verilog-diagrams
+        - cd tests && python3 -m unittest test.TestYosysType
+
     - stage: Build
       name: "Build"
       script:

environment.yml

@@ -11,6 +11,7 @@ dependencies:
 - pip
 - python=3.7
 - sphinx
+- yosys
 - pip:          # Packages installed from PyPI
   - -r file:requirements.txt
   - -r file:docs/requirements.txt

tests/test.py

@@ -10,6 +10,7 @@
 
 VERILOG_DIAGRAMS_PATH = os.path.abspath("..")
 
+## Helpers
 
 def get_sphinx_dirs(test_build_dir):
     sphinx_dirs = {
@@ -29,8 +30,37 @@ def generate_sphinx_config(test_build_dir, **jinja_dict):
         template = env.get_template("conf.py.template")
         template.stream(**jinja_dict).dump(fd)
 
+## Base class for tests
 
-class TestSkins(unittest.TestCase):
+class TestBase(unittest.TestCase):
+
+    def print_test_header(self, case_name, test_name):
+        print("")
+        print("# ---------------------------------------------------------- #")
+        print("# TEST CASE: {}".format(case_name))
+        print("# TEST NAME: {}".format(test_name))
+        print("# ---------------------------------------------------------- #")
+        print("")
+
+    def prepare_test(self, test_name, test_build_dir, test_files, **test_jinja_dict):
+        self.print_test_header(self.TEST_CASE_NAME, test_name)
+
+        # Create the TestCase build directory
+        os.makedirs(test_build_dir, exist_ok=True)
+
+        # Generate a Sphinx config
+        generate_sphinx_config(test_build_dir, **test_jinja_dict)
+
+        # Copy the test files
+        for src in test_files:
+            src_basename = os.path.basename(src)
+            dst = os.path.join(test_build_dir, src_basename)
+            shutil.copyfile(src, dst)
+
+
+## Test cases
+
+class TestSkins(TestBase):
 
     TEST_CASE_NAME = "TestSkins"
     TEST_CASE_BUILD_DIR = os.path.join("build", TEST_CASE_NAME)
@@ -50,17 +80,7 @@ def test_netlistsvg_diagram(self):
             "custom_variables": "verilog_diagram_skin = os.path.realpath('skin-purple.svg')"
         }
 
-        # Create the TestCase build directory
-        os.makedirs(TEST_BUILD_DIR, exist_ok=True)
-
-        # Generate a Sphinx config
-        generate_sphinx_config(TEST_BUILD_DIR, **TEST_JINJA_DICT)
-
-        # Copy the test files
-        for src in TEST_FILES:
-            src_basename = os.path.basename(src)
-            dst = os.path.join(TEST_BUILD_DIR, src_basename)
-            shutil.copyfile(src, dst)
+        self.prepare_test(TEST_NAME, TEST_BUILD_DIR, TEST_FILES, **TEST_JINJA_DICT)
 
         # Run the Sphinx
         sphinx_dirs = get_sphinx_dirs(TEST_BUILD_DIR)
@@ -69,7 +89,7 @@ def test_netlistsvg_diagram(self):
             app.build(force_all=True)
 
 
-class TestYosysScript(unittest.TestCase):
+class TestYosysScript(TestBase):
 
     TEST_CASE_NAME = "TestYosysScript"
     TEST_CASE_BUILD_DIR = os.path.join("build", TEST_CASE_NAME)
@@ -89,24 +109,86 @@ def test_yosys_script(self):
             "custom_variables": "verilog_diagram_yosys_script = os.path.realpath('yosys_script.ys')"
         }
 
-        # Create the TestCase build directory
-        os.makedirs(TEST_BUILD_DIR, exist_ok=True)
+        self.prepare_test(TEST_NAME, TEST_BUILD_DIR, TEST_FILES, **TEST_JINJA_DICT)
 
-        # Generate a Sphinx config
-        generate_sphinx_config(TEST_BUILD_DIR, **TEST_JINJA_DICT)
+        # Run the Sphinx
+        sphinx_dirs = get_sphinx_dirs(TEST_BUILD_DIR)
+        with docutils_namespace():
+            app = Sphinx(buildername="html", warningiserror=True, **sphinx_dirs)
+            app.build(force_all=True)
 
-        # Copy the test files
-        for src in TEST_FILES:
-            src_basename = os.path.basename(src)
-            dst = os.path.join(TEST_BUILD_DIR, src_basename)
-            shutil.copyfile(src, dst)
+class TestYosysType(TestBase):
+
+    TEST_CASE_NAME = "TestYowasp"
+    TEST_CASE_BUILD_DIR = os.path.join("build", TEST_CASE_NAME)
+
+    def test_yosys_yowasp(self):
+        TEST_NAME = "test_yosys_yowasp"
+        TEST_BUILD_DIR = os.path.join("build", self.TEST_CASE_NAME, TEST_NAME)
+        TEST_FILES = [
+            "test_yosys_type/test_yosys_yowasp.rst",
+            "verilog/adder.v"
+        ]
+        TEST_JINJA_DICT = {
+            "verilog_diagrams_path": "'{}'".format(VERILOG_DIAGRAMS_PATH),
+            "master_doc": "'test_yosys_yowasp'",
+            "custom_variables": ""
+        }
+
+        self.prepare_test(TEST_NAME, TEST_BUILD_DIR, TEST_FILES, **TEST_JINJA_DICT)
+
+        # Run the Sphinx
+        sphinx_dirs = get_sphinx_dirs(TEST_BUILD_DIR)
+        with docutils_namespace():
+            app = Sphinx(buildername="html", warningiserror=True, **sphinx_dirs)
+            app.build(force_all=True)
+
+    @unittest.skipIf(shutil.which('yosys') is None, 'Skipping test_yosys_system. Yosys is not installed!')
+    def test_yosys_system(self):
+        TEST_NAME = "test_yosys_system"
+        TEST_BUILD_DIR = os.path.join("build", self.TEST_CASE_NAME, TEST_NAME)
+        TEST_FILES = [
+            "test_yosys_type/test_yosys_system.rst",
+            "verilog/adder.v"
+        ]
+        TEST_JINJA_DICT = {
+            "verilog_diagrams_path": "'{}'".format(VERILOG_DIAGRAMS_PATH),
+            "master_doc": "'test_yosys_system'",
+            "custom_variables": "verilog_diagram_yosys = 'system'"
+        }
+
+        self.prepare_test(TEST_NAME, TEST_BUILD_DIR, TEST_FILES, **TEST_JINJA_DICT)
 
         # Run the Sphinx
         sphinx_dirs = get_sphinx_dirs(TEST_BUILD_DIR)
         with docutils_namespace():
             app = Sphinx(buildername="html", warningiserror=True, **sphinx_dirs)
             app.build(force_all=True)
 
+    @unittest.skipIf(shutil.which('yosys') is None, 'Skipping test_yosys_path. Yosys is not installed!')
+    def test_yosys_path(self):
+        TEST_NAME = "test_yosys_path"
+        TEST_BUILD_DIR = os.path.join("build", self.TEST_CASE_NAME, TEST_NAME)
+        TEST_FILES = [
+            "test_yosys_type/test_yosys_path.rst",
+            "verilog/adder.v"
+        ]
+
+        yosys_path = shutil.which("yosys")
+
+        TEST_JINJA_DICT = {
+            "verilog_diagrams_path": "'{}'".format(VERILOG_DIAGRAMS_PATH),
+            "master_doc": "'test_yosys_path'",
+            "custom_variables": "verilog_diagram_yosys = '{}'".format(yosys_path)
+        }
+
+        self.prepare_test(TEST_NAME, TEST_BUILD_DIR, TEST_FILES, **TEST_JINJA_DICT)
+
+        # Run the Sphinx
+        sphinx_dirs = get_sphinx_dirs(TEST_BUILD_DIR)
+        with docutils_namespace():
+            app = Sphinx(buildername="html", warningiserror=True, **sphinx_dirs)
+            app.build(force_all=True)
 
 if __name__ == '__main__':
     unittest.main()

tests/test_yosys_type/test_yosys_path.rst

@@ -0,0 +1,56 @@
+Test Yowasp - path
+==================
+
+This test checks whether the ability to switch between different Yosys types
+works as intended. This functionality is enabled by ``verilog_domain_yosys``
+variable, which can take the following values:
+
+- ``yowasp`` (default)
+- ``system``
+- ``<path-to-yosys>``
+
+The diagrams presented below have been generated using the ``<path-to-yosys>`` option.
+
+Here is the fragment of the ``conf.py`` script, used to configure the extension:
+
+.. literalinclude:: conf.py
+   :lines: 58
+
+Yosys BlackBox Diagram
+----------------------
+
+.. code-block:: rst
+
+   .. verilog-diagram:: adder.v
+      :type: yosys-blackbox
+      :module: ADDER
+
+.. verilog-diagram:: adder.v
+   :type: yosys-blackbox
+   :module: ADDER
+
+Yosys AIG Diagram
+-----------------
+
+.. code-block:: rst
+
+   .. verilog-diagram:: adder.v
+      :type: yosys-aig
+      :module: ADDER
+
+.. verilog-diagram:: adder.v
+   :type: yosys-aig
+   :module: ADDER
+
+Netlistsvg Diagram
+------------------
+
+.. code-block:: rst
+
+   .. verilog-diagram:: adder.v
+      :type: netlistsvg
+      :module: ADDER
+
+.. verilog-diagram:: adder.v
+   :type: netlistsvg
+   :module: ADDER

tests/test_yosys_type/test_yosys_system.rst

@@ -0,0 +1,56 @@
+Test Yowasp - system
+====================
+
+This test checks whether the ability to switch between different Yosys types
+works as intended. This functionality is enabled by ``verilog_domain_yosys``
+variable, which can take the following values:
+
+- ``yowasp`` (default)
+- ``system``
+- ``<path-to-yosys>``
+
+The diagrams presented below have been generated using the ``system`` option.
+
+Here is the fragment of the ``conf.py`` script, used to configure the extension::
+
+   verilog_diagram_yosys = 'system'
+
+Yosys BlackBox Diagram
+----------------------
+
+.. code-block:: rst
+
+   .. verilog-diagram:: adder.v
+      :type: yosys-blackbox
+      :module: ADDER
+
+.. verilog-diagram:: adder.v
+   :type: yosys-blackbox
+   :module: ADDER
+
+Yosys AIG Diagram
+-----------------
+
+.. code-block:: rst
+
+   .. verilog-diagram:: adder.v
+      :type: yosys-aig
+      :module: ADDER
+
+.. verilog-diagram:: adder.v
+   :type: yosys-aig
+   :module: ADDER
+
+Netlistsvg Diagram
+------------------
+
+.. code-block:: rst
+
+   .. verilog-diagram:: adder.v
+      :type: netlistsvg
+      :module: ADDER
+
+.. verilog-diagram:: adder.v
+   :type: netlistsvg
+   :module: ADDER
+

tests/test_yosys_type/test_yosys_yowasp.rst

@@ -0,0 +1,57 @@
+Test Yowasp - yowasp
+====================
+
+This test checks whether the ability to switch between different Yosys types
+works as intended. This functionality is enabled by ``verilog_domain_yosys``
+variable, which can take the following values:
+
+- ``yowasp`` (default)
+- ``system``
+- ``<path-to-yosys>``
+
+The diagrams presented below have been generated using the ``<yowasp>`` option.
+
+Here is the fragment of the ``conf.py`` script, used to configure the extension::
+
+   verilog_diagram_yosys = 'yowasp'
+
+.. note:: ``yowasp`` is the default setting. The configuration presented above can be omitted.
+
+Yosys BlackBox Diagram
+----------------------
+
+.. code-block:: rst
+
+   .. verilog-diagram:: adder.v
+      :type: yosys-blackbox
+      :module: ADDER
+
+.. verilog-diagram:: adder.v
+   :type: yosys-blackbox
+   :module: ADDER
+
+Yosys AIG Diagram
+-----------------
+
+.. code-block:: rst
+
+   .. verilog-diagram:: adder.v
+      :type: yosys-aig
+      :module: ADDER
+
+.. verilog-diagram:: adder.v
+   :type: yosys-aig
+   :module: ADDER
+
+Netlistsvg Diagram
+------------------
+
+.. code-block:: rst
+
+   .. verilog-diagram:: adder.v
+      :type: netlistsvg
+      :module: ADDER
+
+.. verilog-diagram:: adder.v
+   :type: netlistsvg
+   :module: ADDER