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2 parents b76a72b + 68562a0 commit 8c16b8fCopy full SHA for 8c16b8f
setup.py
@@ -54,8 +54,8 @@
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description='Generate diagrams from Verilog in Sphinx.',
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long_description=readme,
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long_description_content_type="text/x-rst",
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- author="Tim 'mithro' Ansell",
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- author_email='me@mith.ro',
+ author="The SymbiFlow Authors",
+ author_email='symbiflow@lists.librecores.org',
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url='https://github.com/SymbiFlow/sphinxcontrib-verilog-diagrams',
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packages=find_packages(),
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license="Apache 2.0",
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