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Change verilog-diagram directive to hdl-diagram in tests
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
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‎tests/test_skins/test_skins.rst‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -13,33 +13,33 @@ Here is the fragment of the ``conf.py`` script::
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verilog_diagram_skin = os.path.realpath('skin-purple.svg')
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The following ``verilog-diagram`` diagram should be placed in an RST file::
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The following ``hdl-diagram`` diagram should be placed in an RST file::
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER
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Below you can see the output of the directive. The diagram presented below
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should be black-purple.
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER
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Per Diagram Skin Setting
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------------------------
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Per diagram skin setting is achieved by using the ``:skin:`` option with
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the ``verilog-diagram`` directive.
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the ``hdl-diagram`` directive.
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The following ``verilog-diagram`` directive should be placed in an RST file::
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The following ``hdl-diagram`` directive should be placed in an RST file::
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER
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:skin: skin-yellow.svg
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER
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:skin: skin-yellow.svg
@@ -54,17 +54,17 @@ It is possible to overwrite the global skin settings using the ``:skin:`` option
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To reset the skin setting to the default value, you can use the ``:skin: default``
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setting.
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The following ``verilog-diagram`` directive should be placed in an RST file::
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The following ``hdl-diagram`` directive should be placed in an RST file::
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER
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:skin: default
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Below you can see the output of the directive. The diagram presented below
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should be black-white.
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER
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:skin: default

‎tests/test_yosys_script/test_yosys_script.rst‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -21,15 +21,15 @@ Here is the fragment of the ``conf.py`` script::
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verilog_diagram_yosys_script = os.path.realpath('yosys_script.ys')
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The following ``verilog-diagram`` diagram should be placed in an RST file::
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The following ``hdl-diagram`` diagram should be placed in an RST file::
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-blackbox
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:module: ADDER
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Below you can see the output of the directive:
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-blackbox
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:module: ADDER
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@@ -40,19 +40,19 @@ Script per diagram
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++++++++++++++++++
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Per diagram Yosys script setting is achieved by using the ``:yosys_script:``
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option with the ``verilog-diagram`` directive.
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option with the ``hdl-diagram`` directive.
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Here is the example of a ``verilog-diagram`` directive that should be
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Here is the example of a ``hdl-diagram`` directive that should be
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placed in an RST file::
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-blackbox
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:module: ADDER
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:yosys_script: yosys_script2.ys
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Below you can see the output of the directive:
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-blackbox
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:module: ADDER
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:yosys_script: yosys_script2.ys
@@ -67,17 +67,17 @@ It is possible to overwrite the global Yosys script setting using
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the ``:yosys_script:`` option. To reset the setting to the default value,
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you can use the ``:yosys_script: default`` setting.
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Here is an example of a ``verilog-diagram`` directive that should be
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Here is an example of a ``hdl-diagram`` directive that should be
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placed in an RST file::
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-blackbox
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:module: ADDER
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:yosys_script: default
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Below you can see the output of the directive:
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-blackbox
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:module: ADDER
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:yosys_script: default
@@ -93,11 +93,11 @@ Global script test
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-aig
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:module: ADDER
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-aig
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:module: ADDER
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@@ -106,12 +106,12 @@ Script per diagram
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-aig
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:module: ADDER
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:yosys_script: yosys_script2.ys
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-aig
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:module: ADDER
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:yosys_script: yosys_script2.ys
@@ -121,12 +121,12 @@ Global overwrite
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-aig
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:module: ADDER
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:yosys_script: default
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-aig
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:module: ADDER
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:yosys_script: default
@@ -140,12 +140,12 @@ Global script test
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER
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:yosys_script: default
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER
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:yosys_script: default
@@ -155,12 +155,12 @@ Script per diagram
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER
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:yosys_script: default
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER
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:yosys_script: default
@@ -170,12 +170,12 @@ Global overwrite
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER
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:yosys_script: default
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER
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:yosys_script: default

‎tests/test_yosys_type/test_yosys_path.rst‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -21,11 +21,11 @@ Yosys BlackBox Diagram
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-blackbox
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:module: ADDER
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-blackbox
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:module: ADDER
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@@ -34,11 +34,11 @@ Yosys AIG Diagram
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-aig
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:module: ADDER
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-aig
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:module: ADDER
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@@ -47,10 +47,10 @@ Netlistsvg Diagram
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER

‎tests/test_yosys_type/test_yosys_system.rst‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -20,11 +20,11 @@ Yosys BlackBox Diagram
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-blackbox
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:module: ADDER
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-blackbox
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:module: ADDER
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@@ -33,11 +33,11 @@ Yosys AIG Diagram
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-aig
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:module: ADDER
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-aig
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:module: ADDER
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@@ -46,11 +46,11 @@ Netlistsvg Diagram
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER
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‎tests/test_yosys_type/test_yosys_yowasp.rst‎

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Original file line numberDiff line numberDiff line change
@@ -22,11 +22,11 @@ Yosys BlackBox Diagram
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-blackbox
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:module: ADDER
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-blackbox
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:module: ADDER
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@@ -35,11 +35,11 @@ Yosys AIG Diagram
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-aig
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:module: ADDER
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: yosys-aig
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:module: ADDER
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@@ -48,10 +48,10 @@ Netlistsvg Diagram
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER
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.. verilog-diagram:: adder.v
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.. hdl-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER

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