From 3c224776202b789b5fb0b1d4a04afc26ab1a143d Mon Sep 17 00:00:00 2001 From: jeff-7 Date: Tue, 3 Mar 2026 00:02:25 -0500 Subject: [PATCH 01/16] Add Zbs single-bit operations implementation (RV32, SystemVerilog) --- src/ext/b/zbs.sv | 70 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 src/ext/b/zbs.sv diff --git a/src/ext/b/zbs.sv b/src/ext/b/zbs.sv new file mode 100644 index 00000000..bc98a5ff --- /dev/null +++ b/src/ext/b/zbs.sv @@ -0,0 +1,70 @@ +// Zbs: Single-Bit Operations (RV32) +// Implements the RV32 Zbs (Bit-Manipulation Single-Bit) instructions: +// - bclr / bclri : Clear bit +// - bset / bseti : Set bit +// - binv / binvi : Invert bit +// - bext / bexti : Extract bit (result placed in bit[0]) +// The decoder is responsible for selecting the correct operands: +// - For register-form instructions: +// reg2 = rs2 +// - For immediate-form instructions: +// reg2[4:0] = shamt +// Therefore, this module simply treats reg2[4:0] as the bit index. +// +// inst encoding (local mini-ALU selector): +// 3'b000 : bclr / bclri +// 3'b001 : bset / bseti +// 3'b010 : binv / binvi +// 3'b011 : bext / bexti +// 3'b100-111 : reserved +// +// Notes: +// - RV32 => XLEN = 32 +// - Bit index is masked to 5 bits (0–31) +// - All logic is purely combinational + +module zbs ( + input logic [31:0] reg1, // rs1 operand + input logic [31:0] reg2, // rs2 or immediate (index source) + input logic [2:0] inst, // operation selector + output logic [31:0] out // result +); + + // Extract bit index (only lower 5 bits used in RV32) + logic [4:0] index; + + // Bit mask for single-bit operations + logic [31:0] mask; + + // Combinational ALU logic + always_comb begin + + // reg2 may come from rs2 or immediate (handled externally) + index = reg2[4:0]; + + // Generate one-hot mask: 1 << index + mask = 32'h1 << index; + + // Perform selected single-bit operation + unique case (inst) + + // Clear selected bit + 3'b000: out = reg1 & ~mask; + + // Set selected bit + 3'b001: out = reg1 | mask; + + // Invert selected bit + 3'b010: out = reg1 ^ mask; + + // Extract selected bit into bit[0] + // Upper bits are zero + 3'b011: out = (reg1 >> index) & 32'h1; + + // Default safe output + default: out = 32'd0; + + endcase + end + +endmodule \ No newline at end of file From 180479630fc2dad25373a622923b0fb1d4fba756 Mon Sep 17 00:00:00 2001 From: jeff-7 Date: Tue, 3 Mar 2026 00:05:20 -0500 Subject: [PATCH 02/16] Ignore macOS .DS_Store --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 8738c930..08982cae 100644 --- a/.gitignore +++ b/.gitignore @@ -28,3 +28,4 @@ out/** !out/.gitkeep build/** !build/.gitkeep +.DS_Store From 38ffa5d8d1e9c9c19079268ef35c8c81a23ee36d Mon Sep 17 00:00:00 2001 From: jeff-7 Date: Tue, 3 Mar 2026 00:42:31 -0500 Subject: [PATCH 03/16] Fix svlint style issues in Zbs --- src/ext/b/zbs.sv | 86 +++++++++++++++++++----------------------------- 1 file changed, 33 insertions(+), 53 deletions(-) diff --git a/src/ext/b/zbs.sv b/src/ext/b/zbs.sv index bc98a5ff..b7f3d7d2 100644 --- a/src/ext/b/zbs.sv +++ b/src/ext/b/zbs.sv @@ -1,70 +1,50 @@ // Zbs: Single-Bit Operations (RV32) -// Implements the RV32 Zbs (Bit-Manipulation Single-Bit) instructions: -// - bclr / bclri : Clear bit -// - bset / bseti : Set bit -// - binv / binvi : Invert bit -// - bext / bexti : Extract bit (result placed in bit[0]) -// The decoder is responsible for selecting the correct operands: -// - For register-form instructions: -// reg2 = rs2 -// - For immediate-form instructions: -// reg2[4:0] = shamt -// Therefore, this module simply treats reg2[4:0] as the bit index. // -// inst encoding (local mini-ALU selector): -// 3'b000 : bclr / bclri -// 3'b001 : bset / bseti -// 3'b010 : binv / binvi -// 3'b011 : bext / bexti -// 3'b100-111 : reserved +// Implements: +// - bclr / bclri +// - bset / bseti +// - binv / binvi +// - bext / bexti // -// Notes: -// - RV32 => XLEN = 32 -// - Bit index is masked to 5 bits (0–31) -// - All logic is purely combinational +// Design note: +// - This module is purely functional. +// - reg2[4:0] is treated as the bit index. +// - R/I distinction is handled in the decoder. module zbs ( - input logic [31:0] reg1, // rs1 operand - input logic [31:0] reg2, // rs2 or immediate (index source) - input logic [2:0] inst, // operation selector - output logic [31:0] out // result + input logic [31:0] reg1 , // rs1 operand + input logic [31:0] reg2 , // rs2 or immediate (bit index source) + input logic [1:0] inst , // operation selector + output logic [31:0] out // result ); - // Extract bit index (only lower 5 bits used in RV32) - logic [4:0] index; + logic [4:0] index ; + logic [31:0] mask ; - // Bit mask for single-bit operations - logic [31:0] mask; + always_comb + begin + index = reg2[4:0]; + mask = 32'h1 << index; - // Combinational ALU logic - always_comb begin - - // reg2 may come from rs2 or immediate (handled externally) - index = reg2[4:0]; + // Zbs operation selector + case (inst) - // Generate one-hot mask: 1 << index - mask = 32'h1 << index; + // 000 : bclr / bclri → clear selected bit + 3'b000 : out = reg1 & ~mask; - // Perform selected single-bit operation - unique case (inst) + // 001 : bset / bseti → set selected bit + 3'b001 : out = reg1 | mask; - // Clear selected bit - 3'b000: out = reg1 & ~mask; + // 010 : binv / binvi → invert selected bit + 3'b010 : out = reg1 ^ mask; - // Set selected bit - 3'b001: out = reg1 | mask; + // 011 : bext / bexti → extract selected bit (to bit[0]) + 3'b011 : out = (reg1 >> index) & 32'h1; - // Invert selected bit - 3'b010: out = reg1 ^ mask; + // others → safe default + default : out = 32'd0; - // Extract selected bit into bit[0] - // Upper bits are zero - 3'b011: out = (reg1 >> index) & 32'h1; - - // Default safe output - default: out = 32'd0; - - endcase - end + endcase + end endmodule \ No newline at end of file From 07a45567f4d6273b7319191523dbd611970e4b94 Mon Sep 17 00:00:00 2001 From: jeff-7 Date: Tue, 3 Mar 2026 00:48:43 -0500 Subject: [PATCH 04/16] Fix svlint issues --- src/ext/b/zbs.sv | 47 +++++++++++++++++++++++------------------------ 1 file changed, 23 insertions(+), 24 deletions(-) diff --git a/src/ext/b/zbs.sv b/src/ext/b/zbs.sv index b7f3d7d2..45754c21 100644 --- a/src/ext/b/zbs.sv +++ b/src/ext/b/zbs.sv @@ -7,44 +7,43 @@ // - bext / bexti // // Design note: -// - This module is purely functional. -// - reg2[4:0] is treated as the bit index. -// - R/I distinction is handled in the decoder. +// - Purely combinational ALU block +// - reg2[4:0] used as bit index +// - R/I distinction handled in decoder module zbs ( - input logic [31:0] reg1 , // rs1 operand - input logic [31:0] reg2 , // rs2 or immediate (bit index source) - input logic [1:0] inst , // operation selector - output logic [31:0] out // result + input logic [31:0] reg1 , + input logic [31:0] reg2 , + input logic [1:0] inst , + output logic [31:0] out ); logic [4:0] index ; logic [31:0] mask ; always_comb - begin - index = reg2[4:0]; - mask = 32'h1 << index; + index = reg2[4:0] ; - // Zbs operation selector - case (inst) + always_comb + mask = 32'h1 << index ; + + always_comb + case (inst) - // 000 : bclr / bclri → clear selected bit - 3'b000 : out = reg1 & ~mask; + // 00 : bclr + 2'b00 : out = reg1 & ~mask ; - // 001 : bset / bseti → set selected bit - 3'b001 : out = reg1 | mask; + // 01 : bset + 2'b01 : out = reg1 | mask ; - // 010 : binv / binvi → invert selected bit - 3'b010 : out = reg1 ^ mask; + // 10 : binv + 2'b10 : out = reg1 ^ mask ; - // 011 : bext / bexti → extract selected bit (to bit[0]) - 3'b011 : out = (reg1 >> index) & 32'h1; + // 11 : bext + 2'b11 : out = (reg1 >> index) & 32'h1 ; - // others → safe default - default : out = 32'd0; + default : out = 32'd0 ; - endcase - end + endcase endmodule \ No newline at end of file From c627fe2f6acc45119d485ffe71f75e3d0a2a9e49 Mon Sep 17 00:00:00 2001 From: jeff-7 Date: Tue, 3 Mar 2026 01:05:16 -0500 Subject: [PATCH 05/16] Fix final svlint whitespace issues --- src/ext/b/zbs.sv | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/src/ext/b/zbs.sv b/src/ext/b/zbs.sv index 45754c21..7444576f 100644 --- a/src/ext/b/zbs.sv +++ b/src/ext/b/zbs.sv @@ -11,38 +11,38 @@ // - reg2[4:0] used as bit index // - R/I distinction handled in decoder -module zbs ( - input logic [31:0] reg1 , - input logic [31:0] reg2 , - input logic [1:0] inst , +module zbs( + input logic [31:0] reg1, + input logic [31:0] reg2, + input logic [1:0] inst, output logic [31:0] out ); - logic [4:0] index ; - logic [31:0] mask ; + logic [4:0] index; + logic [31:0] mask; always_comb - index = reg2[4:0] ; + index = reg2[4:0]; always_comb - mask = 32'h1 << index ; + mask = 32'h1 << index; always_comb - case (inst) + case(inst) // 00 : bclr - 2'b00 : out = reg1 & ~mask ; + 2'b00: out = reg1 & ~mask; // 01 : bset - 2'b01 : out = reg1 | mask ; + 2'b01: out = reg1 | mask; // 10 : binv - 2'b10 : out = reg1 ^ mask ; + 2'b10: out = reg1 ^ mask; // 11 : bext - 2'b11 : out = (reg1 >> index) & 32'h1 ; + 2'b11: out = (reg1 >> index) & 32'h1; - default : out = 32'd0 ; + default: out = 32'd0; endcase From 227077b3fcf4893273e63d0edfd92f6e89eee826 Mon Sep 17 00:00:00 2001 From: jeff-7 Date: Tue, 3 Mar 2026 01:05:32 -0500 Subject: [PATCH 06/16] Force CI From 41fd19edcec47a3fa7226e191a1b83103c372b74 Mon Sep 17 00:00:00 2001 From: jeff-7 Date: Tue, 3 Mar 2026 01:07:51 -0500 Subject: [PATCH 07/16] Fix final svlint whitespace issues --- src/ext/b/zbs.sv | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/ext/b/zbs.sv b/src/ext/b/zbs.sv index 7444576f..af93df66 100644 --- a/src/ext/b/zbs.sv +++ b/src/ext/b/zbs.sv @@ -12,10 +12,10 @@ // - R/I distinction handled in decoder module zbs( - input logic [31:0] reg1, - input logic [31:0] reg2, - input logic [1:0] inst, - output logic [31:0] out + input logic [31:0] reg1, // rs1 operand + input logic [31:0] reg2, // rs2 or immediate (bit index source) + input logic [1:0] inst, // operation selector + output logic [31:0] out // result ); logic [4:0] index; @@ -30,18 +30,19 @@ module zbs( always_comb case(inst) - // 00 : bclr + // 00 : bclr / bclri → clear selected bit 2'b00: out = reg1 & ~mask; - // 01 : bset + // 01 : bset / bseti → set selected bit 2'b01: out = reg1 | mask; - // 10 : binv + // 10 : binv / binvi → invert selected bit 2'b10: out = reg1 ^ mask; - // 11 : bext + // 11 : bext / bexti → extract selected bit (to bit[0]) 2'b11: out = (reg1 >> index) & 32'h1; + // others → safe default default: out = 32'd0; endcase From 9bcdeb1837fa6b0bd56ef413710c814efeb7388d Mon Sep 17 00:00:00 2001 From: jeff-7 Date: Tue, 3 Mar 2026 01:08:19 -0500 Subject: [PATCH 08/16] Force CI From 9c900385f1ccc0392c5821dc98aa00bb7bc7b266 Mon Sep 17 00:00:00 2001 From: jeff-7 Date: Tue, 3 Mar 2026 01:14:36 -0500 Subject: [PATCH 09/16] Fix comma-leading and keyword spacing --- src/ext/b/zbs.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/ext/b/zbs.sv b/src/ext/b/zbs.sv index af93df66..b3d39e82 100644 --- a/src/ext/b/zbs.sv +++ b/src/ext/b/zbs.sv @@ -11,11 +11,11 @@ // - reg2[4:0] used as bit index // - R/I distinction handled in decoder -module zbs( - input logic [31:0] reg1, // rs1 operand - input logic [31:0] reg2, // rs2 or immediate (bit index source) - input logic [1:0] inst, // operation selector - output logic [31:0] out // result +module zbs ( + input logic [31:0] reg1 , // rs1 operand + input logic [31:0] reg2 , // rs2 or immediate (bit index source) + input logic [1:0] inst , // operation selector + output logic [31:0] out ); logic [4:0] index; @@ -28,7 +28,7 @@ module zbs( mask = 32'h1 << index; always_comb - case(inst) + case (inst) // 00 : bclr / bclri → clear selected bit 2'b00: out = reg1 & ~mask; From 533d464466180f5a12be41ddf4629f3685e944d5 Mon Sep 17 00:00:00 2001 From: jeff-7 Date: Tue, 3 Mar 2026 01:14:51 -0500 Subject: [PATCH 10/16] Force CI From a897b446ecab14839f9cff4537e5fc9d9a5f77d6 Mon Sep 17 00:00:00 2001 From: jeff-7 Date: Tue, 3 Mar 2026 01:21:14 -0500 Subject: [PATCH 11/16] Fix comma-leading and keyword spacing --- src/ext/b/zbs.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/ext/b/zbs.sv b/src/ext/b/zbs.sv index b3d39e82..b49adf0d 100644 --- a/src/ext/b/zbs.sv +++ b/src/ext/b/zbs.sv @@ -12,10 +12,10 @@ // - R/I distinction handled in decoder module zbs ( - input logic [31:0] reg1 , // rs1 operand - input logic [31:0] reg2 , // rs2 or immediate (bit index source) - input logic [1:0] inst , // operation selector - output logic [31:0] out + input logic [31:0] reg1 // rs1 operand + , input logic [31:0] reg2 // rs2 or immediate (bit index source) + , input logic [1:0] inst // operation selector + , output logic [31:0] out //result ); logic [4:0] index; From 4a918f29d72e3e5b51316d44b7df94d8ead073fd Mon Sep 17 00:00:00 2001 From: jeff-7 Date: Fri, 6 Mar 2026 01:31:32 -0500 Subject: [PATCH 12/16] Replace parameter with localparam in params.svh --- src/ext/b/zbs.sv | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/src/ext/b/zbs.sv b/src/ext/b/zbs.sv index b49adf0d..e0d8c9fc 100644 --- a/src/ext/b/zbs.sv +++ b/src/ext/b/zbs.sv @@ -1,31 +1,30 @@ -// Zbs: Single-Bit Operations (RV32) +// ----------------------------------------------------------------------------- +// Zbs Extension – Single-Bit Instructions (RV32) +// Reference: +// RISC-V Bitmanip Extension Specification v1.0.0 +// Section 5.4 – Zbs (Single-Bit Instructions) // -// Implements: -// - bclr / bclri -// - bset / bseti -// - binv / binvi -// - bext / bexti -// -// Design note: -// - Purely combinational ALU block -// - reg2[4:0] used as bit index -// - R/I distinction handled in decoder +// Notes: +// - Purely combinational logic +// - Bit index = reg2[4:0] +// - R/I distinction handled in decode stage +// ----------------------------------------------------------------------------- module zbs ( - input logic [31:0] reg1 // rs1 operand - , input logic [31:0] reg2 // rs2 or immediate (bit index source) - , input logic [1:0] inst // operation selector - , output logic [31:0] out //result + input data_t reg1 // rs1 operand + , input data_t reg2 // rs2 or immediate (bit index source) + , input logic [1:0] inst // operation selector + , output data_t out //result ); logic [4:0] index; - logic [31:0] mask; + data_t mask; always_comb index = reg2[4:0]; always_comb - mask = 32'h1 << index; + mask = data_t'(32'h1) << index; always_comb case (inst) @@ -40,10 +39,10 @@ module zbs ( 2'b10: out = reg1 ^ mask; // 11 : bext / bexti → extract selected bit (to bit[0]) - 2'b11: out = (reg1 >> index) & 32'h1; + 2'b11: out = (reg1 >> index) & data_t'(32'h1); // others → safe default - default: out = 32'd0; + default: out = '0; endcase From f8678c9be949869f15cb975f8414651409a5de97 Mon Sep 17 00:00:00 2001 From: SenseiPrimexus Date: Sat, 14 Mar 2026 20:47:54 -0400 Subject: [PATCH 13/16] Add Zbs instruction testbench with assertions and randomized tests --- test/zbs_tb.sv | 134 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 test/zbs_tb.sv diff --git a/test/zbs_tb.sv b/test/zbs_tb.sv new file mode 100644 index 00000000..00cc29b9 --- /dev/null +++ b/test/zbs_tb.sv @@ -0,0 +1,134 @@ +`timescale 1ns/1ns +`include "test/utils.svh" + +module zbs_tb; + +logic [31:0] reg1; +logic [31:0] reg2; +logic [2:0] inst; +logic [31:0] out; + +logic [31:0] expected; + +zbs uut ( + .reg1(reg1), + .reg2(reg2), + .inst(inst), + .out(out) +); + +initial begin + + // -------- bclr test -------- + reg1 = 32'b1010; + reg2 = 32'd1; // clear bit 1 + inst = 3'b000; + #10; + + expected = reg1 & ~(32'h1 << reg2[4:0]); + + assert(out == expected) + else $fatal("bclr failed: expected %b got %b", expected, out); + + + // -------- bset test -------- + reg1 = 32'b1110; + reg2 = 32'd0; // set bit 0 + inst = 3'b001; + #10; + + expected = reg1 | (32'h1 << reg2[4:0]); + + assert(out == expected) + else $fatal("bset failed: expected %b got %b", expected, out); + + + // -------- binv test -------- + reg1 = 32'b1010; + reg2 = 32'd1; + inst = 3'b010; + #10; + + expected = reg1 ^ (32'h1 << reg2[4:0]); + + assert(out == expected) + else $fatal("binv failed: expected %b got %b", expected, out); + + + // -------- bext test -------- + reg1 = 32'b1010; + reg2 = 32'd3; + inst = 3'b011; + #10; + + expected = (reg1 >> reg2[4:0]) & 32'h1; + + assert(out == expected) + else $fatal("bext failed: expected %b got %b", expected, out); + + // -------- Edge Cases --------- + + // Bit 0 boundary + reg1 = 32'hFFFFFFFF; + reg2 = 32'd0; + inst = 3'b000; // bclr + #10; + + expected = reg1 & ~(32'h1 << reg2[4:0]); + + assert(out == expected) + else $fatal("corner case bit0 failed"); + + + // Bit 31 boundary + reg1 = 32'hFFFFFFFF; + reg2 = 32'd31; + inst = 3'b000; // bclr + #10; + + expected = reg1 & ~(32'h1 << reg2[4:0]); + + assert(out == expected) + else $fatal("corner case bit31 failed"); + + + // ----------- Randomized Testing (Experimental) ----------- + + + repeat (1000) begin + + reg1 = $urandom; + reg2 = $urandom % 32; + inst = $urandom % 4; + + #1; + + case(inst) + + 3'b000: expected = reg1 & ~(32'h1 << reg2[4:0]); + + 3'b001: expected = reg1 | (32'h1 << reg2[4:0]); + + 3'b010: expected = reg1 ^ (32'h1 << reg2[4:0]); + + 3'b011: expected = (reg1 >> reg2[4:0]) & 32'h1; + + default: expected = 32'd0; + + endcase + + assert(out == expected) + else $fatal("random test failed: inst=%0d reg1=%h reg2=%d expected=%h got=%h", + inst, reg1, reg2, expected, out); + + end + + $display("All tests passed!"); + + $finish; + +end + +`SETUP_VCD_DUMP(zbs_tb) + +endmodule \ No newline at end of file From 50f5aee5720fd97107aeda599a3ac90ac4787b34 Mon Sep 17 00:00:00 2001 From: SenseiPrimexus Date: Sun, 15 Mar 2026 15:29:22 -0400 Subject: [PATCH 14/16] Match bit width in bext comparison --- test/zbs_tb.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/zbs_tb.sv b/test/zbs_tb.sv index 00cc29b9..3b740edc 100644 --- a/test/zbs_tb.sv +++ b/test/zbs_tb.sv @@ -61,7 +61,7 @@ initial begin inst = 3'b011; #10; - expected = (reg1 >> reg2[4:0]) & 32'h1; + expected = {31'b0, reg1[reg2[4:0]]}; assert(out == expected) else $fatal("bext failed: expected %b got %b", expected, out); @@ -111,7 +111,7 @@ initial begin 3'b010: expected = reg1 ^ (32'h1 << reg2[4:0]); - 3'b011: expected = (reg1 >> reg2[4:0]) & 32'h1; + 3'b011: expected = {31'b0, reg1[reg2[4:0]]}; default: expected = 32'd0; From de0a360946d517cf10a6611f5a2d1ca0c147ef19 Mon Sep 17 00:00:00 2001 From: SenseiPrimexus Date: Sun, 15 Mar 2026 15:49:19 -0400 Subject: [PATCH 15/16] Fix: Resolve svlint style violations --- test/zbs_tb.sv | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/test/zbs_tb.sv b/test/zbs_tb.sv index 3b740edc..6ed9e2aa 100644 --- a/test/zbs_tb.sv +++ b/test/zbs_tb.sv @@ -11,9 +11,9 @@ logic [31:0] out; logic [31:0] expected; zbs uut ( - .reg1(reg1), - .reg2(reg2), - .inst(inst), + .reg1(reg1), + .reg2(reg2), + .inst(inst), .out(out) ); @@ -27,7 +27,7 @@ initial begin expected = reg1 & ~(32'h1 << reg2[4:0]); - assert(out == expected) + assert (out == expected) else $fatal("bclr failed: expected %b got %b", expected, out); @@ -39,7 +39,7 @@ initial begin expected = reg1 | (32'h1 << reg2[4:0]); - assert(out == expected) + assert (out == expected) else $fatal("bset failed: expected %b got %b", expected, out); @@ -51,7 +51,7 @@ initial begin expected = reg1 ^ (32'h1 << reg2[4:0]); - assert(out == expected) + assert (out == expected) else $fatal("binv failed: expected %b got %b", expected, out); @@ -63,7 +63,7 @@ initial begin expected = {31'b0, reg1[reg2[4:0]]}; - assert(out == expected) + assert (out == expected) else $fatal("bext failed: expected %b got %b", expected, out); // -------- Edge Cases --------- @@ -76,7 +76,7 @@ initial begin expected = reg1 & ~(32'h1 << reg2[4:0]); - assert(out == expected) + assert (out == expected) else $fatal("corner case bit0 failed"); @@ -88,13 +88,12 @@ initial begin expected = reg1 & ~(32'h1 << reg2[4:0]); - assert(out == expected) + assert (out == expected) else $fatal("corner case bit31 failed"); // ----------- Randomized Testing (Experimental) ----------- - repeat (1000) begin reg1 = $urandom; @@ -117,7 +116,7 @@ initial begin endcase - assert(out == expected) + assert (out == expected) else $fatal("random test failed: inst=%0d reg1=%h reg2=%d expected=%h got=%h", inst, reg1, reg2, expected, out); From 0894e45add9724a54f079f66cfc2dc8c882e42a1 Mon Sep 17 00:00:00 2001 From: Boris Date: Sun, 22 Mar 2026 17:33:48 +0000 Subject: [PATCH 16/16] fix svlint infractions --- test/zbs_tb.sv | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/test/zbs_tb.sv b/test/zbs_tb.sv index 6ed9e2aa..cfe9407f 100644 --- a/test/zbs_tb.sv +++ b/test/zbs_tb.sv @@ -10,11 +10,11 @@ logic [31:0] out; logic [31:0] expected; -zbs uut ( - .reg1(reg1), - .reg2(reg2), - .inst(inst), - .out(out) +zbs uut + ( .reg1 ( reg1 ) + , .reg2 ( reg2 ) + , .inst ( inst ) + , .out ( out ) ); initial begin @@ -93,7 +93,7 @@ initial begin // ----------- Randomized Testing (Experimental) ----------- - + repeat (1000) begin reg1 = $urandom; @@ -102,7 +102,7 @@ initial begin #1; - case(inst) + case (inst) 3'b000: expected = reg1 & ~(32'h1 << reg2[4:0]); @@ -116,9 +116,9 @@ initial begin endcase - assert (out == expected) - else $fatal("random test failed: inst=%0d reg1=%h reg2=%d expected=%h got=%h", - inst, reg1, reg2, expected, out); + assert (out == expected) else + $fatal("random test failed: inst=%0d reg1=%h reg2=%d expected=%h got=%h" + , inst, reg1, reg2, expected, out); end @@ -130,4 +130,4 @@ end `SETUP_VCD_DUMP(zbs_tb) -endmodule \ No newline at end of file +endmodule