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Merge pull request #77 from Bochlin/std_logic_misc
Comment out std_logic_vector functions from std_logic_misc.
2 parents 181709e + dc565c6 commit 34325ce

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‎vhdl_libraries/synopsys/std_logic_misc.vhdl‎

Lines changed: 134 additions & 134 deletions
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ package std_logic_misc is
5454
--synopsys synthesis_on
5555
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
5656

57-
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
57+
-- function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
5858
--synopsys synthesis_off
5959

6060
-- attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
@@ -69,15 +69,15 @@ package std_logic_misc is
6969

7070
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
7171

72-
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
73-
return STD_LOGIC_VECTOR;
72+
-- function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
73+
-- return STD_LOGIC_VECTOR;
7474
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
7575
return STD_ULOGIC_VECTOR;
7676

77-
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
78-
return STD_LOGIC_VECTOR;
79-
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
80-
return STD_ULOGIC_VECTOR;
77+
-- function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
78+
-- return STD_LOGIC_VECTOR;
79+
-- function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
80+
-- return STD_ULOGIC_VECTOR;
8181

8282
--synopsys synthesis_on
8383

@@ -143,12 +143,12 @@ package std_logic_misc is
143143
) return BIT;
144144

145145
--------------------------------------------------------------------
146-
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
147-
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
148-
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
149-
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
150-
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
151-
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
146+
-- function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
147+
-- function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
148+
-- function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
149+
-- function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
150+
-- function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
151+
-- function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
152152

153153
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
154154
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
@@ -263,18 +263,18 @@ package body std_logic_misc is
263263
end Drive;
264264

265265

266-
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is
267-
-- pragma built_in SYN_FEED_THRU
268-
-- pragma subpgm_id 390
269-
--synopsys synthesis_off
270-
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
271-
--synopsys synthesis_on
272-
begin
273-
--synopsys synthesis_off
274-
return STD_LOGIC_VECTOR(Value);
275-
--synopsys synthesis_on
276-
end Drive;
277-
--synopsys synthesis_off
266+
-- function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is
267+
-- -- pragma built_in SYN_FEED_THRU
268+
-- -- pragma subpgm_id 390
269+
-- --synopsys synthesis_off
270+
-- alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
271+
-- --synopsys synthesis_on
272+
-- begin
273+
-- --synopsys synthesis_off
274+
-- return STD_LOGIC_VECTOR(Value);
275+
-- --synopsys synthesis_on
276+
-- end Drive;
277+
-- --synopsys synthesis_off
278278

279279

280280
---------------------------------------------------------------------
@@ -302,25 +302,25 @@ package body std_logic_misc is
302302
end Sense;
303303

304304

305-
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
306-
return STD_LOGIC_VECTOR is
307-
-- pragma subpgm_id 392
308-
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
309-
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
310-
begin
311-
for i in Value'range loop
312-
if ( Value(i) = 'Z' ) then
313-
Result(i) := vZ;
314-
elsif Value(i) = 'U' then
315-
Result(i) := vU;
316-
elsif Value(i) = '-' then
317-
Result(i) := vDC;
318-
else
319-
Result(i) := Value(i);
320-
end if;
321-
end loop;
322-
return Result;
323-
end Sense;
305+
-- function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
306+
-- return STD_LOGIC_VECTOR is
307+
-- -- pragma subpgm_id 392
308+
-- alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
309+
-- variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
310+
-- begin
311+
-- for i in Value'range loop
312+
-- if ( Value(i) = 'Z' ) then
313+
-- Result(i) := vZ;
314+
-- elsif Value(i) = 'U' then
315+
-- Result(i) := vU;
316+
-- elsif Value(i) = '-' then
317+
-- Result(i) := vDC;
318+
-- else
319+
-- Result(i) := Value(i);
320+
-- end if;
321+
-- end loop;
322+
-- return Result;
323+
-- end Sense;
324324

325325

326326
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
@@ -344,46 +344,46 @@ package body std_logic_misc is
344344
end Sense;
345345

346346

347-
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
348-
return STD_LOGIC_VECTOR is
349-
-- pragma subpgm_id 394
350-
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
351-
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
352-
begin
353-
for i in Value'range loop
354-
if ( Value(i) = 'Z' ) then
355-
Result(i) := vZ;
356-
elsif Value(i) = 'U' then
357-
Result(i) := vU;
358-
elsif Value(i) = '-' then
359-
Result(i) := vDC;
360-
else
361-
Result(i) := Value(i);
362-
end if;
363-
end loop;
364-
return Result;
365-
end Sense;
366-
367-
368-
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
369-
return STD_ULOGIC_VECTOR is
370-
-- pragma subpgm_id 395
371-
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
372-
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
373-
begin
374-
for i in Value'range loop
375-
if ( Value(i) = 'Z' ) then
376-
Result(i) := vZ;
377-
elsif Value(i) = 'U' then
378-
Result(i) := vU;
379-
elsif Value(i) = '-' then
380-
Result(i) := vDC;
381-
else
382-
Result(i) := Value(i);
383-
end if;
384-
end loop;
385-
return Result;
386-
end Sense;
347+
-- function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
348+
-- return STD_LOGIC_VECTOR is
349+
-- -- pragma subpgm_id 394
350+
-- alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
351+
-- variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
352+
-- begin
353+
-- for i in Value'range loop
354+
-- if ( Value(i) = 'Z' ) then
355+
-- Result(i) := vZ;
356+
-- elsif Value(i) = 'U' then
357+
-- Result(i) := vU;
358+
-- elsif Value(i) = '-' then
359+
-- Result(i) := vDC;
360+
-- else
361+
-- Result(i) := Value(i);
362+
-- end if;
363+
-- end loop;
364+
-- return Result;
365+
-- end Sense;
366+
367+
368+
-- function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
369+
-- return STD_ULOGIC_VECTOR is
370+
-- -- pragma subpgm_id 395
371+
-- alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
372+
-- variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
373+
-- begin
374+
-- for i in Value'range loop
375+
-- if ( Value(i) = 'Z' ) then
376+
-- Result(i) := vZ;
377+
-- elsif Value(i) = 'U' then
378+
-- Result(i) := vU;
379+
-- elsif Value(i) = '-' then
380+
-- Result(i) := vDC;
381+
-- else
382+
-- Result(i) := Value(i);
383+
-- end if;
384+
-- end loop;
385+
-- return Result;
386+
-- end Sense;
387387

388388
---------------------------------------------------------------------
389389
--
@@ -660,56 +660,56 @@ package body std_logic_misc is
660660

661661
--------------------------------------------------------------------------
662662

663-
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
664-
-- pragma subpgm_id 399
665-
variable result: STD_LOGIC;
666-
begin
667-
result := '1';
668-
for i in ARG'range loop
669-
result := result and ARG(i);
670-
end loop;
671-
return result;
672-
end;
673-
674-
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
675-
-- pragma subpgm_id 400
676-
begin
677-
return not AND_REDUCE(ARG);
678-
end;
679-
680-
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
681-
-- pragma subpgm_id 401
682-
variable result: STD_LOGIC;
683-
begin
684-
result := '0';
685-
for i in ARG'range loop
686-
result := result or ARG(i);
687-
end loop;
688-
return result;
689-
end;
690-
691-
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
692-
-- pragma subpgm_id 402
693-
begin
694-
return not OR_REDUCE(ARG);
695-
end;
696-
697-
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
698-
-- pragma subpgm_id 403
699-
variable result: STD_LOGIC;
700-
begin
701-
result := '0';
702-
for i in ARG'range loop
703-
result := result xor ARG(i);
704-
end loop;
705-
return result;
706-
end;
707-
708-
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
709-
-- pragma subpgm_id 404
710-
begin
711-
return not XOR_REDUCE(ARG);
712-
end;
663+
-- function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
664+
-- -- pragma subpgm_id 399
665+
-- variable result: STD_LOGIC;
666+
-- begin
667+
-- result := '1';
668+
-- for i in ARG'range loop
669+
-- result := result and ARG(i);
670+
-- end loop;
671+
-- return result;
672+
-- end;
673+
674+
-- function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
675+
-- -- pragma subpgm_id 400
676+
-- begin
677+
-- return not AND_REDUCE(ARG);
678+
-- end;
679+
680+
-- function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
681+
-- -- pragma subpgm_id 401
682+
-- variable result: STD_LOGIC;
683+
-- begin
684+
-- result := '0';
685+
-- for i in ARG'range loop
686+
-- result := result or ARG(i);
687+
-- end loop;
688+
-- return result;
689+
-- end;
690+
691+
-- function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
692+
-- -- pragma subpgm_id 402
693+
-- begin
694+
-- return not OR_REDUCE(ARG);
695+
-- end;
696+
697+
-- function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
698+
-- -- pragma subpgm_id 403
699+
-- variable result: STD_LOGIC;
700+
-- begin
701+
-- result := '0';
702+
-- for i in ARG'range loop
703+
-- result := result xor ARG(i);
704+
-- end loop;
705+
-- return result;
706+
-- end;
707+
708+
-- function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
709+
-- -- pragma subpgm_id 404
710+
-- begin
711+
-- return not XOR_REDUCE(ARG);
712+
-- end;
713713

714714
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
715715
-- pragma subpgm_id 405

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