diff --git a/README.md b/README.md
index fe95e42..1dba644 100644
--- a/README.md
+++ b/README.md
@@ -1,4 +1,5 @@
-
+
+
## About
@@ -49,7 +50,7 @@ make
Compressed-first, micro-coded RISC-V CPU |
- | NVDLA |
+ NVDLA-small |
Scalable and configurable deep learning accelerator |
diff --git a/designs/asap7/lfsr_prbs_gen/config.mk b/designs/asap7/lfsr_prbs_gen/config.mk
deleted file mode 100644
index c838f3a..0000000
--- a/designs/asap7/lfsr_prbs_gen/config.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-export DESIGN_NAME = lfsr_prbs_gen
-export PLATFORM = asap7
-
--include $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/verilog.mk
-
-export SDC_FILE = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
-
-export CORE_UTILIZATION = 40
-export TNS_END_PERCENT = 100
diff --git a/designs/asap7/lfsr_prbs_gen/constraint.sdc b/designs/asap7/lfsr_prbs_gen/constraint.sdc
deleted file mode 100644
index 4958ac1..0000000
--- a/designs/asap7/lfsr_prbs_gen/constraint.sdc
+++ /dev/null
@@ -1,15 +0,0 @@
-current_design lfsr_prbs_gen
-
-set clk_name core_clock
-set clk_port_name clk
-set clk_period 230
-set clk_io_pct 0.2
-
-set clk_port [get_ports $clk_port_name]
-
-create_clock -name $clk_name -period $clk_period $clk_port
-
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
-set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/docs/images/HighTideLogo.png b/docs/images/HighTideLogo.png
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diff --git a/docs/images/HighTideLogo.svg b/docs/images/HighTideLogo.svg
new file mode 100644
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