From 49bf67b8eb6410c789d56fd72809d18de711cb2e Mon Sep 17 00:00:00 2001 From: Paolo Pedroso <108847100+paolopedroso@users.noreply.github.com> Date: Thu, 26 Mar 2026 18:34:42 -0700 Subject: [PATCH 1/2] SYNtzulA for sky130 --- .gitmodules | 3 + designs/sky130hd/SYNtzulA/BUILD.bazel | 29 + designs/sky130hd/SYNtzulA/config.mk | 14 + designs/sky130hd/SYNtzulA/constraint.sdc | 21 + .../SYNtzulA/sram/lef/fakeram_48x256_1rw.lef | 1485 +++ .../SYNtzulA/sram/lef/fakeram_64x1024_1rw.lef | 1983 +++ .../SYNtzulA/sram/lef/fakeram_64x2048_1rw.lef | 2080 ++++ .../SYNtzulA/sram/lef/fakeram_64x256_1rw.lef | 2047 ++++ .../SYNtzulA/sram/lef/fakeram_64x512_1rw.lef | 1928 +++ .../SYNtzulA/sram/lef/fakeram_64x64_1rw.lef | 1879 +++ .../SYNtzulA/sram/lib/fakeram_48x256_1rw.lib | 468 + .../SYNtzulA/sram/lib/fakeram_64x1024_1rw.lib | 468 + .../SYNtzulA/sram/lib/fakeram_64x2048_1rw.lib | 468 + .../SYNtzulA/sram/lib/fakeram_64x256_1rw.lib | 468 + .../SYNtzulA/sram/lib/fakeram_64x512_1rw.lib | 468 + .../SYNtzulA/sram/lib/fakeram_64x64_1rw.lib | 468 + designs/src/SYNtzulA/BUILD.bazel | 66 + designs/src/SYNtzulA/SYNtzulATop.v | 10177 ++++++++++++++++ designs/src/SYNtzulA/config.txt | 21 + designs/src/SYNtzulA/dev/patch-synsnn.patch | 351 + designs/src/SYNtzulA/dev/repo | 1 + designs/src/SYNtzulA/dev/setup.sh | 122 + designs/src/SYNtzulA/macros.v | 201 + designs/src/SYNtzulA/verilog.mk | 61 + 24 files changed, 25277 insertions(+) create mode 100644 designs/sky130hd/SYNtzulA/BUILD.bazel create mode 100644 designs/sky130hd/SYNtzulA/config.mk create mode 100644 designs/sky130hd/SYNtzulA/constraint.sdc create mode 100644 designs/sky130hd/SYNtzulA/sram/lef/fakeram_48x256_1rw.lef create mode 100644 designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x1024_1rw.lef create mode 100644 designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x2048_1rw.lef create mode 100644 designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x256_1rw.lef create mode 100644 designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x512_1rw.lef create mode 100644 designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x64_1rw.lef create mode 100644 designs/sky130hd/SYNtzulA/sram/lib/fakeram_48x256_1rw.lib create mode 100644 designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x1024_1rw.lib create mode 100644 designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x2048_1rw.lib create mode 100644 designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x256_1rw.lib create mode 100644 designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x512_1rw.lib create mode 100644 designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x64_1rw.lib create mode 100644 designs/src/SYNtzulA/BUILD.bazel create mode 100644 designs/src/SYNtzulA/SYNtzulATop.v create mode 100644 designs/src/SYNtzulA/config.txt create mode 100644 designs/src/SYNtzulA/dev/patch-synsnn.patch create mode 160000 designs/src/SYNtzulA/dev/repo create mode 100644 designs/src/SYNtzulA/dev/setup.sh create mode 100644 designs/src/SYNtzulA/macros.v create mode 100644 designs/src/SYNtzulA/verilog.mk diff --git a/.gitmodules b/.gitmodules index 31c106c..d9939fb 100644 --- a/.gitmodules +++ b/.gitmodules @@ -25,3 +25,6 @@ [submodule "designs/src/sha3/dev/repo"] path = designs/src/sha3/dev/repo url = https://github.com/ucb-bar/sha3 +[submodule "designs/src/SYNtzulA/dev/repo"] + path = designs/src/SYNtzulA/dev/repo + url = https://github.com/EOLAB-2025/SYNtzulA.git diff --git a/designs/sky130hd/SYNtzulA/BUILD.bazel b/designs/sky130hd/SYNtzulA/BUILD.bazel new file mode 100644 index 0000000..a5c6999 --- /dev/null +++ b/designs/sky130hd/SYNtzulA/BUILD.bazel @@ -0,0 +1,29 @@ +load("//:defs.bzl", "hightide_design") + +filegroup( + name = "sram_lefs", + srcs = glob(["sram/lef/*.lef"]) +) + +filegroup( + name = "sram_libs", + srcs = glob(["sram/lib/*.lib"]) +) + +hightide_design( + name = "SYNtzulA", + top = "service_ihp_chip", + platform = "sky130hd", + verilog_files = ["//designs/src/SYNtzulA:rtl"], + sources = { + "SDC_FILE": [":constraint.sdc"], + "ADDITIONAL_LEFS": [":sram_lefs"], + "ADDITIONAL_LIBS": [":sram_libs"], + }, + arguments = { + "DIE_AREA": "0 0 2290 2290", + "CORE_AREA": "40 40 2250 2250", + "PLACE_DENSITY": "0.60", + "HOLD_SLACK_MARGIN": "0.2", + }, +) diff --git a/designs/sky130hd/SYNtzulA/config.mk b/designs/sky130hd/SYNtzulA/config.mk new file mode 100644 index 0000000..eb5cc61 --- /dev/null +++ b/designs/sky130hd/SYNtzulA/config.mk @@ -0,0 +1,14 @@ +export DESIGN_NAME = service_ihp_chip +export PLATFORM = sky130hd +export DESIGN_NICKNAME = SYNtzulA + +-include $(BENCH_DESIGN_HOME)/src/$(DESIGN_NICKNAME)/verilog.mk + +export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc + +export DIE_AREA = 0 0 2290 2290 +export CORE_AREA = 40 40 2250 2250 + +export PLACE_DENSITY = 0.60 + +export HOLD_SLACK_MARGIN = 0.2 diff --git a/designs/sky130hd/SYNtzulA/constraint.sdc b/designs/sky130hd/SYNtzulA/constraint.sdc new file mode 100644 index 0000000..f5a45ea --- /dev/null +++ b/designs/sky130hd/SYNtzulA/constraint.sdc @@ -0,0 +1,21 @@ +#################################################################### Design +current_design service_ihp_chip + +#################################################################### Clock del sistema +set clk_name wb_clk +set clk_port_name wb_clk +set clk_period 8 +set clk_port [get_ports $clk_port_name] +create_clock -name $clk_name -period $clk_period $clk_port + +#################################################################### Clock del timer responsabile gating +set clk_name timer_clk +set clk_port_name timer_clk +set clk_period 100000 +set clk_port [get_ports $clk_port_name] +create_clock -name $clk_name -period $clk_period $clk_port + +set_max_fanout 8 [current_design] + +set_false_path -from [get_ports wb_rst] +set_false_path -from [get_ports enb_debug] \ No newline at end of file diff --git a/designs/sky130hd/SYNtzulA/sram/lef/fakeram_48x256_1rw.lef b/designs/sky130hd/SYNtzulA/sram/lef/fakeram_48x256_1rw.lef new file mode 100644 index 0000000..a3b89db --- /dev/null +++ b/designs/sky130hd/SYNtzulA/sram/lef/fakeram_48x256_1rw.lef @@ -0,0 +1,1485 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_48x256_1rw + FOREIGN fakeram_48x256_1rw 0 0 ; + SYMMETRY X Y R90 ; + SIZE 303.600 BY 399.840 ; + CLASS BLOCK ; + PIN rw0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 3.930 0.900 4.230 ; + END + END rw0_wmask_in[0] + PIN rw0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 17.530 0.900 17.830 ; + END + END rw0_wmask_in[1] + PIN rw0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 31.130 0.900 31.430 ; + END + END rw0_wmask_in[2] + PIN rw0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 44.730 0.900 45.030 ; + END + END rw0_wmask_in[3] + PIN rw0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 58.330 0.900 58.630 ; + END + END rw0_wmask_in[4] + PIN rw0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 71.930 0.900 72.230 ; + END + END rw0_wmask_in[5] + PIN rw0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 85.530 0.900 85.830 ; + END + END rw0_wmask_in[6] + PIN rw0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 99.130 0.900 99.430 ; + END + END rw0_wmask_in[7] + PIN rw0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 112.730 0.900 113.030 ; + END + END rw0_wmask_in[8] + PIN rw0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 126.330 0.900 126.630 ; + END + END rw0_wmask_in[9] + PIN rw0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 139.930 0.900 140.230 ; + END + END rw0_wmask_in[10] + PIN rw0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 153.530 0.900 153.830 ; + END + END rw0_wmask_in[11] + PIN rw0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 3.930 303.600 4.230 ; + END + END rw0_wmask_in[12] + PIN rw0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 17.530 303.600 17.830 ; + END + END rw0_wmask_in[13] + PIN rw0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 31.130 303.600 31.430 ; + END + END rw0_wmask_in[14] + PIN rw0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 44.730 303.600 45.030 ; + END + END rw0_wmask_in[15] + PIN rw0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 58.330 303.600 58.630 ; + END + END rw0_wmask_in[16] + PIN rw0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 71.930 303.600 72.230 ; + END + END rw0_wmask_in[17] + PIN rw0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 85.530 303.600 85.830 ; + END + END rw0_wmask_in[18] + PIN rw0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 99.130 303.600 99.430 ; + END + END rw0_wmask_in[19] + PIN rw0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 112.730 303.600 113.030 ; + END + END rw0_wmask_in[20] + PIN rw0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 126.330 303.600 126.630 ; + END + END rw0_wmask_in[21] + PIN rw0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 139.930 303.600 140.230 ; + END + END rw0_wmask_in[22] + PIN rw0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 153.530 303.600 153.830 ; + END + END rw0_wmask_in[23] + PIN rw0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 2.690 399.420 2.830 399.840 ; + END + END rw0_wmask_in[24] + PIN rw0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 8.210 399.420 8.350 399.840 ; + END + END rw0_wmask_in[25] + PIN rw0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 13.730 399.420 13.870 399.840 ; + END + END rw0_wmask_in[26] + PIN rw0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 19.250 399.420 19.390 399.840 ; + END + END rw0_wmask_in[27] + PIN rw0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 24.770 399.420 24.910 399.840 ; + END + END rw0_wmask_in[28] + PIN rw0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 30.290 399.420 30.430 399.840 ; + END + END rw0_wmask_in[29] + PIN rw0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 35.810 399.420 35.950 399.840 ; + END + END rw0_wmask_in[30] + PIN rw0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 41.330 399.420 41.470 399.840 ; + END + END rw0_wmask_in[31] + PIN rw0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 46.850 399.420 46.990 399.840 ; + END + END rw0_wmask_in[32] + PIN rw0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 52.370 399.420 52.510 399.840 ; + END + END rw0_wmask_in[33] + PIN rw0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 57.890 399.420 58.030 399.840 ; + END + END rw0_wmask_in[34] + PIN rw0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 63.410 399.420 63.550 399.840 ; + END + END rw0_wmask_in[35] + PIN rw0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 68.930 399.420 69.070 399.840 ; + END + END rw0_wmask_in[36] + PIN rw0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 74.450 399.420 74.590 399.840 ; + END + END rw0_wmask_in[37] + PIN rw0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 79.970 399.420 80.110 399.840 ; + END + END rw0_wmask_in[38] + PIN rw0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 85.490 399.420 85.630 399.840 ; + END + END rw0_wmask_in[39] + PIN rw0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 91.010 399.420 91.150 399.840 ; + END + END rw0_wmask_in[40] + PIN rw0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 96.530 399.420 96.670 399.840 ; + END + END rw0_wmask_in[41] + PIN rw0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 102.050 399.420 102.190 399.840 ; + END + END rw0_wmask_in[42] + PIN rw0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 107.570 399.420 107.710 399.840 ; + END + END rw0_wmask_in[43] + PIN rw0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 113.090 399.420 113.230 399.840 ; + END + END rw0_wmask_in[44] + PIN rw0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 118.610 399.420 118.750 399.840 ; + END + END rw0_wmask_in[45] + PIN rw0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 124.130 399.420 124.270 399.840 ; + END + END rw0_wmask_in[46] + PIN rw0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 129.650 399.420 129.790 399.840 ; + END + END rw0_wmask_in[47] + PIN rw0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 167.130 0.900 167.430 ; + END + END rw0_wd_in[0] + PIN rw0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 180.730 0.900 181.030 ; + END + END rw0_wd_in[1] + PIN rw0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 194.330 0.900 194.630 ; + END + END rw0_wd_in[2] + PIN rw0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 207.930 0.900 208.230 ; + END + END rw0_wd_in[3] + PIN rw0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 221.530 0.900 221.830 ; + END + END rw0_wd_in[4] + PIN rw0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 235.130 0.900 235.430 ; + END + END rw0_wd_in[5] + PIN rw0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 248.730 0.900 249.030 ; + END + END rw0_wd_in[6] + PIN rw0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 262.330 0.900 262.630 ; + END + END rw0_wd_in[7] + PIN rw0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 275.930 0.900 276.230 ; + END + END rw0_wd_in[8] + PIN rw0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 289.530 0.900 289.830 ; + END + END rw0_wd_in[9] + PIN rw0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 303.130 0.900 303.430 ; + END + END rw0_wd_in[10] + PIN rw0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 316.730 0.900 317.030 ; + END + END rw0_wd_in[11] + PIN rw0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 167.130 303.600 167.430 ; + END + END rw0_wd_in[12] + PIN rw0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 180.730 303.600 181.030 ; + END + END rw0_wd_in[13] + PIN rw0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 194.330 303.600 194.630 ; + END + END rw0_wd_in[14] + PIN rw0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 207.930 303.600 208.230 ; + END + END rw0_wd_in[15] + PIN rw0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 221.530 303.600 221.830 ; + END + END rw0_wd_in[16] + PIN rw0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 235.130 303.600 235.430 ; + END + END rw0_wd_in[17] + PIN rw0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 248.730 303.600 249.030 ; + END + END rw0_wd_in[18] + PIN rw0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 262.330 303.600 262.630 ; + END + END rw0_wd_in[19] + PIN rw0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 275.930 303.600 276.230 ; + END + END rw0_wd_in[20] + PIN rw0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 289.530 303.600 289.830 ; + END + END rw0_wd_in[21] + PIN rw0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 303.130 303.600 303.430 ; + END + END rw0_wd_in[22] + PIN rw0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 316.730 303.600 317.030 ; + END + END rw0_wd_in[23] + PIN rw0_wd_in[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 2.690 0.000 2.830 0.420 ; + END + END rw0_wd_in[24] + PIN rw0_wd_in[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 8.670 0.000 8.810 0.420 ; + END + END rw0_wd_in[25] + PIN rw0_wd_in[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 14.650 0.000 14.790 0.420 ; + END + END rw0_wd_in[26] + PIN rw0_wd_in[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 20.630 0.000 20.770 0.420 ; + END + END rw0_wd_in[27] + PIN rw0_wd_in[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 26.610 0.000 26.750 0.420 ; + END + END rw0_wd_in[28] + PIN rw0_wd_in[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 32.590 0.000 32.730 0.420 ; + END + END rw0_wd_in[29] + PIN rw0_wd_in[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 38.570 0.000 38.710 0.420 ; + END + END rw0_wd_in[30] + PIN rw0_wd_in[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 44.550 0.000 44.690 0.420 ; + END + END rw0_wd_in[31] + PIN rw0_wd_in[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 50.530 0.000 50.670 0.420 ; + END + END rw0_wd_in[32] + PIN rw0_wd_in[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 56.510 0.000 56.650 0.420 ; + END + END rw0_wd_in[33] + PIN rw0_wd_in[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 62.490 0.000 62.630 0.420 ; + END + END rw0_wd_in[34] + PIN rw0_wd_in[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 68.470 0.000 68.610 0.420 ; + END + END rw0_wd_in[35] + PIN rw0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 74.450 0.000 74.590 0.420 ; + END + END rw0_wd_in[36] + PIN rw0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 80.430 0.000 80.570 0.420 ; + END + END rw0_wd_in[37] + PIN rw0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 86.410 0.000 86.550 0.420 ; + END + END rw0_wd_in[38] + PIN rw0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 92.390 0.000 92.530 0.420 ; + END + END rw0_wd_in[39] + PIN rw0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 98.370 0.000 98.510 0.420 ; + END + END rw0_wd_in[40] + PIN rw0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 104.350 0.000 104.490 0.420 ; + END + END rw0_wd_in[41] + PIN rw0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 110.330 0.000 110.470 0.420 ; + END + END rw0_wd_in[42] + PIN rw0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 116.310 0.000 116.450 0.420 ; + END + END rw0_wd_in[43] + PIN rw0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 122.290 0.000 122.430 0.420 ; + END + END rw0_wd_in[44] + PIN rw0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 128.270 0.000 128.410 0.420 ; + END + END rw0_wd_in[45] + PIN rw0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 134.250 0.000 134.390 0.420 ; + END + END rw0_wd_in[46] + PIN rw0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 140.230 0.000 140.370 0.420 ; + END + END rw0_wd_in[47] + PIN rw0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 146.210 0.000 146.350 0.420 ; + END + END rw0_rd_out[0] + PIN rw0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 152.190 0.000 152.330 0.420 ; + END + END rw0_rd_out[1] + PIN rw0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 158.170 0.000 158.310 0.420 ; + END + END rw0_rd_out[2] + PIN rw0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 164.150 0.000 164.290 0.420 ; + END + END rw0_rd_out[3] + PIN rw0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 170.130 0.000 170.270 0.420 ; + END + END rw0_rd_out[4] + PIN rw0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 176.110 0.000 176.250 0.420 ; + END + END rw0_rd_out[5] + PIN rw0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 182.090 0.000 182.230 0.420 ; + END + END rw0_rd_out[6] + PIN rw0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 188.070 0.000 188.210 0.420 ; + END + END rw0_rd_out[7] + PIN rw0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 194.050 0.000 194.190 0.420 ; + END + END rw0_rd_out[8] + PIN rw0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 200.030 0.000 200.170 0.420 ; + END + END rw0_rd_out[9] + PIN rw0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 206.010 0.000 206.150 0.420 ; + END + END rw0_rd_out[10] + PIN rw0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 211.990 0.000 212.130 0.420 ; + END + END rw0_rd_out[11] + PIN rw0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 217.970 0.000 218.110 0.420 ; + END + END rw0_rd_out[12] + PIN rw0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 223.950 0.000 224.090 0.420 ; + END + END rw0_rd_out[13] + PIN rw0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 229.930 0.000 230.070 0.420 ; + END + END rw0_rd_out[14] + PIN rw0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 235.910 0.000 236.050 0.420 ; + END + END rw0_rd_out[15] + PIN rw0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 241.890 0.000 242.030 0.420 ; + END + END rw0_rd_out[16] + PIN rw0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 247.870 0.000 248.010 0.420 ; + END + END rw0_rd_out[17] + PIN rw0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 253.850 0.000 253.990 0.420 ; + END + END rw0_rd_out[18] + PIN rw0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 259.830 0.000 259.970 0.420 ; + END + END rw0_rd_out[19] + PIN rw0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 265.810 0.000 265.950 0.420 ; + END + END rw0_rd_out[20] + PIN rw0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 271.790 0.000 271.930 0.420 ; + END + END rw0_rd_out[21] + PIN rw0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 277.770 0.000 277.910 0.420 ; + END + END rw0_rd_out[22] + PIN rw0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 283.750 0.000 283.890 0.420 ; + END + END rw0_rd_out[23] + PIN rw0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 135.170 399.420 135.310 399.840 ; + END + END rw0_rd_out[24] + PIN rw0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 140.690 399.420 140.830 399.840 ; + END + END rw0_rd_out[25] + PIN rw0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 146.210 399.420 146.350 399.840 ; + END + END rw0_rd_out[26] + PIN rw0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 151.730 399.420 151.870 399.840 ; + END + END rw0_rd_out[27] + PIN rw0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 157.250 399.420 157.390 399.840 ; + END + END rw0_rd_out[28] + PIN rw0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 162.770 399.420 162.910 399.840 ; + END + END rw0_rd_out[29] + PIN rw0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 168.290 399.420 168.430 399.840 ; + END + END rw0_rd_out[30] + PIN rw0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 173.810 399.420 173.950 399.840 ; + END + END rw0_rd_out[31] + PIN rw0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 179.330 399.420 179.470 399.840 ; + END + END rw0_rd_out[32] + PIN rw0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 184.850 399.420 184.990 399.840 ; + END + END rw0_rd_out[33] + PIN rw0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 190.370 399.420 190.510 399.840 ; + END + END rw0_rd_out[34] + PIN rw0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 195.890 399.420 196.030 399.840 ; + END + END rw0_rd_out[35] + PIN rw0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 201.410 399.420 201.550 399.840 ; + END + END rw0_rd_out[36] + PIN rw0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 206.930 399.420 207.070 399.840 ; + END + END rw0_rd_out[37] + PIN rw0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 212.450 399.420 212.590 399.840 ; + END + END rw0_rd_out[38] + PIN rw0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 217.970 399.420 218.110 399.840 ; + END + END rw0_rd_out[39] + PIN rw0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 223.490 399.420 223.630 399.840 ; + END + END rw0_rd_out[40] + PIN rw0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 229.010 399.420 229.150 399.840 ; + END + END rw0_rd_out[41] + PIN rw0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 234.530 399.420 234.670 399.840 ; + END + END rw0_rd_out[42] + PIN rw0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 240.050 399.420 240.190 399.840 ; + END + END rw0_rd_out[43] + PIN rw0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 245.570 399.420 245.710 399.840 ; + END + END rw0_rd_out[44] + PIN rw0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 251.090 399.420 251.230 399.840 ; + END + END rw0_rd_out[45] + PIN rw0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 256.610 399.420 256.750 399.840 ; + END + END rw0_rd_out[46] + PIN rw0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 262.130 399.420 262.270 399.840 ; + END + END rw0_rd_out[47] + PIN rw0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 330.330 0.900 330.630 ; + END + END rw0_addr_in[0] + PIN rw0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 343.930 0.900 344.230 ; + END + END rw0_addr_in[1] + PIN rw0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 357.530 0.900 357.830 ; + END + END rw0_addr_in[2] + PIN rw0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 371.130 0.900 371.430 ; + END + END rw0_addr_in[3] + PIN rw0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 330.330 303.600 330.630 ; + END + END rw0_addr_in[4] + PIN rw0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 343.930 303.600 344.230 ; + END + END rw0_addr_in[5] + PIN rw0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 357.530 303.600 357.830 ; + END + END rw0_addr_in[6] + PIN rw0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 302.700 371.130 303.600 371.430 ; + END + END rw0_addr_in[7] + PIN rw0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 267.650 399.420 267.790 399.840 ; + END + END rw0_we_in + PIN rw0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 273.170 399.420 273.310 399.840 ; + END + END rw0_ce_in + PIN rw0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 278.690 399.420 278.830 399.840 ; + END + END rw0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met4 ; + RECT 2.160 4.080 3.360 395.760 ; + RECT 13.040 4.080 14.240 395.760 ; + RECT 23.920 4.080 25.120 395.760 ; + RECT 34.800 4.080 36.000 395.760 ; + RECT 45.680 4.080 46.880 395.760 ; + RECT 56.560 4.080 57.760 395.760 ; + RECT 67.440 4.080 68.640 395.760 ; + RECT 78.320 4.080 79.520 395.760 ; + RECT 89.200 4.080 90.400 395.760 ; + RECT 100.080 4.080 101.280 395.760 ; + RECT 110.960 4.080 112.160 395.760 ; + RECT 121.840 4.080 123.040 395.760 ; + RECT 132.720 4.080 133.920 395.760 ; + RECT 143.600 4.080 144.800 395.760 ; + RECT 154.480 4.080 155.680 395.760 ; + RECT 165.360 4.080 166.560 395.760 ; + RECT 176.240 4.080 177.440 395.760 ; + RECT 187.120 4.080 188.320 395.760 ; + RECT 198.000 4.080 199.200 395.760 ; + RECT 208.880 4.080 210.080 395.760 ; + RECT 219.760 4.080 220.960 395.760 ; + RECT 230.640 4.080 231.840 395.760 ; + RECT 241.520 4.080 242.720 395.760 ; + RECT 252.400 4.080 253.600 395.760 ; + RECT 263.280 4.080 264.480 395.760 ; + RECT 274.160 4.080 275.360 395.760 ; + RECT 285.040 4.080 286.240 395.760 ; + RECT 295.920 4.080 297.120 395.760 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met4 ; + RECT 2.160 4.080 3.360 395.760 ; + RECT 13.040 4.080 14.240 395.760 ; + RECT 23.920 4.080 25.120 395.760 ; + RECT 34.800 4.080 36.000 395.760 ; + RECT 45.680 4.080 46.880 395.760 ; + RECT 56.560 4.080 57.760 395.760 ; + RECT 67.440 4.080 68.640 395.760 ; + RECT 78.320 4.080 79.520 395.760 ; + RECT 89.200 4.080 90.400 395.760 ; + RECT 100.080 4.080 101.280 395.760 ; + RECT 110.960 4.080 112.160 395.760 ; + RECT 121.840 4.080 123.040 395.760 ; + RECT 132.720 4.080 133.920 395.760 ; + RECT 143.600 4.080 144.800 395.760 ; + RECT 154.480 4.080 155.680 395.760 ; + RECT 165.360 4.080 166.560 395.760 ; + RECT 176.240 4.080 177.440 395.760 ; + RECT 187.120 4.080 188.320 395.760 ; + RECT 198.000 4.080 199.200 395.760 ; + RECT 208.880 4.080 210.080 395.760 ; + RECT 219.760 4.080 220.960 395.760 ; + RECT 230.640 4.080 231.840 395.760 ; + RECT 241.520 4.080 242.720 395.760 ; + RECT 252.400 4.080 253.600 395.760 ; + RECT 263.280 4.080 264.480 395.760 ; + RECT 274.160 4.080 275.360 395.760 ; + RECT 285.040 4.080 286.240 395.760 ; + RECT 295.920 4.080 297.120 395.760 ; + END + END VDD + OBS + LAYER met1 ; + RECT 0 0 303.600 399.840 ; + LAYER met2 ; + RECT 0 0 303.600 399.840 ; + LAYER met3 ; + RECT 0 0 303.600 399.840 ; + LAYER met4 ; + RECT 0 0 303.600 399.840 ; + END +END fakeram_48x256_1rw + +END LIBRARY diff --git a/designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x1024_1rw.lef b/designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x1024_1rw.lef new file mode 100644 index 0000000..900f8c9 --- /dev/null +++ b/designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x1024_1rw.lef @@ -0,0 +1,1983 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_64x1024_1rw + FOREIGN fakeram_64x1024_1rw 0 0 ; + SYMMETRY X Y R90 ; + SIZE 559.820 BY 655.520 ; + CLASS BLOCK ; + PIN rw0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 3.930 0.900 4.230 ; + END + END rw0_wmask_in[0] + PIN rw0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 20.930 0.900 21.230 ; + END + END rw0_wmask_in[1] + PIN rw0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 37.930 0.900 38.230 ; + END + END rw0_wmask_in[2] + PIN rw0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 54.930 0.900 55.230 ; + END + END rw0_wmask_in[3] + PIN rw0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 71.930 0.900 72.230 ; + END + END rw0_wmask_in[4] + PIN rw0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 88.930 0.900 89.230 ; + END + END rw0_wmask_in[5] + PIN rw0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 105.930 0.900 106.230 ; + END + END rw0_wmask_in[6] + PIN rw0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 122.930 0.900 123.230 ; + END + END rw0_wmask_in[7] + PIN rw0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 139.930 0.900 140.230 ; + END + END rw0_wmask_in[8] + PIN rw0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 156.930 0.900 157.230 ; + END + END rw0_wmask_in[9] + PIN rw0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 173.930 0.900 174.230 ; + END + END rw0_wmask_in[10] + PIN rw0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 190.930 0.900 191.230 ; + END + END rw0_wmask_in[11] + PIN rw0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 207.930 0.900 208.230 ; + END + END rw0_wmask_in[12] + PIN rw0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 224.930 0.900 225.230 ; + END + END rw0_wmask_in[13] + PIN rw0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 241.930 0.900 242.230 ; + END + END rw0_wmask_in[14] + PIN rw0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 258.930 0.900 259.230 ; + END + END rw0_wmask_in[15] + PIN rw0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 3.930 559.820 4.230 ; + END + END rw0_wmask_in[16] + PIN rw0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 20.930 559.820 21.230 ; + END + END rw0_wmask_in[17] + PIN rw0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 37.930 559.820 38.230 ; + END + END rw0_wmask_in[18] + PIN rw0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 54.930 559.820 55.230 ; + END + END rw0_wmask_in[19] + PIN rw0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 71.930 559.820 72.230 ; + END + END rw0_wmask_in[20] + PIN rw0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 88.930 559.820 89.230 ; + END + END rw0_wmask_in[21] + PIN rw0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 105.930 559.820 106.230 ; + END + END rw0_wmask_in[22] + PIN rw0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 122.930 559.820 123.230 ; + END + END rw0_wmask_in[23] + PIN rw0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 139.930 559.820 140.230 ; + END + END rw0_wmask_in[24] + PIN rw0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 156.930 559.820 157.230 ; + END + END rw0_wmask_in[25] + PIN rw0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 173.930 559.820 174.230 ; + END + END rw0_wmask_in[26] + PIN rw0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 190.930 559.820 191.230 ; + END + END rw0_wmask_in[27] + PIN rw0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 207.930 559.820 208.230 ; + END + END rw0_wmask_in[28] + PIN rw0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 224.930 559.820 225.230 ; + END + END rw0_wmask_in[29] + PIN rw0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 241.930 559.820 242.230 ; + END + END rw0_wmask_in[30] + PIN rw0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 258.930 559.820 259.230 ; + END + END rw0_wmask_in[31] + PIN rw0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 2.690 655.100 2.830 655.520 ; + END + END rw0_wmask_in[32] + PIN rw0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 10.510 655.100 10.650 655.520 ; + END + END rw0_wmask_in[33] + PIN rw0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 18.330 655.100 18.470 655.520 ; + END + END rw0_wmask_in[34] + PIN rw0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 26.150 655.100 26.290 655.520 ; + END + END rw0_wmask_in[35] + PIN rw0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 33.970 655.100 34.110 655.520 ; + END + END rw0_wmask_in[36] + PIN rw0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 41.790 655.100 41.930 655.520 ; + END + END rw0_wmask_in[37] + PIN rw0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 49.610 655.100 49.750 655.520 ; + END + END rw0_wmask_in[38] + PIN rw0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 57.430 655.100 57.570 655.520 ; + END + END rw0_wmask_in[39] + PIN rw0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 65.250 655.100 65.390 655.520 ; + END + END rw0_wmask_in[40] + PIN rw0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 73.070 655.100 73.210 655.520 ; + END + END rw0_wmask_in[41] + PIN rw0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 80.890 655.100 81.030 655.520 ; + END + END rw0_wmask_in[42] + PIN rw0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 88.710 655.100 88.850 655.520 ; + END + END rw0_wmask_in[43] + PIN rw0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 96.530 655.100 96.670 655.520 ; + END + END rw0_wmask_in[44] + PIN rw0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 104.350 655.100 104.490 655.520 ; + END + END rw0_wmask_in[45] + PIN rw0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 112.170 655.100 112.310 655.520 ; + END + END rw0_wmask_in[46] + PIN rw0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 119.990 655.100 120.130 655.520 ; + END + END rw0_wmask_in[47] + PIN rw0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 127.810 655.100 127.950 655.520 ; + END + END rw0_wmask_in[48] + PIN rw0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 135.630 655.100 135.770 655.520 ; + END + END rw0_wmask_in[49] + PIN rw0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 143.450 655.100 143.590 655.520 ; + END + END rw0_wmask_in[50] + PIN rw0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 151.270 655.100 151.410 655.520 ; + END + END rw0_wmask_in[51] + PIN rw0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 159.090 655.100 159.230 655.520 ; + END + END rw0_wmask_in[52] + PIN rw0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 166.910 655.100 167.050 655.520 ; + END + END rw0_wmask_in[53] + PIN rw0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 174.730 655.100 174.870 655.520 ; + END + END rw0_wmask_in[54] + PIN rw0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 182.550 655.100 182.690 655.520 ; + END + END rw0_wmask_in[55] + PIN rw0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 190.370 655.100 190.510 655.520 ; + END + END rw0_wmask_in[56] + PIN rw0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 198.190 655.100 198.330 655.520 ; + END + END rw0_wmask_in[57] + PIN rw0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 206.010 655.100 206.150 655.520 ; + END + END rw0_wmask_in[58] + PIN rw0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 213.830 655.100 213.970 655.520 ; + END + END rw0_wmask_in[59] + PIN rw0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 221.650 655.100 221.790 655.520 ; + END + END rw0_wmask_in[60] + PIN rw0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 229.470 655.100 229.610 655.520 ; + END + END rw0_wmask_in[61] + PIN rw0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 237.290 655.100 237.430 655.520 ; + END + END rw0_wmask_in[62] + PIN rw0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 245.110 655.100 245.250 655.520 ; + END + END rw0_wmask_in[63] + PIN rw0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 275.930 0.900 276.230 ; + END + END rw0_wd_in[0] + PIN rw0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 292.930 0.900 293.230 ; + END + END rw0_wd_in[1] + PIN rw0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 309.930 0.900 310.230 ; + END + END rw0_wd_in[2] + PIN rw0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 326.930 0.900 327.230 ; + END + END rw0_wd_in[3] + PIN rw0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 343.930 0.900 344.230 ; + END + END rw0_wd_in[4] + PIN rw0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 360.930 0.900 361.230 ; + END + END rw0_wd_in[5] + PIN rw0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 377.930 0.900 378.230 ; + END + END rw0_wd_in[6] + PIN rw0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 394.930 0.900 395.230 ; + END + END rw0_wd_in[7] + PIN rw0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 411.930 0.900 412.230 ; + END + END rw0_wd_in[8] + PIN rw0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 428.930 0.900 429.230 ; + END + END rw0_wd_in[9] + PIN rw0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 445.930 0.900 446.230 ; + END + END rw0_wd_in[10] + PIN rw0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 462.930 0.900 463.230 ; + END + END rw0_wd_in[11] + PIN rw0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 479.930 0.900 480.230 ; + END + END rw0_wd_in[12] + PIN rw0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 496.930 0.900 497.230 ; + END + END rw0_wd_in[13] + PIN rw0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 513.930 0.900 514.230 ; + END + END rw0_wd_in[14] + PIN rw0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 530.930 0.900 531.230 ; + END + END rw0_wd_in[15] + PIN rw0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 275.930 559.820 276.230 ; + END + END rw0_wd_in[16] + PIN rw0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 292.930 559.820 293.230 ; + END + END rw0_wd_in[17] + PIN rw0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 309.930 559.820 310.230 ; + END + END rw0_wd_in[18] + PIN rw0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 326.930 559.820 327.230 ; + END + END rw0_wd_in[19] + PIN rw0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 343.930 559.820 344.230 ; + END + END rw0_wd_in[20] + PIN rw0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 360.930 559.820 361.230 ; + END + END rw0_wd_in[21] + PIN rw0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 377.930 559.820 378.230 ; + END + END rw0_wd_in[22] + PIN rw0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 394.930 559.820 395.230 ; + END + END rw0_wd_in[23] + PIN rw0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 411.930 559.820 412.230 ; + END + END rw0_wd_in[24] + PIN rw0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 428.930 559.820 429.230 ; + END + END rw0_wd_in[25] + PIN rw0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 445.930 559.820 446.230 ; + END + END rw0_wd_in[26] + PIN rw0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 462.930 559.820 463.230 ; + END + END rw0_wd_in[27] + PIN rw0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 479.930 559.820 480.230 ; + END + END rw0_wd_in[28] + PIN rw0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 496.930 559.820 497.230 ; + END + END rw0_wd_in[29] + PIN rw0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 513.930 559.820 514.230 ; + END + END rw0_wd_in[30] + PIN rw0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 530.930 559.820 531.230 ; + END + END rw0_wd_in[31] + PIN rw0_wd_in[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 2.690 0.000 2.830 0.420 ; + END + END rw0_wd_in[32] + PIN rw0_wd_in[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 10.970 0.000 11.110 0.420 ; + END + END rw0_wd_in[33] + PIN rw0_wd_in[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 19.250 0.000 19.390 0.420 ; + END + END rw0_wd_in[34] + PIN rw0_wd_in[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 27.530 0.000 27.670 0.420 ; + END + END rw0_wd_in[35] + PIN rw0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 35.810 0.000 35.950 0.420 ; + END + END rw0_wd_in[36] + PIN rw0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 44.090 0.000 44.230 0.420 ; + END + END rw0_wd_in[37] + PIN rw0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 52.370 0.000 52.510 0.420 ; + END + END rw0_wd_in[38] + PIN rw0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 60.650 0.000 60.790 0.420 ; + END + END rw0_wd_in[39] + PIN rw0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 68.930 0.000 69.070 0.420 ; + END + END rw0_wd_in[40] + PIN rw0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 77.210 0.000 77.350 0.420 ; + END + END rw0_wd_in[41] + PIN rw0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 85.490 0.000 85.630 0.420 ; + END + END rw0_wd_in[42] + PIN rw0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 93.770 0.000 93.910 0.420 ; + END + END rw0_wd_in[43] + PIN rw0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 102.050 0.000 102.190 0.420 ; + END + END rw0_wd_in[44] + PIN rw0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 110.330 0.000 110.470 0.420 ; + END + END rw0_wd_in[45] + PIN rw0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 118.610 0.000 118.750 0.420 ; + END + END rw0_wd_in[46] + PIN rw0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 126.890 0.000 127.030 0.420 ; + END + END rw0_wd_in[47] + PIN rw0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 135.170 0.000 135.310 0.420 ; + END + END rw0_wd_in[48] + PIN rw0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 143.450 0.000 143.590 0.420 ; + END + END rw0_wd_in[49] + PIN rw0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 151.730 0.000 151.870 0.420 ; + END + END rw0_wd_in[50] + PIN rw0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 160.010 0.000 160.150 0.420 ; + END + END rw0_wd_in[51] + PIN rw0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 168.290 0.000 168.430 0.420 ; + END + END rw0_wd_in[52] + PIN rw0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 176.570 0.000 176.710 0.420 ; + END + END rw0_wd_in[53] + PIN rw0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 184.850 0.000 184.990 0.420 ; + END + END rw0_wd_in[54] + PIN rw0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 193.130 0.000 193.270 0.420 ; + END + END rw0_wd_in[55] + PIN rw0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 201.410 0.000 201.550 0.420 ; + END + END rw0_wd_in[56] + PIN rw0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 209.690 0.000 209.830 0.420 ; + END + END rw0_wd_in[57] + PIN rw0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 217.970 0.000 218.110 0.420 ; + END + END rw0_wd_in[58] + PIN rw0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 226.250 0.000 226.390 0.420 ; + END + END rw0_wd_in[59] + PIN rw0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 234.530 0.000 234.670 0.420 ; + END + END rw0_wd_in[60] + PIN rw0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 242.810 0.000 242.950 0.420 ; + END + END rw0_wd_in[61] + PIN rw0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 251.090 0.000 251.230 0.420 ; + END + END rw0_wd_in[62] + PIN rw0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 259.370 0.000 259.510 0.420 ; + END + END rw0_wd_in[63] + PIN rw0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 267.650 0.000 267.790 0.420 ; + END + END rw0_rd_out[0] + PIN rw0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 275.930 0.000 276.070 0.420 ; + END + END rw0_rd_out[1] + PIN rw0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 284.210 0.000 284.350 0.420 ; + END + END rw0_rd_out[2] + PIN rw0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 292.490 0.000 292.630 0.420 ; + END + END rw0_rd_out[3] + PIN rw0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 300.770 0.000 300.910 0.420 ; + END + END rw0_rd_out[4] + PIN rw0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 309.050 0.000 309.190 0.420 ; + END + END rw0_rd_out[5] + PIN rw0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 317.330 0.000 317.470 0.420 ; + END + END rw0_rd_out[6] + PIN rw0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 325.610 0.000 325.750 0.420 ; + END + END rw0_rd_out[7] + PIN rw0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 333.890 0.000 334.030 0.420 ; + END + END rw0_rd_out[8] + PIN rw0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 342.170 0.000 342.310 0.420 ; + END + END rw0_rd_out[9] + PIN rw0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 350.450 0.000 350.590 0.420 ; + END + END rw0_rd_out[10] + PIN rw0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 358.730 0.000 358.870 0.420 ; + END + END rw0_rd_out[11] + PIN rw0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 367.010 0.000 367.150 0.420 ; + END + END rw0_rd_out[12] + PIN rw0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 375.290 0.000 375.430 0.420 ; + END + END rw0_rd_out[13] + PIN rw0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 383.570 0.000 383.710 0.420 ; + END + END rw0_rd_out[14] + PIN rw0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 391.850 0.000 391.990 0.420 ; + END + END rw0_rd_out[15] + PIN rw0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 400.130 0.000 400.270 0.420 ; + END + END rw0_rd_out[16] + PIN rw0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 408.410 0.000 408.550 0.420 ; + END + END rw0_rd_out[17] + PIN rw0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 416.690 0.000 416.830 0.420 ; + END + END rw0_rd_out[18] + PIN rw0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 424.970 0.000 425.110 0.420 ; + END + END rw0_rd_out[19] + PIN rw0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 433.250 0.000 433.390 0.420 ; + END + END rw0_rd_out[20] + PIN rw0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 441.530 0.000 441.670 0.420 ; + END + END rw0_rd_out[21] + PIN rw0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 449.810 0.000 449.950 0.420 ; + END + END rw0_rd_out[22] + PIN rw0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 458.090 0.000 458.230 0.420 ; + END + END rw0_rd_out[23] + PIN rw0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 466.370 0.000 466.510 0.420 ; + END + END rw0_rd_out[24] + PIN rw0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 474.650 0.000 474.790 0.420 ; + END + END rw0_rd_out[25] + PIN rw0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 482.930 0.000 483.070 0.420 ; + END + END rw0_rd_out[26] + PIN rw0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 491.210 0.000 491.350 0.420 ; + END + END rw0_rd_out[27] + PIN rw0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 499.490 0.000 499.630 0.420 ; + END + END rw0_rd_out[28] + PIN rw0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 507.770 0.000 507.910 0.420 ; + END + END rw0_rd_out[29] + PIN rw0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 516.050 0.000 516.190 0.420 ; + END + END rw0_rd_out[30] + PIN rw0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 524.330 0.000 524.470 0.420 ; + END + END rw0_rd_out[31] + PIN rw0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 252.930 655.100 253.070 655.520 ; + END + END rw0_rd_out[32] + PIN rw0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 260.750 655.100 260.890 655.520 ; + END + END rw0_rd_out[33] + PIN rw0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 268.570 655.100 268.710 655.520 ; + END + END rw0_rd_out[34] + PIN rw0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 276.390 655.100 276.530 655.520 ; + END + END rw0_rd_out[35] + PIN rw0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 284.210 655.100 284.350 655.520 ; + END + END rw0_rd_out[36] + PIN rw0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 292.030 655.100 292.170 655.520 ; + END + END rw0_rd_out[37] + PIN rw0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 299.850 655.100 299.990 655.520 ; + END + END rw0_rd_out[38] + PIN rw0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 307.670 655.100 307.810 655.520 ; + END + END rw0_rd_out[39] + PIN rw0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 315.490 655.100 315.630 655.520 ; + END + END rw0_rd_out[40] + PIN rw0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 323.310 655.100 323.450 655.520 ; + END + END rw0_rd_out[41] + PIN rw0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 331.130 655.100 331.270 655.520 ; + END + END rw0_rd_out[42] + PIN rw0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 338.950 655.100 339.090 655.520 ; + END + END rw0_rd_out[43] + PIN rw0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 346.770 655.100 346.910 655.520 ; + END + END rw0_rd_out[44] + PIN rw0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 354.590 655.100 354.730 655.520 ; + END + END rw0_rd_out[45] + PIN rw0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 362.410 655.100 362.550 655.520 ; + END + END rw0_rd_out[46] + PIN rw0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 370.230 655.100 370.370 655.520 ; + END + END rw0_rd_out[47] + PIN rw0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 378.050 655.100 378.190 655.520 ; + END + END rw0_rd_out[48] + PIN rw0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 385.870 655.100 386.010 655.520 ; + END + END rw0_rd_out[49] + PIN rw0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 393.690 655.100 393.830 655.520 ; + END + END rw0_rd_out[50] + PIN rw0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 401.510 655.100 401.650 655.520 ; + END + END rw0_rd_out[51] + PIN rw0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 409.330 655.100 409.470 655.520 ; + END + END rw0_rd_out[52] + PIN rw0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 417.150 655.100 417.290 655.520 ; + END + END rw0_rd_out[53] + PIN rw0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 424.970 655.100 425.110 655.520 ; + END + END rw0_rd_out[54] + PIN rw0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 432.790 655.100 432.930 655.520 ; + END + END rw0_rd_out[55] + PIN rw0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 440.610 655.100 440.750 655.520 ; + END + END rw0_rd_out[56] + PIN rw0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 448.430 655.100 448.570 655.520 ; + END + END rw0_rd_out[57] + PIN rw0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 456.250 655.100 456.390 655.520 ; + END + END rw0_rd_out[58] + PIN rw0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 464.070 655.100 464.210 655.520 ; + END + END rw0_rd_out[59] + PIN rw0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 471.890 655.100 472.030 655.520 ; + END + END rw0_rd_out[60] + PIN rw0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 479.710 655.100 479.850 655.520 ; + END + END rw0_rd_out[61] + PIN rw0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 487.530 655.100 487.670 655.520 ; + END + END rw0_rd_out[62] + PIN rw0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 495.350 655.100 495.490 655.520 ; + END + END rw0_rd_out[63] + PIN rw0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 547.930 0.900 548.230 ; + END + END rw0_addr_in[0] + PIN rw0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 564.930 0.900 565.230 ; + END + END rw0_addr_in[1] + PIN rw0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 581.930 0.900 582.230 ; + END + END rw0_addr_in[2] + PIN rw0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 598.930 0.900 599.230 ; + END + END rw0_addr_in[3] + PIN rw0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 615.930 0.900 616.230 ; + END + END rw0_addr_in[4] + PIN rw0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 547.930 559.820 548.230 ; + END + END rw0_addr_in[5] + PIN rw0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 564.930 559.820 565.230 ; + END + END rw0_addr_in[6] + PIN rw0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 581.930 559.820 582.230 ; + END + END rw0_addr_in[7] + PIN rw0_addr_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 598.930 559.820 599.230 ; + END + END rw0_addr_in[8] + PIN rw0_addr_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 558.920 615.930 559.820 616.230 ; + END + END rw0_addr_in[9] + PIN rw0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 503.170 655.100 503.310 655.520 ; + END + END rw0_we_in + PIN rw0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 510.990 655.100 511.130 655.520 ; + END + END rw0_ce_in + PIN rw0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 518.810 655.100 518.950 655.520 ; + END + END rw0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met4 ; + RECT 2.160 4.080 3.360 651.440 ; + RECT 13.040 4.080 14.240 651.440 ; + RECT 23.920 4.080 25.120 651.440 ; + RECT 34.800 4.080 36.000 651.440 ; + RECT 45.680 4.080 46.880 651.440 ; + RECT 56.560 4.080 57.760 651.440 ; + RECT 67.440 4.080 68.640 651.440 ; + RECT 78.320 4.080 79.520 651.440 ; + RECT 89.200 4.080 90.400 651.440 ; + RECT 100.080 4.080 101.280 651.440 ; + RECT 110.960 4.080 112.160 651.440 ; + RECT 121.840 4.080 123.040 651.440 ; + RECT 132.720 4.080 133.920 651.440 ; + RECT 143.600 4.080 144.800 651.440 ; + RECT 154.480 4.080 155.680 651.440 ; + RECT 165.360 4.080 166.560 651.440 ; + RECT 176.240 4.080 177.440 651.440 ; + RECT 187.120 4.080 188.320 651.440 ; + RECT 198.000 4.080 199.200 651.440 ; + RECT 208.880 4.080 210.080 651.440 ; + RECT 219.760 4.080 220.960 651.440 ; + RECT 230.640 4.080 231.840 651.440 ; + RECT 241.520 4.080 242.720 651.440 ; + RECT 252.400 4.080 253.600 651.440 ; + RECT 263.280 4.080 264.480 651.440 ; + RECT 274.160 4.080 275.360 651.440 ; + RECT 285.040 4.080 286.240 651.440 ; + RECT 295.920 4.080 297.120 651.440 ; + RECT 306.800 4.080 308.000 651.440 ; + RECT 317.680 4.080 318.880 651.440 ; + RECT 328.560 4.080 329.760 651.440 ; + RECT 339.440 4.080 340.640 651.440 ; + RECT 350.320 4.080 351.520 651.440 ; + RECT 361.200 4.080 362.400 651.440 ; + RECT 372.080 4.080 373.280 651.440 ; + RECT 382.960 4.080 384.160 651.440 ; + RECT 393.840 4.080 395.040 651.440 ; + RECT 404.720 4.080 405.920 651.440 ; + RECT 415.600 4.080 416.800 651.440 ; + RECT 426.480 4.080 427.680 651.440 ; + RECT 437.360 4.080 438.560 651.440 ; + RECT 448.240 4.080 449.440 651.440 ; + RECT 459.120 4.080 460.320 651.440 ; + RECT 470.000 4.080 471.200 651.440 ; + RECT 480.880 4.080 482.080 651.440 ; + RECT 491.760 4.080 492.960 651.440 ; + RECT 502.640 4.080 503.840 651.440 ; + RECT 513.520 4.080 514.720 651.440 ; + RECT 524.400 4.080 525.600 651.440 ; + RECT 535.280 4.080 536.480 651.440 ; + RECT 546.160 4.080 547.360 651.440 ; + RECT 557.040 4.080 558.240 651.440 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met4 ; + RECT 2.160 4.080 3.360 651.440 ; + RECT 13.040 4.080 14.240 651.440 ; + RECT 23.920 4.080 25.120 651.440 ; + RECT 34.800 4.080 36.000 651.440 ; + RECT 45.680 4.080 46.880 651.440 ; + RECT 56.560 4.080 57.760 651.440 ; + RECT 67.440 4.080 68.640 651.440 ; + RECT 78.320 4.080 79.520 651.440 ; + RECT 89.200 4.080 90.400 651.440 ; + RECT 100.080 4.080 101.280 651.440 ; + RECT 110.960 4.080 112.160 651.440 ; + RECT 121.840 4.080 123.040 651.440 ; + RECT 132.720 4.080 133.920 651.440 ; + RECT 143.600 4.080 144.800 651.440 ; + RECT 154.480 4.080 155.680 651.440 ; + RECT 165.360 4.080 166.560 651.440 ; + RECT 176.240 4.080 177.440 651.440 ; + RECT 187.120 4.080 188.320 651.440 ; + RECT 198.000 4.080 199.200 651.440 ; + RECT 208.880 4.080 210.080 651.440 ; + RECT 219.760 4.080 220.960 651.440 ; + RECT 230.640 4.080 231.840 651.440 ; + RECT 241.520 4.080 242.720 651.440 ; + RECT 252.400 4.080 253.600 651.440 ; + RECT 263.280 4.080 264.480 651.440 ; + RECT 274.160 4.080 275.360 651.440 ; + RECT 285.040 4.080 286.240 651.440 ; + RECT 295.920 4.080 297.120 651.440 ; + RECT 306.800 4.080 308.000 651.440 ; + RECT 317.680 4.080 318.880 651.440 ; + RECT 328.560 4.080 329.760 651.440 ; + RECT 339.440 4.080 340.640 651.440 ; + RECT 350.320 4.080 351.520 651.440 ; + RECT 361.200 4.080 362.400 651.440 ; + RECT 372.080 4.080 373.280 651.440 ; + RECT 382.960 4.080 384.160 651.440 ; + RECT 393.840 4.080 395.040 651.440 ; + RECT 404.720 4.080 405.920 651.440 ; + RECT 415.600 4.080 416.800 651.440 ; + RECT 426.480 4.080 427.680 651.440 ; + RECT 437.360 4.080 438.560 651.440 ; + RECT 448.240 4.080 449.440 651.440 ; + RECT 459.120 4.080 460.320 651.440 ; + RECT 470.000 4.080 471.200 651.440 ; + RECT 480.880 4.080 482.080 651.440 ; + RECT 491.760 4.080 492.960 651.440 ; + RECT 502.640 4.080 503.840 651.440 ; + RECT 513.520 4.080 514.720 651.440 ; + RECT 524.400 4.080 525.600 651.440 ; + RECT 535.280 4.080 536.480 651.440 ; + RECT 546.160 4.080 547.360 651.440 ; + RECT 557.040 4.080 558.240 651.440 ; + END + END VDD + OBS + LAYER met1 ; + RECT 0 0 559.820 655.520 ; + LAYER met2 ; + RECT 0 0 559.820 655.520 ; + LAYER met3 ; + RECT 0 0 559.820 655.520 ; + LAYER met4 ; + RECT 0 0 559.820 655.520 ; + END +END fakeram_64x1024_1rw + +END LIBRARY diff --git a/designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x2048_1rw.lef b/designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x2048_1rw.lef new file mode 100644 index 0000000..ae933ba --- /dev/null +++ b/designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x2048_1rw.lef @@ -0,0 +1,2080 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_64x2048_1rw + FOREIGN fakeram_64x2048_1rw 0 0 ; + SYMMETRY X Y R90 ; + SIZE 1046.040 BY 652.800 ; + CLASS BLOCK ; + PIN rw0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 3.930 0.900 4.230 ; + END + END rw0_wmask_in[0] + PIN rw0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 20.250 0.900 20.550 ; + END + END rw0_wmask_in[1] + PIN rw0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 36.570 0.900 36.870 ; + END + END rw0_wmask_in[2] + PIN rw0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 52.890 0.900 53.190 ; + END + END rw0_wmask_in[3] + PIN rw0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 69.210 0.900 69.510 ; + END + END rw0_wmask_in[4] + PIN rw0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 85.530 0.900 85.830 ; + END + END rw0_wmask_in[5] + PIN rw0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 101.850 0.900 102.150 ; + END + END rw0_wmask_in[6] + PIN rw0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 118.170 0.900 118.470 ; + END + END rw0_wmask_in[7] + PIN rw0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 134.490 0.900 134.790 ; + END + END rw0_wmask_in[8] + PIN rw0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 150.810 0.900 151.110 ; + END + END rw0_wmask_in[9] + PIN rw0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 167.130 0.900 167.430 ; + END + END rw0_wmask_in[10] + PIN rw0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 183.450 0.900 183.750 ; + END + END rw0_wmask_in[11] + PIN rw0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 199.770 0.900 200.070 ; + END + END rw0_wmask_in[12] + PIN rw0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 216.090 0.900 216.390 ; + END + END rw0_wmask_in[13] + PIN rw0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 232.410 0.900 232.710 ; + END + END rw0_wmask_in[14] + PIN rw0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 248.730 0.900 249.030 ; + END + END rw0_wmask_in[15] + PIN rw0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 3.930 1046.040 4.230 ; + END + END rw0_wmask_in[16] + PIN rw0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 20.250 1046.040 20.550 ; + END + END rw0_wmask_in[17] + PIN rw0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 36.570 1046.040 36.870 ; + END + END rw0_wmask_in[18] + PIN rw0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 52.890 1046.040 53.190 ; + END + END rw0_wmask_in[19] + PIN rw0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 69.210 1046.040 69.510 ; + END + END rw0_wmask_in[20] + PIN rw0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 85.530 1046.040 85.830 ; + END + END rw0_wmask_in[21] + PIN rw0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 101.850 1046.040 102.150 ; + END + END rw0_wmask_in[22] + PIN rw0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 118.170 1046.040 118.470 ; + END + END rw0_wmask_in[23] + PIN rw0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 134.490 1046.040 134.790 ; + END + END rw0_wmask_in[24] + PIN rw0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 150.810 1046.040 151.110 ; + END + END rw0_wmask_in[25] + PIN rw0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 167.130 1046.040 167.430 ; + END + END rw0_wmask_in[26] + PIN rw0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 183.450 1046.040 183.750 ; + END + END rw0_wmask_in[27] + PIN rw0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 199.770 1046.040 200.070 ; + END + END rw0_wmask_in[28] + PIN rw0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 216.090 1046.040 216.390 ; + END + END rw0_wmask_in[29] + PIN rw0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 232.410 1046.040 232.710 ; + END + END rw0_wmask_in[30] + PIN rw0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 248.730 1046.040 249.030 ; + END + END rw0_wmask_in[31] + PIN rw0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 2.690 652.380 2.830 652.800 ; + END + END rw0_wmask_in[32] + PIN rw0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 17.870 652.380 18.010 652.800 ; + END + END rw0_wmask_in[33] + PIN rw0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 33.050 652.380 33.190 652.800 ; + END + END rw0_wmask_in[34] + PIN rw0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 48.230 652.380 48.370 652.800 ; + END + END rw0_wmask_in[35] + PIN rw0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 63.410 652.380 63.550 652.800 ; + END + END rw0_wmask_in[36] + PIN rw0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 78.590 652.380 78.730 652.800 ; + END + END rw0_wmask_in[37] + PIN rw0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 93.770 652.380 93.910 652.800 ; + END + END rw0_wmask_in[38] + PIN rw0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 108.950 652.380 109.090 652.800 ; + END + END rw0_wmask_in[39] + PIN rw0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 124.130 652.380 124.270 652.800 ; + END + END rw0_wmask_in[40] + PIN rw0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 139.310 652.380 139.450 652.800 ; + END + END rw0_wmask_in[41] + PIN rw0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 154.490 652.380 154.630 652.800 ; + END + END rw0_wmask_in[42] + PIN rw0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 169.670 652.380 169.810 652.800 ; + END + END rw0_wmask_in[43] + PIN rw0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 184.850 652.380 184.990 652.800 ; + END + END rw0_wmask_in[44] + PIN rw0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 200.030 652.380 200.170 652.800 ; + END + END rw0_wmask_in[45] + PIN rw0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 215.210 652.380 215.350 652.800 ; + END + END rw0_wmask_in[46] + PIN rw0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 230.390 652.380 230.530 652.800 ; + END + END rw0_wmask_in[47] + PIN rw0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 245.570 652.380 245.710 652.800 ; + END + END rw0_wmask_in[48] + PIN rw0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 260.750 652.380 260.890 652.800 ; + END + END rw0_wmask_in[49] + PIN rw0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 275.930 652.380 276.070 652.800 ; + END + END rw0_wmask_in[50] + PIN rw0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 291.110 652.380 291.250 652.800 ; + END + END rw0_wmask_in[51] + PIN rw0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 306.290 652.380 306.430 652.800 ; + END + END rw0_wmask_in[52] + PIN rw0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 321.470 652.380 321.610 652.800 ; + END + END rw0_wmask_in[53] + PIN rw0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 336.650 652.380 336.790 652.800 ; + END + END rw0_wmask_in[54] + PIN rw0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 351.830 652.380 351.970 652.800 ; + END + END rw0_wmask_in[55] + PIN rw0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 367.010 652.380 367.150 652.800 ; + END + END rw0_wmask_in[56] + PIN rw0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 382.190 652.380 382.330 652.800 ; + END + END rw0_wmask_in[57] + PIN rw0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 397.370 652.380 397.510 652.800 ; + END + END rw0_wmask_in[58] + PIN rw0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 412.550 652.380 412.690 652.800 ; + END + END rw0_wmask_in[59] + PIN rw0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 427.730 652.380 427.870 652.800 ; + END + END rw0_wmask_in[60] + PIN rw0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 442.910 652.380 443.050 652.800 ; + END + END rw0_wmask_in[61] + PIN rw0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 458.090 652.380 458.230 652.800 ; + END + END rw0_wmask_in[62] + PIN rw0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 473.270 652.380 473.410 652.800 ; + END + END rw0_wmask_in[63] + PIN rw0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 265.050 0.900 265.350 ; + END + END rw0_wd_in[0] + PIN rw0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 281.370 0.900 281.670 ; + END + END rw0_wd_in[1] + PIN rw0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 297.690 0.900 297.990 ; + END + END rw0_wd_in[2] + PIN rw0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 314.010 0.900 314.310 ; + END + END rw0_wd_in[3] + PIN rw0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 330.330 0.900 330.630 ; + END + END rw0_wd_in[4] + PIN rw0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 346.650 0.900 346.950 ; + END + END rw0_wd_in[5] + PIN rw0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 362.970 0.900 363.270 ; + END + END rw0_wd_in[6] + PIN rw0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 379.290 0.900 379.590 ; + END + END rw0_wd_in[7] + PIN rw0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 395.610 0.900 395.910 ; + END + END rw0_wd_in[8] + PIN rw0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 411.930 0.900 412.230 ; + END + END rw0_wd_in[9] + PIN rw0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 428.250 0.900 428.550 ; + END + END rw0_wd_in[10] + PIN rw0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 444.570 0.900 444.870 ; + END + END rw0_wd_in[11] + PIN rw0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 460.890 0.900 461.190 ; + END + END rw0_wd_in[12] + PIN rw0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 477.210 0.900 477.510 ; + END + END rw0_wd_in[13] + PIN rw0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 493.530 0.900 493.830 ; + END + END rw0_wd_in[14] + PIN rw0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 509.850 0.900 510.150 ; + END + END rw0_wd_in[15] + PIN rw0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 265.050 1046.040 265.350 ; + END + END rw0_wd_in[16] + PIN rw0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 281.370 1046.040 281.670 ; + END + END rw0_wd_in[17] + PIN rw0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 297.690 1046.040 297.990 ; + END + END rw0_wd_in[18] + PIN rw0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 314.010 1046.040 314.310 ; + END + END rw0_wd_in[19] + PIN rw0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 330.330 1046.040 330.630 ; + END + END rw0_wd_in[20] + PIN rw0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 346.650 1046.040 346.950 ; + END + END rw0_wd_in[21] + PIN rw0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 362.970 1046.040 363.270 ; + END + END rw0_wd_in[22] + PIN rw0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 379.290 1046.040 379.590 ; + END + END rw0_wd_in[23] + PIN rw0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 395.610 1046.040 395.910 ; + END + END rw0_wd_in[24] + PIN rw0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 411.930 1046.040 412.230 ; + END + END rw0_wd_in[25] + PIN rw0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 428.250 1046.040 428.550 ; + END + END rw0_wd_in[26] + PIN rw0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 444.570 1046.040 444.870 ; + END + END rw0_wd_in[27] + PIN rw0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 460.890 1046.040 461.190 ; + END + END rw0_wd_in[28] + PIN rw0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 477.210 1046.040 477.510 ; + END + END rw0_wd_in[29] + PIN rw0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 493.530 1046.040 493.830 ; + END + END rw0_wd_in[30] + PIN rw0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 509.850 1046.040 510.150 ; + END + END rw0_wd_in[31] + PIN rw0_wd_in[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 2.690 0.000 2.830 0.420 ; + END + END rw0_wd_in[32] + PIN rw0_wd_in[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 18.790 0.000 18.930 0.420 ; + END + END rw0_wd_in[33] + PIN rw0_wd_in[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 34.890 0.000 35.030 0.420 ; + END + END rw0_wd_in[34] + PIN rw0_wd_in[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 50.990 0.000 51.130 0.420 ; + END + END rw0_wd_in[35] + PIN rw0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 67.090 0.000 67.230 0.420 ; + END + END rw0_wd_in[36] + PIN rw0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 83.190 0.000 83.330 0.420 ; + END + END rw0_wd_in[37] + PIN rw0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 99.290 0.000 99.430 0.420 ; + END + END rw0_wd_in[38] + PIN rw0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 115.390 0.000 115.530 0.420 ; + END + END rw0_wd_in[39] + PIN rw0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 131.490 0.000 131.630 0.420 ; + END + END rw0_wd_in[40] + PIN rw0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 147.590 0.000 147.730 0.420 ; + END + END rw0_wd_in[41] + PIN rw0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 163.690 0.000 163.830 0.420 ; + END + END rw0_wd_in[42] + PIN rw0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 179.790 0.000 179.930 0.420 ; + END + END rw0_wd_in[43] + PIN rw0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 195.890 0.000 196.030 0.420 ; + END + END rw0_wd_in[44] + PIN rw0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 211.990 0.000 212.130 0.420 ; + END + END rw0_wd_in[45] + PIN rw0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 228.090 0.000 228.230 0.420 ; + END + END rw0_wd_in[46] + PIN rw0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 244.190 0.000 244.330 0.420 ; + END + END rw0_wd_in[47] + PIN rw0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 260.290 0.000 260.430 0.420 ; + END + END rw0_wd_in[48] + PIN rw0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 276.390 0.000 276.530 0.420 ; + END + END rw0_wd_in[49] + PIN rw0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 292.490 0.000 292.630 0.420 ; + END + END rw0_wd_in[50] + PIN rw0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 308.590 0.000 308.730 0.420 ; + END + END rw0_wd_in[51] + PIN rw0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 324.690 0.000 324.830 0.420 ; + END + END rw0_wd_in[52] + PIN rw0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 340.790 0.000 340.930 0.420 ; + END + END rw0_wd_in[53] + PIN rw0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 356.890 0.000 357.030 0.420 ; + END + END rw0_wd_in[54] + PIN rw0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 372.990 0.000 373.130 0.420 ; + END + END rw0_wd_in[55] + PIN rw0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 389.090 0.000 389.230 0.420 ; + END + END rw0_wd_in[56] + PIN rw0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 405.190 0.000 405.330 0.420 ; + END + END rw0_wd_in[57] + PIN rw0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 421.290 0.000 421.430 0.420 ; + END + END rw0_wd_in[58] + PIN rw0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 437.390 0.000 437.530 0.420 ; + END + END rw0_wd_in[59] + PIN rw0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 453.490 0.000 453.630 0.420 ; + END + END rw0_wd_in[60] + PIN rw0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 469.590 0.000 469.730 0.420 ; + END + END rw0_wd_in[61] + PIN rw0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 485.690 0.000 485.830 0.420 ; + END + END rw0_wd_in[62] + PIN rw0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 501.790 0.000 501.930 0.420 ; + END + END rw0_wd_in[63] + PIN rw0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 517.890 0.000 518.030 0.420 ; + END + END rw0_rd_out[0] + PIN rw0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 533.990 0.000 534.130 0.420 ; + END + END rw0_rd_out[1] + PIN rw0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 550.090 0.000 550.230 0.420 ; + END + END rw0_rd_out[2] + PIN rw0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 566.190 0.000 566.330 0.420 ; + END + END rw0_rd_out[3] + PIN rw0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 582.290 0.000 582.430 0.420 ; + END + END rw0_rd_out[4] + PIN rw0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 598.390 0.000 598.530 0.420 ; + END + END rw0_rd_out[5] + PIN rw0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 614.490 0.000 614.630 0.420 ; + END + END rw0_rd_out[6] + PIN rw0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 630.590 0.000 630.730 0.420 ; + END + END rw0_rd_out[7] + PIN rw0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 646.690 0.000 646.830 0.420 ; + END + END rw0_rd_out[8] + PIN rw0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 662.790 0.000 662.930 0.420 ; + END + END rw0_rd_out[9] + PIN rw0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 678.890 0.000 679.030 0.420 ; + END + END rw0_rd_out[10] + PIN rw0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 694.990 0.000 695.130 0.420 ; + END + END rw0_rd_out[11] + PIN rw0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 711.090 0.000 711.230 0.420 ; + END + END rw0_rd_out[12] + PIN rw0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 727.190 0.000 727.330 0.420 ; + END + END rw0_rd_out[13] + PIN rw0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 743.290 0.000 743.430 0.420 ; + END + END rw0_rd_out[14] + PIN rw0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 759.390 0.000 759.530 0.420 ; + END + END rw0_rd_out[15] + PIN rw0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 775.490 0.000 775.630 0.420 ; + END + END rw0_rd_out[16] + PIN rw0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 791.590 0.000 791.730 0.420 ; + END + END rw0_rd_out[17] + PIN rw0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 807.690 0.000 807.830 0.420 ; + END + END rw0_rd_out[18] + PIN rw0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 823.790 0.000 823.930 0.420 ; + END + END rw0_rd_out[19] + PIN rw0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 839.890 0.000 840.030 0.420 ; + END + END rw0_rd_out[20] + PIN rw0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 855.990 0.000 856.130 0.420 ; + END + END rw0_rd_out[21] + PIN rw0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 872.090 0.000 872.230 0.420 ; + END + END rw0_rd_out[22] + PIN rw0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 888.190 0.000 888.330 0.420 ; + END + END rw0_rd_out[23] + PIN rw0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 904.290 0.000 904.430 0.420 ; + END + END rw0_rd_out[24] + PIN rw0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 920.390 0.000 920.530 0.420 ; + END + END rw0_rd_out[25] + PIN rw0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 936.490 0.000 936.630 0.420 ; + END + END rw0_rd_out[26] + PIN rw0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 952.590 0.000 952.730 0.420 ; + END + END rw0_rd_out[27] + PIN rw0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 968.690 0.000 968.830 0.420 ; + END + END rw0_rd_out[28] + PIN rw0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 984.790 0.000 984.930 0.420 ; + END + END rw0_rd_out[29] + PIN rw0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 1000.890 0.000 1001.030 0.420 ; + END + END rw0_rd_out[30] + PIN rw0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 1016.990 0.000 1017.130 0.420 ; + END + END rw0_rd_out[31] + PIN rw0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 488.450 652.380 488.590 652.800 ; + END + END rw0_rd_out[32] + PIN rw0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 503.630 652.380 503.770 652.800 ; + END + END rw0_rd_out[33] + PIN rw0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 518.810 652.380 518.950 652.800 ; + END + END rw0_rd_out[34] + PIN rw0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 533.990 652.380 534.130 652.800 ; + END + END rw0_rd_out[35] + PIN rw0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 549.170 652.380 549.310 652.800 ; + END + END rw0_rd_out[36] + PIN rw0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 564.350 652.380 564.490 652.800 ; + END + END rw0_rd_out[37] + PIN rw0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 579.530 652.380 579.670 652.800 ; + END + END rw0_rd_out[38] + PIN rw0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 594.710 652.380 594.850 652.800 ; + END + END rw0_rd_out[39] + PIN rw0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 609.890 652.380 610.030 652.800 ; + END + END rw0_rd_out[40] + PIN rw0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 625.070 652.380 625.210 652.800 ; + END + END rw0_rd_out[41] + PIN rw0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 640.250 652.380 640.390 652.800 ; + END + END rw0_rd_out[42] + PIN rw0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 655.430 652.380 655.570 652.800 ; + END + END rw0_rd_out[43] + PIN rw0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 670.610 652.380 670.750 652.800 ; + END + END rw0_rd_out[44] + PIN rw0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 685.790 652.380 685.930 652.800 ; + END + END rw0_rd_out[45] + PIN rw0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 700.970 652.380 701.110 652.800 ; + END + END rw0_rd_out[46] + PIN rw0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 716.150 652.380 716.290 652.800 ; + END + END rw0_rd_out[47] + PIN rw0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 731.330 652.380 731.470 652.800 ; + END + END rw0_rd_out[48] + PIN rw0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 746.510 652.380 746.650 652.800 ; + END + END rw0_rd_out[49] + PIN rw0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 761.690 652.380 761.830 652.800 ; + END + END rw0_rd_out[50] + PIN rw0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 776.870 652.380 777.010 652.800 ; + END + END rw0_rd_out[51] + PIN rw0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 792.050 652.380 792.190 652.800 ; + END + END rw0_rd_out[52] + PIN rw0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 807.230 652.380 807.370 652.800 ; + END + END rw0_rd_out[53] + PIN rw0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 822.410 652.380 822.550 652.800 ; + END + END rw0_rd_out[54] + PIN rw0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 837.590 652.380 837.730 652.800 ; + END + END rw0_rd_out[55] + PIN rw0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 852.770 652.380 852.910 652.800 ; + END + END rw0_rd_out[56] + PIN rw0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 867.950 652.380 868.090 652.800 ; + END + END rw0_rd_out[57] + PIN rw0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 883.130 652.380 883.270 652.800 ; + END + END rw0_rd_out[58] + PIN rw0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 898.310 652.380 898.450 652.800 ; + END + END rw0_rd_out[59] + PIN rw0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 913.490 652.380 913.630 652.800 ; + END + END rw0_rd_out[60] + PIN rw0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 928.670 652.380 928.810 652.800 ; + END + END rw0_rd_out[61] + PIN rw0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 943.850 652.380 943.990 652.800 ; + END + END rw0_rd_out[62] + PIN rw0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 959.030 652.380 959.170 652.800 ; + END + END rw0_rd_out[63] + PIN rw0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 526.170 0.900 526.470 ; + END + END rw0_addr_in[0] + PIN rw0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 542.490 0.900 542.790 ; + END + END rw0_addr_in[1] + PIN rw0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 558.810 0.900 559.110 ; + END + END rw0_addr_in[2] + PIN rw0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 575.130 0.900 575.430 ; + END + END rw0_addr_in[3] + PIN rw0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 591.450 0.900 591.750 ; + END + END rw0_addr_in[4] + PIN rw0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 607.770 0.900 608.070 ; + END + END rw0_addr_in[5] + PIN rw0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 526.170 1046.040 526.470 ; + END + END rw0_addr_in[6] + PIN rw0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 542.490 1046.040 542.790 ; + END + END rw0_addr_in[7] + PIN rw0_addr_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 558.810 1046.040 559.110 ; + END + END rw0_addr_in[8] + PIN rw0_addr_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 575.130 1046.040 575.430 ; + END + END rw0_addr_in[9] + PIN rw0_addr_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1045.140 591.450 1046.040 591.750 ; + END + END rw0_addr_in[10] + PIN rw0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 974.210 652.380 974.350 652.800 ; + END + END rw0_we_in + PIN rw0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 989.390 652.380 989.530 652.800 ; + END + END rw0_ce_in + PIN rw0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 1004.570 652.380 1004.710 652.800 ; + END + END rw0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met4 ; + RECT 2.160 4.080 3.360 648.720 ; + RECT 13.040 4.080 14.240 648.720 ; + RECT 23.920 4.080 25.120 648.720 ; + RECT 34.800 4.080 36.000 648.720 ; + RECT 45.680 4.080 46.880 648.720 ; + RECT 56.560 4.080 57.760 648.720 ; + RECT 67.440 4.080 68.640 648.720 ; + RECT 78.320 4.080 79.520 648.720 ; + RECT 89.200 4.080 90.400 648.720 ; + RECT 100.080 4.080 101.280 648.720 ; + RECT 110.960 4.080 112.160 648.720 ; + RECT 121.840 4.080 123.040 648.720 ; + RECT 132.720 4.080 133.920 648.720 ; + RECT 143.600 4.080 144.800 648.720 ; + RECT 154.480 4.080 155.680 648.720 ; + RECT 165.360 4.080 166.560 648.720 ; + RECT 176.240 4.080 177.440 648.720 ; + RECT 187.120 4.080 188.320 648.720 ; + RECT 198.000 4.080 199.200 648.720 ; + RECT 208.880 4.080 210.080 648.720 ; + RECT 219.760 4.080 220.960 648.720 ; + RECT 230.640 4.080 231.840 648.720 ; + RECT 241.520 4.080 242.720 648.720 ; + RECT 252.400 4.080 253.600 648.720 ; + RECT 263.280 4.080 264.480 648.720 ; + RECT 274.160 4.080 275.360 648.720 ; + RECT 285.040 4.080 286.240 648.720 ; + RECT 295.920 4.080 297.120 648.720 ; + RECT 306.800 4.080 308.000 648.720 ; + RECT 317.680 4.080 318.880 648.720 ; + RECT 328.560 4.080 329.760 648.720 ; + RECT 339.440 4.080 340.640 648.720 ; + RECT 350.320 4.080 351.520 648.720 ; + RECT 361.200 4.080 362.400 648.720 ; + RECT 372.080 4.080 373.280 648.720 ; + RECT 382.960 4.080 384.160 648.720 ; + RECT 393.840 4.080 395.040 648.720 ; + RECT 404.720 4.080 405.920 648.720 ; + RECT 415.600 4.080 416.800 648.720 ; + RECT 426.480 4.080 427.680 648.720 ; + RECT 437.360 4.080 438.560 648.720 ; + RECT 448.240 4.080 449.440 648.720 ; + RECT 459.120 4.080 460.320 648.720 ; + RECT 470.000 4.080 471.200 648.720 ; + RECT 480.880 4.080 482.080 648.720 ; + RECT 491.760 4.080 492.960 648.720 ; + RECT 502.640 4.080 503.840 648.720 ; + RECT 513.520 4.080 514.720 648.720 ; + RECT 524.400 4.080 525.600 648.720 ; + RECT 535.280 4.080 536.480 648.720 ; + RECT 546.160 4.080 547.360 648.720 ; + RECT 557.040 4.080 558.240 648.720 ; + RECT 567.920 4.080 569.120 648.720 ; + RECT 578.800 4.080 580.000 648.720 ; + RECT 589.680 4.080 590.880 648.720 ; + RECT 600.560 4.080 601.760 648.720 ; + RECT 611.440 4.080 612.640 648.720 ; + RECT 622.320 4.080 623.520 648.720 ; + RECT 633.200 4.080 634.400 648.720 ; + RECT 644.080 4.080 645.280 648.720 ; + RECT 654.960 4.080 656.160 648.720 ; + RECT 665.840 4.080 667.040 648.720 ; + RECT 676.720 4.080 677.920 648.720 ; + RECT 687.600 4.080 688.800 648.720 ; + RECT 698.480 4.080 699.680 648.720 ; + RECT 709.360 4.080 710.560 648.720 ; + RECT 720.240 4.080 721.440 648.720 ; + RECT 731.120 4.080 732.320 648.720 ; + RECT 742.000 4.080 743.200 648.720 ; + RECT 752.880 4.080 754.080 648.720 ; + RECT 763.760 4.080 764.960 648.720 ; + RECT 774.640 4.080 775.840 648.720 ; + RECT 785.520 4.080 786.720 648.720 ; + RECT 796.400 4.080 797.600 648.720 ; + RECT 807.280 4.080 808.480 648.720 ; + RECT 818.160 4.080 819.360 648.720 ; + RECT 829.040 4.080 830.240 648.720 ; + RECT 839.920 4.080 841.120 648.720 ; + RECT 850.800 4.080 852.000 648.720 ; + RECT 861.680 4.080 862.880 648.720 ; + RECT 872.560 4.080 873.760 648.720 ; + RECT 883.440 4.080 884.640 648.720 ; + RECT 894.320 4.080 895.520 648.720 ; + RECT 905.200 4.080 906.400 648.720 ; + RECT 916.080 4.080 917.280 648.720 ; + RECT 926.960 4.080 928.160 648.720 ; + RECT 937.840 4.080 939.040 648.720 ; + RECT 948.720 4.080 949.920 648.720 ; + RECT 959.600 4.080 960.800 648.720 ; + RECT 970.480 4.080 971.680 648.720 ; + RECT 981.360 4.080 982.560 648.720 ; + RECT 992.240 4.080 993.440 648.720 ; + RECT 1003.120 4.080 1004.320 648.720 ; + RECT 1014.000 4.080 1015.200 648.720 ; + RECT 1024.880 4.080 1026.080 648.720 ; + RECT 1035.760 4.080 1036.960 648.720 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met4 ; + RECT 2.160 4.080 3.360 648.720 ; + RECT 13.040 4.080 14.240 648.720 ; + RECT 23.920 4.080 25.120 648.720 ; + RECT 34.800 4.080 36.000 648.720 ; + RECT 45.680 4.080 46.880 648.720 ; + RECT 56.560 4.080 57.760 648.720 ; + RECT 67.440 4.080 68.640 648.720 ; + RECT 78.320 4.080 79.520 648.720 ; + RECT 89.200 4.080 90.400 648.720 ; + RECT 100.080 4.080 101.280 648.720 ; + RECT 110.960 4.080 112.160 648.720 ; + RECT 121.840 4.080 123.040 648.720 ; + RECT 132.720 4.080 133.920 648.720 ; + RECT 143.600 4.080 144.800 648.720 ; + RECT 154.480 4.080 155.680 648.720 ; + RECT 165.360 4.080 166.560 648.720 ; + RECT 176.240 4.080 177.440 648.720 ; + RECT 187.120 4.080 188.320 648.720 ; + RECT 198.000 4.080 199.200 648.720 ; + RECT 208.880 4.080 210.080 648.720 ; + RECT 219.760 4.080 220.960 648.720 ; + RECT 230.640 4.080 231.840 648.720 ; + RECT 241.520 4.080 242.720 648.720 ; + RECT 252.400 4.080 253.600 648.720 ; + RECT 263.280 4.080 264.480 648.720 ; + RECT 274.160 4.080 275.360 648.720 ; + RECT 285.040 4.080 286.240 648.720 ; + RECT 295.920 4.080 297.120 648.720 ; + RECT 306.800 4.080 308.000 648.720 ; + RECT 317.680 4.080 318.880 648.720 ; + RECT 328.560 4.080 329.760 648.720 ; + RECT 339.440 4.080 340.640 648.720 ; + RECT 350.320 4.080 351.520 648.720 ; + RECT 361.200 4.080 362.400 648.720 ; + RECT 372.080 4.080 373.280 648.720 ; + RECT 382.960 4.080 384.160 648.720 ; + RECT 393.840 4.080 395.040 648.720 ; + RECT 404.720 4.080 405.920 648.720 ; + RECT 415.600 4.080 416.800 648.720 ; + RECT 426.480 4.080 427.680 648.720 ; + RECT 437.360 4.080 438.560 648.720 ; + RECT 448.240 4.080 449.440 648.720 ; + RECT 459.120 4.080 460.320 648.720 ; + RECT 470.000 4.080 471.200 648.720 ; + RECT 480.880 4.080 482.080 648.720 ; + RECT 491.760 4.080 492.960 648.720 ; + RECT 502.640 4.080 503.840 648.720 ; + RECT 513.520 4.080 514.720 648.720 ; + RECT 524.400 4.080 525.600 648.720 ; + RECT 535.280 4.080 536.480 648.720 ; + RECT 546.160 4.080 547.360 648.720 ; + RECT 557.040 4.080 558.240 648.720 ; + RECT 567.920 4.080 569.120 648.720 ; + RECT 578.800 4.080 580.000 648.720 ; + RECT 589.680 4.080 590.880 648.720 ; + RECT 600.560 4.080 601.760 648.720 ; + RECT 611.440 4.080 612.640 648.720 ; + RECT 622.320 4.080 623.520 648.720 ; + RECT 633.200 4.080 634.400 648.720 ; + RECT 644.080 4.080 645.280 648.720 ; + RECT 654.960 4.080 656.160 648.720 ; + RECT 665.840 4.080 667.040 648.720 ; + RECT 676.720 4.080 677.920 648.720 ; + RECT 687.600 4.080 688.800 648.720 ; + RECT 698.480 4.080 699.680 648.720 ; + RECT 709.360 4.080 710.560 648.720 ; + RECT 720.240 4.080 721.440 648.720 ; + RECT 731.120 4.080 732.320 648.720 ; + RECT 742.000 4.080 743.200 648.720 ; + RECT 752.880 4.080 754.080 648.720 ; + RECT 763.760 4.080 764.960 648.720 ; + RECT 774.640 4.080 775.840 648.720 ; + RECT 785.520 4.080 786.720 648.720 ; + RECT 796.400 4.080 797.600 648.720 ; + RECT 807.280 4.080 808.480 648.720 ; + RECT 818.160 4.080 819.360 648.720 ; + RECT 829.040 4.080 830.240 648.720 ; + RECT 839.920 4.080 841.120 648.720 ; + RECT 850.800 4.080 852.000 648.720 ; + RECT 861.680 4.080 862.880 648.720 ; + RECT 872.560 4.080 873.760 648.720 ; + RECT 883.440 4.080 884.640 648.720 ; + RECT 894.320 4.080 895.520 648.720 ; + RECT 905.200 4.080 906.400 648.720 ; + RECT 916.080 4.080 917.280 648.720 ; + RECT 926.960 4.080 928.160 648.720 ; + RECT 937.840 4.080 939.040 648.720 ; + RECT 948.720 4.080 949.920 648.720 ; + RECT 959.600 4.080 960.800 648.720 ; + RECT 970.480 4.080 971.680 648.720 ; + RECT 981.360 4.080 982.560 648.720 ; + RECT 992.240 4.080 993.440 648.720 ; + RECT 1003.120 4.080 1004.320 648.720 ; + RECT 1014.000 4.080 1015.200 648.720 ; + RECT 1024.880 4.080 1026.080 648.720 ; + RECT 1035.760 4.080 1036.960 648.720 ; + END + END VDD + OBS + LAYER met1 ; + RECT 0 0 1046.040 652.800 ; + LAYER met2 ; + RECT 0 0 1046.040 652.800 ; + LAYER met3 ; + RECT 0 0 1046.040 652.800 ; + LAYER met4 ; + RECT 0 0 1046.040 652.800 ; + END +END fakeram_64x2048_1rw + +END LIBRARY diff --git a/designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x256_1rw.lef b/designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x256_1rw.lef new file mode 100644 index 0000000..a54285e --- /dev/null +++ b/designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x256_1rw.lef @@ -0,0 +1,2047 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_64x256_1rw + FOREIGN fakeram_64x256_1rw 0 0 ; + SYMMETRY X Y R90 ; + SIZE 1010.160 BY 160.480 ; + CLASS BLOCK ; + PIN rw0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 3.930 0.900 4.230 ; + END + END rw0_wmask_in[0] + PIN rw0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 8.010 0.900 8.310 ; + END + END rw0_wmask_in[1] + PIN rw0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 12.090 0.900 12.390 ; + END + END rw0_wmask_in[2] + PIN rw0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 16.170 0.900 16.470 ; + END + END rw0_wmask_in[3] + PIN rw0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 20.250 0.900 20.550 ; + END + END rw0_wmask_in[4] + PIN rw0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 24.330 0.900 24.630 ; + END + END rw0_wmask_in[5] + PIN rw0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 28.410 0.900 28.710 ; + END + END rw0_wmask_in[6] + PIN rw0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 32.490 0.900 32.790 ; + END + END rw0_wmask_in[7] + PIN rw0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 36.570 0.900 36.870 ; + END + END rw0_wmask_in[8] + PIN rw0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 40.650 0.900 40.950 ; + END + END rw0_wmask_in[9] + PIN rw0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 44.730 0.900 45.030 ; + END + END rw0_wmask_in[10] + PIN rw0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 48.810 0.900 49.110 ; + END + END rw0_wmask_in[11] + PIN rw0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 52.890 0.900 53.190 ; + END + END rw0_wmask_in[12] + PIN rw0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 56.970 0.900 57.270 ; + END + END rw0_wmask_in[13] + PIN rw0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 61.050 0.900 61.350 ; + END + END rw0_wmask_in[14] + PIN rw0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 65.130 0.900 65.430 ; + END + END rw0_wmask_in[15] + PIN rw0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 3.930 1010.160 4.230 ; + END + END rw0_wmask_in[16] + PIN rw0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 8.010 1010.160 8.310 ; + END + END rw0_wmask_in[17] + PIN rw0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 12.090 1010.160 12.390 ; + END + END rw0_wmask_in[18] + PIN rw0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 16.170 1010.160 16.470 ; + END + END rw0_wmask_in[19] + PIN rw0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 20.250 1010.160 20.550 ; + END + END rw0_wmask_in[20] + PIN rw0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 24.330 1010.160 24.630 ; + END + END rw0_wmask_in[21] + PIN rw0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 28.410 1010.160 28.710 ; + END + END rw0_wmask_in[22] + PIN rw0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 32.490 1010.160 32.790 ; + END + END rw0_wmask_in[23] + PIN rw0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 36.570 1010.160 36.870 ; + END + END rw0_wmask_in[24] + PIN rw0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 40.650 1010.160 40.950 ; + END + END rw0_wmask_in[25] + PIN rw0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 44.730 1010.160 45.030 ; + END + END rw0_wmask_in[26] + PIN rw0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 48.810 1010.160 49.110 ; + END + END rw0_wmask_in[27] + PIN rw0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 52.890 1010.160 53.190 ; + END + END rw0_wmask_in[28] + PIN rw0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 56.970 1010.160 57.270 ; + END + END rw0_wmask_in[29] + PIN rw0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 61.050 1010.160 61.350 ; + END + END rw0_wmask_in[30] + PIN rw0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 65.130 1010.160 65.430 ; + END + END rw0_wmask_in[31] + PIN rw0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 2.690 160.060 2.830 160.480 ; + END + END rw0_wmask_in[32] + PIN rw0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 17.410 160.060 17.550 160.480 ; + END + END rw0_wmask_in[33] + PIN rw0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 32.130 160.060 32.270 160.480 ; + END + END rw0_wmask_in[34] + PIN rw0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 46.850 160.060 46.990 160.480 ; + END + END rw0_wmask_in[35] + PIN rw0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 61.570 160.060 61.710 160.480 ; + END + END rw0_wmask_in[36] + PIN rw0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 76.290 160.060 76.430 160.480 ; + END + END rw0_wmask_in[37] + PIN rw0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 91.010 160.060 91.150 160.480 ; + END + END rw0_wmask_in[38] + PIN rw0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 105.730 160.060 105.870 160.480 ; + END + END rw0_wmask_in[39] + PIN rw0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 120.450 160.060 120.590 160.480 ; + END + END rw0_wmask_in[40] + PIN rw0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 135.170 160.060 135.310 160.480 ; + END + END rw0_wmask_in[41] + PIN rw0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 149.890 160.060 150.030 160.480 ; + END + END rw0_wmask_in[42] + PIN rw0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 164.610 160.060 164.750 160.480 ; + END + END rw0_wmask_in[43] + PIN rw0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 179.330 160.060 179.470 160.480 ; + END + END rw0_wmask_in[44] + PIN rw0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 194.050 160.060 194.190 160.480 ; + END + END rw0_wmask_in[45] + PIN rw0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 208.770 160.060 208.910 160.480 ; + END + END rw0_wmask_in[46] + PIN rw0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 223.490 160.060 223.630 160.480 ; + END + END rw0_wmask_in[47] + PIN rw0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 238.210 160.060 238.350 160.480 ; + END + END rw0_wmask_in[48] + PIN rw0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 252.930 160.060 253.070 160.480 ; + END + END rw0_wmask_in[49] + PIN rw0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 267.650 160.060 267.790 160.480 ; + END + END rw0_wmask_in[50] + PIN rw0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 282.370 160.060 282.510 160.480 ; + END + END rw0_wmask_in[51] + PIN rw0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 297.090 160.060 297.230 160.480 ; + END + END rw0_wmask_in[52] + PIN rw0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 311.810 160.060 311.950 160.480 ; + END + END rw0_wmask_in[53] + PIN rw0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 326.530 160.060 326.670 160.480 ; + END + END rw0_wmask_in[54] + PIN rw0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 341.250 160.060 341.390 160.480 ; + END + END rw0_wmask_in[55] + PIN rw0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 355.970 160.060 356.110 160.480 ; + END + END rw0_wmask_in[56] + PIN rw0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 370.690 160.060 370.830 160.480 ; + END + END rw0_wmask_in[57] + PIN rw0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 385.410 160.060 385.550 160.480 ; + END + END rw0_wmask_in[58] + PIN rw0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 400.130 160.060 400.270 160.480 ; + END + END rw0_wmask_in[59] + PIN rw0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 414.850 160.060 414.990 160.480 ; + END + END rw0_wmask_in[60] + PIN rw0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 429.570 160.060 429.710 160.480 ; + END + END rw0_wmask_in[61] + PIN rw0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 444.290 160.060 444.430 160.480 ; + END + END rw0_wmask_in[62] + PIN rw0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 459.010 160.060 459.150 160.480 ; + END + END rw0_wmask_in[63] + PIN rw0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 69.210 0.900 69.510 ; + END + END rw0_wd_in[0] + PIN rw0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 73.290 0.900 73.590 ; + END + END rw0_wd_in[1] + PIN rw0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 77.370 0.900 77.670 ; + END + END rw0_wd_in[2] + PIN rw0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 81.450 0.900 81.750 ; + END + END rw0_wd_in[3] + PIN rw0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 85.530 0.900 85.830 ; + END + END rw0_wd_in[4] + PIN rw0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 89.610 0.900 89.910 ; + END + END rw0_wd_in[5] + PIN rw0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 93.690 0.900 93.990 ; + END + END rw0_wd_in[6] + PIN rw0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 97.770 0.900 98.070 ; + END + END rw0_wd_in[7] + PIN rw0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 101.850 0.900 102.150 ; + END + END rw0_wd_in[8] + PIN rw0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 105.930 0.900 106.230 ; + END + END rw0_wd_in[9] + PIN rw0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 110.010 0.900 110.310 ; + END + END rw0_wd_in[10] + PIN rw0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 114.090 0.900 114.390 ; + END + END rw0_wd_in[11] + PIN rw0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 118.170 0.900 118.470 ; + END + END rw0_wd_in[12] + PIN rw0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 122.250 0.900 122.550 ; + END + END rw0_wd_in[13] + PIN rw0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 126.330 0.900 126.630 ; + END + END rw0_wd_in[14] + PIN rw0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 130.410 0.900 130.710 ; + END + END rw0_wd_in[15] + PIN rw0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 69.210 1010.160 69.510 ; + END + END rw0_wd_in[16] + PIN rw0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 73.290 1010.160 73.590 ; + END + END rw0_wd_in[17] + PIN rw0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 77.370 1010.160 77.670 ; + END + END rw0_wd_in[18] + PIN rw0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 81.450 1010.160 81.750 ; + END + END rw0_wd_in[19] + PIN rw0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 85.530 1010.160 85.830 ; + END + END rw0_wd_in[20] + PIN rw0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 89.610 1010.160 89.910 ; + END + END rw0_wd_in[21] + PIN rw0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 93.690 1010.160 93.990 ; + END + END rw0_wd_in[22] + PIN rw0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 97.770 1010.160 98.070 ; + END + END rw0_wd_in[23] + PIN rw0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 101.850 1010.160 102.150 ; + END + END rw0_wd_in[24] + PIN rw0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 105.930 1010.160 106.230 ; + END + END rw0_wd_in[25] + PIN rw0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 110.010 1010.160 110.310 ; + END + END rw0_wd_in[26] + PIN rw0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 114.090 1010.160 114.390 ; + END + END rw0_wd_in[27] + PIN rw0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 118.170 1010.160 118.470 ; + END + END rw0_wd_in[28] + PIN rw0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 122.250 1010.160 122.550 ; + END + END rw0_wd_in[29] + PIN rw0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 126.330 1010.160 126.630 ; + END + END rw0_wd_in[30] + PIN rw0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 130.410 1010.160 130.710 ; + END + END rw0_wd_in[31] + PIN rw0_wd_in[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 2.690 0.000 2.830 0.420 ; + END + END rw0_wd_in[32] + PIN rw0_wd_in[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 18.330 0.000 18.470 0.420 ; + END + END rw0_wd_in[33] + PIN rw0_wd_in[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 33.970 0.000 34.110 0.420 ; + END + END rw0_wd_in[34] + PIN rw0_wd_in[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 49.610 0.000 49.750 0.420 ; + END + END rw0_wd_in[35] + PIN rw0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 65.250 0.000 65.390 0.420 ; + END + END rw0_wd_in[36] + PIN rw0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 80.890 0.000 81.030 0.420 ; + END + END rw0_wd_in[37] + PIN rw0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 96.530 0.000 96.670 0.420 ; + END + END rw0_wd_in[38] + PIN rw0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 112.170 0.000 112.310 0.420 ; + END + END rw0_wd_in[39] + PIN rw0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 127.810 0.000 127.950 0.420 ; + END + END rw0_wd_in[40] + PIN rw0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 143.450 0.000 143.590 0.420 ; + END + END rw0_wd_in[41] + PIN rw0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 159.090 0.000 159.230 0.420 ; + END + END rw0_wd_in[42] + PIN rw0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 174.730 0.000 174.870 0.420 ; + END + END rw0_wd_in[43] + PIN rw0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 190.370 0.000 190.510 0.420 ; + END + END rw0_wd_in[44] + PIN rw0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 206.010 0.000 206.150 0.420 ; + END + END rw0_wd_in[45] + PIN rw0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 221.650 0.000 221.790 0.420 ; + END + END rw0_wd_in[46] + PIN rw0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 237.290 0.000 237.430 0.420 ; + END + END rw0_wd_in[47] + PIN rw0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 252.930 0.000 253.070 0.420 ; + END + END rw0_wd_in[48] + PIN rw0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 268.570 0.000 268.710 0.420 ; + END + END rw0_wd_in[49] + PIN rw0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 284.210 0.000 284.350 0.420 ; + END + END rw0_wd_in[50] + PIN rw0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 299.850 0.000 299.990 0.420 ; + END + END rw0_wd_in[51] + PIN rw0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 315.490 0.000 315.630 0.420 ; + END + END rw0_wd_in[52] + PIN rw0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 331.130 0.000 331.270 0.420 ; + END + END rw0_wd_in[53] + PIN rw0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 346.770 0.000 346.910 0.420 ; + END + END rw0_wd_in[54] + PIN rw0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 362.410 0.000 362.550 0.420 ; + END + END rw0_wd_in[55] + PIN rw0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 378.050 0.000 378.190 0.420 ; + END + END rw0_wd_in[56] + PIN rw0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 393.690 0.000 393.830 0.420 ; + END + END rw0_wd_in[57] + PIN rw0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 409.330 0.000 409.470 0.420 ; + END + END rw0_wd_in[58] + PIN rw0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 424.970 0.000 425.110 0.420 ; + END + END rw0_wd_in[59] + PIN rw0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 440.610 0.000 440.750 0.420 ; + END + END rw0_wd_in[60] + PIN rw0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 456.250 0.000 456.390 0.420 ; + END + END rw0_wd_in[61] + PIN rw0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 471.890 0.000 472.030 0.420 ; + END + END rw0_wd_in[62] + PIN rw0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 487.530 0.000 487.670 0.420 ; + END + END rw0_wd_in[63] + PIN rw0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 503.170 0.000 503.310 0.420 ; + END + END rw0_rd_out[0] + PIN rw0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 518.810 0.000 518.950 0.420 ; + END + END rw0_rd_out[1] + PIN rw0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 534.450 0.000 534.590 0.420 ; + END + END rw0_rd_out[2] + PIN rw0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 550.090 0.000 550.230 0.420 ; + END + END rw0_rd_out[3] + PIN rw0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 565.730 0.000 565.870 0.420 ; + END + END rw0_rd_out[4] + PIN rw0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 581.370 0.000 581.510 0.420 ; + END + END rw0_rd_out[5] + PIN rw0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 597.010 0.000 597.150 0.420 ; + END + END rw0_rd_out[6] + PIN rw0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 612.650 0.000 612.790 0.420 ; + END + END rw0_rd_out[7] + PIN rw0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 628.290 0.000 628.430 0.420 ; + END + END rw0_rd_out[8] + PIN rw0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 643.930 0.000 644.070 0.420 ; + END + END rw0_rd_out[9] + PIN rw0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 659.570 0.000 659.710 0.420 ; + END + END rw0_rd_out[10] + PIN rw0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 675.210 0.000 675.350 0.420 ; + END + END rw0_rd_out[11] + PIN rw0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 690.850 0.000 690.990 0.420 ; + END + END rw0_rd_out[12] + PIN rw0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 706.490 0.000 706.630 0.420 ; + END + END rw0_rd_out[13] + PIN rw0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 722.130 0.000 722.270 0.420 ; + END + END rw0_rd_out[14] + PIN rw0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 737.770 0.000 737.910 0.420 ; + END + END rw0_rd_out[15] + PIN rw0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 753.410 0.000 753.550 0.420 ; + END + END rw0_rd_out[16] + PIN rw0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 769.050 0.000 769.190 0.420 ; + END + END rw0_rd_out[17] + PIN rw0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 784.690 0.000 784.830 0.420 ; + END + END rw0_rd_out[18] + PIN rw0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 800.330 0.000 800.470 0.420 ; + END + END rw0_rd_out[19] + PIN rw0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 815.970 0.000 816.110 0.420 ; + END + END rw0_rd_out[20] + PIN rw0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 831.610 0.000 831.750 0.420 ; + END + END rw0_rd_out[21] + PIN rw0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 847.250 0.000 847.390 0.420 ; + END + END rw0_rd_out[22] + PIN rw0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 862.890 0.000 863.030 0.420 ; + END + END rw0_rd_out[23] + PIN rw0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 878.530 0.000 878.670 0.420 ; + END + END rw0_rd_out[24] + PIN rw0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 894.170 0.000 894.310 0.420 ; + END + END rw0_rd_out[25] + PIN rw0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 909.810 0.000 909.950 0.420 ; + END + END rw0_rd_out[26] + PIN rw0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 925.450 0.000 925.590 0.420 ; + END + END rw0_rd_out[27] + PIN rw0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 941.090 0.000 941.230 0.420 ; + END + END rw0_rd_out[28] + PIN rw0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 956.730 0.000 956.870 0.420 ; + END + END rw0_rd_out[29] + PIN rw0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 972.370 0.000 972.510 0.420 ; + END + END rw0_rd_out[30] + PIN rw0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 988.010 0.000 988.150 0.420 ; + END + END rw0_rd_out[31] + PIN rw0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 473.730 160.060 473.870 160.480 ; + END + END rw0_rd_out[32] + PIN rw0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 488.450 160.060 488.590 160.480 ; + END + END rw0_rd_out[33] + PIN rw0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 503.170 160.060 503.310 160.480 ; + END + END rw0_rd_out[34] + PIN rw0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 517.890 160.060 518.030 160.480 ; + END + END rw0_rd_out[35] + PIN rw0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 532.610 160.060 532.750 160.480 ; + END + END rw0_rd_out[36] + PIN rw0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 547.330 160.060 547.470 160.480 ; + END + END rw0_rd_out[37] + PIN rw0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 562.050 160.060 562.190 160.480 ; + END + END rw0_rd_out[38] + PIN rw0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 576.770 160.060 576.910 160.480 ; + END + END rw0_rd_out[39] + PIN rw0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 591.490 160.060 591.630 160.480 ; + END + END rw0_rd_out[40] + PIN rw0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 606.210 160.060 606.350 160.480 ; + END + END rw0_rd_out[41] + PIN rw0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 620.930 160.060 621.070 160.480 ; + END + END rw0_rd_out[42] + PIN rw0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 635.650 160.060 635.790 160.480 ; + END + END rw0_rd_out[43] + PIN rw0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 650.370 160.060 650.510 160.480 ; + END + END rw0_rd_out[44] + PIN rw0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 665.090 160.060 665.230 160.480 ; + END + END rw0_rd_out[45] + PIN rw0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 679.810 160.060 679.950 160.480 ; + END + END rw0_rd_out[46] + PIN rw0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 694.530 160.060 694.670 160.480 ; + END + END rw0_rd_out[47] + PIN rw0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 709.250 160.060 709.390 160.480 ; + END + END rw0_rd_out[48] + PIN rw0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 723.970 160.060 724.110 160.480 ; + END + END rw0_rd_out[49] + PIN rw0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 738.690 160.060 738.830 160.480 ; + END + END rw0_rd_out[50] + PIN rw0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 753.410 160.060 753.550 160.480 ; + END + END rw0_rd_out[51] + PIN rw0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 768.130 160.060 768.270 160.480 ; + END + END rw0_rd_out[52] + PIN rw0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 782.850 160.060 782.990 160.480 ; + END + END rw0_rd_out[53] + PIN rw0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 797.570 160.060 797.710 160.480 ; + END + END rw0_rd_out[54] + PIN rw0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 812.290 160.060 812.430 160.480 ; + END + END rw0_rd_out[55] + PIN rw0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 827.010 160.060 827.150 160.480 ; + END + END rw0_rd_out[56] + PIN rw0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 841.730 160.060 841.870 160.480 ; + END + END rw0_rd_out[57] + PIN rw0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 856.450 160.060 856.590 160.480 ; + END + END rw0_rd_out[58] + PIN rw0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 871.170 160.060 871.310 160.480 ; + END + END rw0_rd_out[59] + PIN rw0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 885.890 160.060 886.030 160.480 ; + END + END rw0_rd_out[60] + PIN rw0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 900.610 160.060 900.750 160.480 ; + END + END rw0_rd_out[61] + PIN rw0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 915.330 160.060 915.470 160.480 ; + END + END rw0_rd_out[62] + PIN rw0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 930.050 160.060 930.190 160.480 ; + END + END rw0_rd_out[63] + PIN rw0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 134.490 0.900 134.790 ; + END + END rw0_addr_in[0] + PIN rw0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 138.570 0.900 138.870 ; + END + END rw0_addr_in[1] + PIN rw0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 142.650 0.900 142.950 ; + END + END rw0_addr_in[2] + PIN rw0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 146.730 0.900 147.030 ; + END + END rw0_addr_in[3] + PIN rw0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 134.490 1010.160 134.790 ; + END + END rw0_addr_in[4] + PIN rw0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 138.570 1010.160 138.870 ; + END + END rw0_addr_in[5] + PIN rw0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 142.650 1010.160 142.950 ; + END + END rw0_addr_in[6] + PIN rw0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 1009.260 146.730 1010.160 147.030 ; + END + END rw0_addr_in[7] + PIN rw0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 944.770 160.060 944.910 160.480 ; + END + END rw0_we_in + PIN rw0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 959.490 160.060 959.630 160.480 ; + END + END rw0_ce_in + PIN rw0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 974.210 160.060 974.350 160.480 ; + END + END rw0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met4 ; + RECT 2.160 4.080 3.360 156.400 ; + RECT 13.040 4.080 14.240 156.400 ; + RECT 23.920 4.080 25.120 156.400 ; + RECT 34.800 4.080 36.000 156.400 ; + RECT 45.680 4.080 46.880 156.400 ; + RECT 56.560 4.080 57.760 156.400 ; + RECT 67.440 4.080 68.640 156.400 ; + RECT 78.320 4.080 79.520 156.400 ; + RECT 89.200 4.080 90.400 156.400 ; + RECT 100.080 4.080 101.280 156.400 ; + RECT 110.960 4.080 112.160 156.400 ; + RECT 121.840 4.080 123.040 156.400 ; + RECT 132.720 4.080 133.920 156.400 ; + RECT 143.600 4.080 144.800 156.400 ; + RECT 154.480 4.080 155.680 156.400 ; + RECT 165.360 4.080 166.560 156.400 ; + RECT 176.240 4.080 177.440 156.400 ; + RECT 187.120 4.080 188.320 156.400 ; + RECT 198.000 4.080 199.200 156.400 ; + RECT 208.880 4.080 210.080 156.400 ; + RECT 219.760 4.080 220.960 156.400 ; + RECT 230.640 4.080 231.840 156.400 ; + RECT 241.520 4.080 242.720 156.400 ; + RECT 252.400 4.080 253.600 156.400 ; + RECT 263.280 4.080 264.480 156.400 ; + RECT 274.160 4.080 275.360 156.400 ; + RECT 285.040 4.080 286.240 156.400 ; + RECT 295.920 4.080 297.120 156.400 ; + RECT 306.800 4.080 308.000 156.400 ; + RECT 317.680 4.080 318.880 156.400 ; + RECT 328.560 4.080 329.760 156.400 ; + RECT 339.440 4.080 340.640 156.400 ; + RECT 350.320 4.080 351.520 156.400 ; + RECT 361.200 4.080 362.400 156.400 ; + RECT 372.080 4.080 373.280 156.400 ; + RECT 382.960 4.080 384.160 156.400 ; + RECT 393.840 4.080 395.040 156.400 ; + RECT 404.720 4.080 405.920 156.400 ; + RECT 415.600 4.080 416.800 156.400 ; + RECT 426.480 4.080 427.680 156.400 ; + RECT 437.360 4.080 438.560 156.400 ; + RECT 448.240 4.080 449.440 156.400 ; + RECT 459.120 4.080 460.320 156.400 ; + RECT 470.000 4.080 471.200 156.400 ; + RECT 480.880 4.080 482.080 156.400 ; + RECT 491.760 4.080 492.960 156.400 ; + RECT 502.640 4.080 503.840 156.400 ; + RECT 513.520 4.080 514.720 156.400 ; + RECT 524.400 4.080 525.600 156.400 ; + RECT 535.280 4.080 536.480 156.400 ; + RECT 546.160 4.080 547.360 156.400 ; + RECT 557.040 4.080 558.240 156.400 ; + RECT 567.920 4.080 569.120 156.400 ; + RECT 578.800 4.080 580.000 156.400 ; + RECT 589.680 4.080 590.880 156.400 ; + RECT 600.560 4.080 601.760 156.400 ; + RECT 611.440 4.080 612.640 156.400 ; + RECT 622.320 4.080 623.520 156.400 ; + RECT 633.200 4.080 634.400 156.400 ; + RECT 644.080 4.080 645.280 156.400 ; + RECT 654.960 4.080 656.160 156.400 ; + RECT 665.840 4.080 667.040 156.400 ; + RECT 676.720 4.080 677.920 156.400 ; + RECT 687.600 4.080 688.800 156.400 ; + RECT 698.480 4.080 699.680 156.400 ; + RECT 709.360 4.080 710.560 156.400 ; + RECT 720.240 4.080 721.440 156.400 ; + RECT 731.120 4.080 732.320 156.400 ; + RECT 742.000 4.080 743.200 156.400 ; + RECT 752.880 4.080 754.080 156.400 ; + RECT 763.760 4.080 764.960 156.400 ; + RECT 774.640 4.080 775.840 156.400 ; + RECT 785.520 4.080 786.720 156.400 ; + RECT 796.400 4.080 797.600 156.400 ; + RECT 807.280 4.080 808.480 156.400 ; + RECT 818.160 4.080 819.360 156.400 ; + RECT 829.040 4.080 830.240 156.400 ; + RECT 839.920 4.080 841.120 156.400 ; + RECT 850.800 4.080 852.000 156.400 ; + RECT 861.680 4.080 862.880 156.400 ; + RECT 872.560 4.080 873.760 156.400 ; + RECT 883.440 4.080 884.640 156.400 ; + RECT 894.320 4.080 895.520 156.400 ; + RECT 905.200 4.080 906.400 156.400 ; + RECT 916.080 4.080 917.280 156.400 ; + RECT 926.960 4.080 928.160 156.400 ; + RECT 937.840 4.080 939.040 156.400 ; + RECT 948.720 4.080 949.920 156.400 ; + RECT 959.600 4.080 960.800 156.400 ; + RECT 970.480 4.080 971.680 156.400 ; + RECT 981.360 4.080 982.560 156.400 ; + RECT 992.240 4.080 993.440 156.400 ; + RECT 1003.120 4.080 1004.320 156.400 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met4 ; + RECT 2.160 4.080 3.360 156.400 ; + RECT 13.040 4.080 14.240 156.400 ; + RECT 23.920 4.080 25.120 156.400 ; + RECT 34.800 4.080 36.000 156.400 ; + RECT 45.680 4.080 46.880 156.400 ; + RECT 56.560 4.080 57.760 156.400 ; + RECT 67.440 4.080 68.640 156.400 ; + RECT 78.320 4.080 79.520 156.400 ; + RECT 89.200 4.080 90.400 156.400 ; + RECT 100.080 4.080 101.280 156.400 ; + RECT 110.960 4.080 112.160 156.400 ; + RECT 121.840 4.080 123.040 156.400 ; + RECT 132.720 4.080 133.920 156.400 ; + RECT 143.600 4.080 144.800 156.400 ; + RECT 154.480 4.080 155.680 156.400 ; + RECT 165.360 4.080 166.560 156.400 ; + RECT 176.240 4.080 177.440 156.400 ; + RECT 187.120 4.080 188.320 156.400 ; + RECT 198.000 4.080 199.200 156.400 ; + RECT 208.880 4.080 210.080 156.400 ; + RECT 219.760 4.080 220.960 156.400 ; + RECT 230.640 4.080 231.840 156.400 ; + RECT 241.520 4.080 242.720 156.400 ; + RECT 252.400 4.080 253.600 156.400 ; + RECT 263.280 4.080 264.480 156.400 ; + RECT 274.160 4.080 275.360 156.400 ; + RECT 285.040 4.080 286.240 156.400 ; + RECT 295.920 4.080 297.120 156.400 ; + RECT 306.800 4.080 308.000 156.400 ; + RECT 317.680 4.080 318.880 156.400 ; + RECT 328.560 4.080 329.760 156.400 ; + RECT 339.440 4.080 340.640 156.400 ; + RECT 350.320 4.080 351.520 156.400 ; + RECT 361.200 4.080 362.400 156.400 ; + RECT 372.080 4.080 373.280 156.400 ; + RECT 382.960 4.080 384.160 156.400 ; + RECT 393.840 4.080 395.040 156.400 ; + RECT 404.720 4.080 405.920 156.400 ; + RECT 415.600 4.080 416.800 156.400 ; + RECT 426.480 4.080 427.680 156.400 ; + RECT 437.360 4.080 438.560 156.400 ; + RECT 448.240 4.080 449.440 156.400 ; + RECT 459.120 4.080 460.320 156.400 ; + RECT 470.000 4.080 471.200 156.400 ; + RECT 480.880 4.080 482.080 156.400 ; + RECT 491.760 4.080 492.960 156.400 ; + RECT 502.640 4.080 503.840 156.400 ; + RECT 513.520 4.080 514.720 156.400 ; + RECT 524.400 4.080 525.600 156.400 ; + RECT 535.280 4.080 536.480 156.400 ; + RECT 546.160 4.080 547.360 156.400 ; + RECT 557.040 4.080 558.240 156.400 ; + RECT 567.920 4.080 569.120 156.400 ; + RECT 578.800 4.080 580.000 156.400 ; + RECT 589.680 4.080 590.880 156.400 ; + RECT 600.560 4.080 601.760 156.400 ; + RECT 611.440 4.080 612.640 156.400 ; + RECT 622.320 4.080 623.520 156.400 ; + RECT 633.200 4.080 634.400 156.400 ; + RECT 644.080 4.080 645.280 156.400 ; + RECT 654.960 4.080 656.160 156.400 ; + RECT 665.840 4.080 667.040 156.400 ; + RECT 676.720 4.080 677.920 156.400 ; + RECT 687.600 4.080 688.800 156.400 ; + RECT 698.480 4.080 699.680 156.400 ; + RECT 709.360 4.080 710.560 156.400 ; + RECT 720.240 4.080 721.440 156.400 ; + RECT 731.120 4.080 732.320 156.400 ; + RECT 742.000 4.080 743.200 156.400 ; + RECT 752.880 4.080 754.080 156.400 ; + RECT 763.760 4.080 764.960 156.400 ; + RECT 774.640 4.080 775.840 156.400 ; + RECT 785.520 4.080 786.720 156.400 ; + RECT 796.400 4.080 797.600 156.400 ; + RECT 807.280 4.080 808.480 156.400 ; + RECT 818.160 4.080 819.360 156.400 ; + RECT 829.040 4.080 830.240 156.400 ; + RECT 839.920 4.080 841.120 156.400 ; + RECT 850.800 4.080 852.000 156.400 ; + RECT 861.680 4.080 862.880 156.400 ; + RECT 872.560 4.080 873.760 156.400 ; + RECT 883.440 4.080 884.640 156.400 ; + RECT 894.320 4.080 895.520 156.400 ; + RECT 905.200 4.080 906.400 156.400 ; + RECT 916.080 4.080 917.280 156.400 ; + RECT 926.960 4.080 928.160 156.400 ; + RECT 937.840 4.080 939.040 156.400 ; + RECT 948.720 4.080 949.920 156.400 ; + RECT 959.600 4.080 960.800 156.400 ; + RECT 970.480 4.080 971.680 156.400 ; + RECT 981.360 4.080 982.560 156.400 ; + RECT 992.240 4.080 993.440 156.400 ; + RECT 1003.120 4.080 1004.320 156.400 ; + END + END VDD + OBS + LAYER met1 ; + RECT 0 0 1010.160 160.480 ; + LAYER met2 ; + RECT 0 0 1010.160 160.480 ; + LAYER met3 ; + RECT 0 0 1010.160 160.480 ; + LAYER met4 ; + RECT 0 0 1010.160 160.480 ; + END +END fakeram_64x256_1rw + +END LIBRARY diff --git a/designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x512_1rw.lef b/designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x512_1rw.lef new file mode 100644 index 0000000..142b337 --- /dev/null +++ b/designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x512_1rw.lef @@ -0,0 +1,1928 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_64x512_1rw + FOREIGN fakeram_64x512_1rw 0 0 ; + SYMMETRY X Y R90 ; + SIZE 316.480 BY 658.240 ; + CLASS BLOCK ; + PIN rw0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 3.930 0.900 4.230 ; + END + END rw0_wmask_in[0] + PIN rw0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 20.930 0.900 21.230 ; + END + END rw0_wmask_in[1] + PIN rw0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 37.930 0.900 38.230 ; + END + END rw0_wmask_in[2] + PIN rw0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 54.930 0.900 55.230 ; + END + END rw0_wmask_in[3] + PIN rw0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 71.930 0.900 72.230 ; + END + END rw0_wmask_in[4] + PIN rw0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 88.930 0.900 89.230 ; + END + END rw0_wmask_in[5] + PIN rw0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 105.930 0.900 106.230 ; + END + END rw0_wmask_in[6] + PIN rw0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 122.930 0.900 123.230 ; + END + END rw0_wmask_in[7] + PIN rw0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 139.930 0.900 140.230 ; + END + END rw0_wmask_in[8] + PIN rw0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 156.930 0.900 157.230 ; + END + END rw0_wmask_in[9] + PIN rw0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 173.930 0.900 174.230 ; + END + END rw0_wmask_in[10] + PIN rw0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 190.930 0.900 191.230 ; + END + END rw0_wmask_in[11] + PIN rw0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 207.930 0.900 208.230 ; + END + END rw0_wmask_in[12] + PIN rw0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 224.930 0.900 225.230 ; + END + END rw0_wmask_in[13] + PIN rw0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 241.930 0.900 242.230 ; + END + END rw0_wmask_in[14] + PIN rw0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 258.930 0.900 259.230 ; + END + END rw0_wmask_in[15] + PIN rw0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 3.930 316.480 4.230 ; + END + END rw0_wmask_in[16] + PIN rw0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 20.930 316.480 21.230 ; + END + END rw0_wmask_in[17] + PIN rw0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 37.930 316.480 38.230 ; + END + END rw0_wmask_in[18] + PIN rw0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 54.930 316.480 55.230 ; + END + END rw0_wmask_in[19] + PIN rw0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 71.930 316.480 72.230 ; + END + END rw0_wmask_in[20] + PIN rw0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 88.930 316.480 89.230 ; + END + END rw0_wmask_in[21] + PIN rw0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 105.930 316.480 106.230 ; + END + END rw0_wmask_in[22] + PIN rw0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 122.930 316.480 123.230 ; + END + END rw0_wmask_in[23] + PIN rw0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 139.930 316.480 140.230 ; + END + END rw0_wmask_in[24] + PIN rw0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 156.930 316.480 157.230 ; + END + END rw0_wmask_in[25] + PIN rw0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 173.930 316.480 174.230 ; + END + END rw0_wmask_in[26] + PIN rw0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 190.930 316.480 191.230 ; + END + END rw0_wmask_in[27] + PIN rw0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 207.930 316.480 208.230 ; + END + END rw0_wmask_in[28] + PIN rw0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 224.930 316.480 225.230 ; + END + END rw0_wmask_in[29] + PIN rw0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 241.930 316.480 242.230 ; + END + END rw0_wmask_in[30] + PIN rw0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 258.930 316.480 259.230 ; + END + END rw0_wmask_in[31] + PIN rw0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 2.690 657.820 2.830 658.240 ; + END + END rw0_wmask_in[32] + PIN rw0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 7.290 657.820 7.430 658.240 ; + END + END rw0_wmask_in[33] + PIN rw0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 11.890 657.820 12.030 658.240 ; + END + END rw0_wmask_in[34] + PIN rw0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 16.490 657.820 16.630 658.240 ; + END + END rw0_wmask_in[35] + PIN rw0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 21.090 657.820 21.230 658.240 ; + END + END rw0_wmask_in[36] + PIN rw0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 25.690 657.820 25.830 658.240 ; + END + END rw0_wmask_in[37] + PIN rw0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 30.290 657.820 30.430 658.240 ; + END + END rw0_wmask_in[38] + PIN rw0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 34.890 657.820 35.030 658.240 ; + END + END rw0_wmask_in[39] + PIN rw0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 39.490 657.820 39.630 658.240 ; + END + END rw0_wmask_in[40] + PIN rw0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 44.090 657.820 44.230 658.240 ; + END + END rw0_wmask_in[41] + PIN rw0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 48.690 657.820 48.830 658.240 ; + END + END rw0_wmask_in[42] + PIN rw0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 53.290 657.820 53.430 658.240 ; + END + END rw0_wmask_in[43] + PIN rw0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 57.890 657.820 58.030 658.240 ; + END + END rw0_wmask_in[44] + PIN rw0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 62.490 657.820 62.630 658.240 ; + END + END rw0_wmask_in[45] + PIN rw0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 67.090 657.820 67.230 658.240 ; + END + END rw0_wmask_in[46] + PIN rw0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 71.690 657.820 71.830 658.240 ; + END + END rw0_wmask_in[47] + PIN rw0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 76.290 657.820 76.430 658.240 ; + END + END rw0_wmask_in[48] + PIN rw0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 80.890 657.820 81.030 658.240 ; + END + END rw0_wmask_in[49] + PIN rw0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 85.490 657.820 85.630 658.240 ; + END + END rw0_wmask_in[50] + PIN rw0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 90.090 657.820 90.230 658.240 ; + END + END rw0_wmask_in[51] + PIN rw0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 94.690 657.820 94.830 658.240 ; + END + END rw0_wmask_in[52] + PIN rw0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 99.290 657.820 99.430 658.240 ; + END + END rw0_wmask_in[53] + PIN rw0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 103.890 657.820 104.030 658.240 ; + END + END rw0_wmask_in[54] + PIN rw0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 108.490 657.820 108.630 658.240 ; + END + END rw0_wmask_in[55] + PIN rw0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 113.090 657.820 113.230 658.240 ; + END + END rw0_wmask_in[56] + PIN rw0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 117.690 657.820 117.830 658.240 ; + END + END rw0_wmask_in[57] + PIN rw0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 122.290 657.820 122.430 658.240 ; + END + END rw0_wmask_in[58] + PIN rw0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 126.890 657.820 127.030 658.240 ; + END + END rw0_wmask_in[59] + PIN rw0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 131.490 657.820 131.630 658.240 ; + END + END rw0_wmask_in[60] + PIN rw0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 136.090 657.820 136.230 658.240 ; + END + END rw0_wmask_in[61] + PIN rw0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 140.690 657.820 140.830 658.240 ; + END + END rw0_wmask_in[62] + PIN rw0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 145.290 657.820 145.430 658.240 ; + END + END rw0_wmask_in[63] + PIN rw0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 275.930 0.900 276.230 ; + END + END rw0_wd_in[0] + PIN rw0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 292.930 0.900 293.230 ; + END + END rw0_wd_in[1] + PIN rw0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 309.930 0.900 310.230 ; + END + END rw0_wd_in[2] + PIN rw0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 326.930 0.900 327.230 ; + END + END rw0_wd_in[3] + PIN rw0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 343.930 0.900 344.230 ; + END + END rw0_wd_in[4] + PIN rw0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 360.930 0.900 361.230 ; + END + END rw0_wd_in[5] + PIN rw0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 377.930 0.900 378.230 ; + END + END rw0_wd_in[6] + PIN rw0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 394.930 0.900 395.230 ; + END + END rw0_wd_in[7] + PIN rw0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 411.930 0.900 412.230 ; + END + END rw0_wd_in[8] + PIN rw0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 428.930 0.900 429.230 ; + END + END rw0_wd_in[9] + PIN rw0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 445.930 0.900 446.230 ; + END + END rw0_wd_in[10] + PIN rw0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 462.930 0.900 463.230 ; + END + END rw0_wd_in[11] + PIN rw0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 479.930 0.900 480.230 ; + END + END rw0_wd_in[12] + PIN rw0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 496.930 0.900 497.230 ; + END + END rw0_wd_in[13] + PIN rw0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 513.930 0.900 514.230 ; + END + END rw0_wd_in[14] + PIN rw0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 530.930 0.900 531.230 ; + END + END rw0_wd_in[15] + PIN rw0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 275.930 316.480 276.230 ; + END + END rw0_wd_in[16] + PIN rw0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 292.930 316.480 293.230 ; + END + END rw0_wd_in[17] + PIN rw0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 309.930 316.480 310.230 ; + END + END rw0_wd_in[18] + PIN rw0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 326.930 316.480 327.230 ; + END + END rw0_wd_in[19] + PIN rw0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 343.930 316.480 344.230 ; + END + END rw0_wd_in[20] + PIN rw0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 360.930 316.480 361.230 ; + END + END rw0_wd_in[21] + PIN rw0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 377.930 316.480 378.230 ; + END + END rw0_wd_in[22] + PIN rw0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 394.930 316.480 395.230 ; + END + END rw0_wd_in[23] + PIN rw0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 411.930 316.480 412.230 ; + END + END rw0_wd_in[24] + PIN rw0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 428.930 316.480 429.230 ; + END + END rw0_wd_in[25] + PIN rw0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 445.930 316.480 446.230 ; + END + END rw0_wd_in[26] + PIN rw0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 462.930 316.480 463.230 ; + END + END rw0_wd_in[27] + PIN rw0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 479.930 316.480 480.230 ; + END + END rw0_wd_in[28] + PIN rw0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 496.930 316.480 497.230 ; + END + END rw0_wd_in[29] + PIN rw0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 513.930 316.480 514.230 ; + END + END rw0_wd_in[30] + PIN rw0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 530.930 316.480 531.230 ; + END + END rw0_wd_in[31] + PIN rw0_wd_in[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 2.690 0.000 2.830 0.420 ; + END + END rw0_wd_in[32] + PIN rw0_wd_in[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 7.290 0.000 7.430 0.420 ; + END + END rw0_wd_in[33] + PIN rw0_wd_in[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 11.890 0.000 12.030 0.420 ; + END + END rw0_wd_in[34] + PIN rw0_wd_in[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 16.490 0.000 16.630 0.420 ; + END + END rw0_wd_in[35] + PIN rw0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 21.090 0.000 21.230 0.420 ; + END + END rw0_wd_in[36] + PIN rw0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 25.690 0.000 25.830 0.420 ; + END + END rw0_wd_in[37] + PIN rw0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 30.290 0.000 30.430 0.420 ; + END + END rw0_wd_in[38] + PIN rw0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 34.890 0.000 35.030 0.420 ; + END + END rw0_wd_in[39] + PIN rw0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 39.490 0.000 39.630 0.420 ; + END + END rw0_wd_in[40] + PIN rw0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 44.090 0.000 44.230 0.420 ; + END + END rw0_wd_in[41] + PIN rw0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 48.690 0.000 48.830 0.420 ; + END + END rw0_wd_in[42] + PIN rw0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 53.290 0.000 53.430 0.420 ; + END + END rw0_wd_in[43] + PIN rw0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 57.890 0.000 58.030 0.420 ; + END + END rw0_wd_in[44] + PIN rw0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 62.490 0.000 62.630 0.420 ; + END + END rw0_wd_in[45] + PIN rw0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 67.090 0.000 67.230 0.420 ; + END + END rw0_wd_in[46] + PIN rw0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 71.690 0.000 71.830 0.420 ; + END + END rw0_wd_in[47] + PIN rw0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 76.290 0.000 76.430 0.420 ; + END + END rw0_wd_in[48] + PIN rw0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 80.890 0.000 81.030 0.420 ; + END + END rw0_wd_in[49] + PIN rw0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 85.490 0.000 85.630 0.420 ; + END + END rw0_wd_in[50] + PIN rw0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 90.090 0.000 90.230 0.420 ; + END + END rw0_wd_in[51] + PIN rw0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 94.690 0.000 94.830 0.420 ; + END + END rw0_wd_in[52] + PIN rw0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 99.290 0.000 99.430 0.420 ; + END + END rw0_wd_in[53] + PIN rw0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 103.890 0.000 104.030 0.420 ; + END + END rw0_wd_in[54] + PIN rw0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 108.490 0.000 108.630 0.420 ; + END + END rw0_wd_in[55] + PIN rw0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 113.090 0.000 113.230 0.420 ; + END + END rw0_wd_in[56] + PIN rw0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 117.690 0.000 117.830 0.420 ; + END + END rw0_wd_in[57] + PIN rw0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 122.290 0.000 122.430 0.420 ; + END + END rw0_wd_in[58] + PIN rw0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 126.890 0.000 127.030 0.420 ; + END + END rw0_wd_in[59] + PIN rw0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 131.490 0.000 131.630 0.420 ; + END + END rw0_wd_in[60] + PIN rw0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 136.090 0.000 136.230 0.420 ; + END + END rw0_wd_in[61] + PIN rw0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 140.690 0.000 140.830 0.420 ; + END + END rw0_wd_in[62] + PIN rw0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 145.290 0.000 145.430 0.420 ; + END + END rw0_wd_in[63] + PIN rw0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 149.890 0.000 150.030 0.420 ; + END + END rw0_rd_out[0] + PIN rw0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 154.490 0.000 154.630 0.420 ; + END + END rw0_rd_out[1] + PIN rw0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 159.090 0.000 159.230 0.420 ; + END + END rw0_rd_out[2] + PIN rw0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 163.690 0.000 163.830 0.420 ; + END + END rw0_rd_out[3] + PIN rw0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 168.290 0.000 168.430 0.420 ; + END + END rw0_rd_out[4] + PIN rw0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 172.890 0.000 173.030 0.420 ; + END + END rw0_rd_out[5] + PIN rw0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 177.490 0.000 177.630 0.420 ; + END + END rw0_rd_out[6] + PIN rw0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 182.090 0.000 182.230 0.420 ; + END + END rw0_rd_out[7] + PIN rw0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 186.690 0.000 186.830 0.420 ; + END + END rw0_rd_out[8] + PIN rw0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 191.290 0.000 191.430 0.420 ; + END + END rw0_rd_out[9] + PIN rw0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 195.890 0.000 196.030 0.420 ; + END + END rw0_rd_out[10] + PIN rw0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 200.490 0.000 200.630 0.420 ; + END + END rw0_rd_out[11] + PIN rw0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 205.090 0.000 205.230 0.420 ; + END + END rw0_rd_out[12] + PIN rw0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 209.690 0.000 209.830 0.420 ; + END + END rw0_rd_out[13] + PIN rw0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 214.290 0.000 214.430 0.420 ; + END + END rw0_rd_out[14] + PIN rw0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 218.890 0.000 219.030 0.420 ; + END + END rw0_rd_out[15] + PIN rw0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 223.490 0.000 223.630 0.420 ; + END + END rw0_rd_out[16] + PIN rw0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 228.090 0.000 228.230 0.420 ; + END + END rw0_rd_out[17] + PIN rw0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 232.690 0.000 232.830 0.420 ; + END + END rw0_rd_out[18] + PIN rw0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 237.290 0.000 237.430 0.420 ; + END + END rw0_rd_out[19] + PIN rw0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 241.890 0.000 242.030 0.420 ; + END + END rw0_rd_out[20] + PIN rw0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 246.490 0.000 246.630 0.420 ; + END + END rw0_rd_out[21] + PIN rw0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 251.090 0.000 251.230 0.420 ; + END + END rw0_rd_out[22] + PIN rw0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 255.690 0.000 255.830 0.420 ; + END + END rw0_rd_out[23] + PIN rw0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 260.290 0.000 260.430 0.420 ; + END + END rw0_rd_out[24] + PIN rw0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 264.890 0.000 265.030 0.420 ; + END + END rw0_rd_out[25] + PIN rw0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 269.490 0.000 269.630 0.420 ; + END + END rw0_rd_out[26] + PIN rw0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 274.090 0.000 274.230 0.420 ; + END + END rw0_rd_out[27] + PIN rw0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 278.690 0.000 278.830 0.420 ; + END + END rw0_rd_out[28] + PIN rw0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 283.290 0.000 283.430 0.420 ; + END + END rw0_rd_out[29] + PIN rw0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 287.890 0.000 288.030 0.420 ; + END + END rw0_rd_out[30] + PIN rw0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 292.490 0.000 292.630 0.420 ; + END + END rw0_rd_out[31] + PIN rw0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 149.890 657.820 150.030 658.240 ; + END + END rw0_rd_out[32] + PIN rw0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 154.490 657.820 154.630 658.240 ; + END + END rw0_rd_out[33] + PIN rw0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 159.090 657.820 159.230 658.240 ; + END + END rw0_rd_out[34] + PIN rw0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 163.690 657.820 163.830 658.240 ; + END + END rw0_rd_out[35] + PIN rw0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 168.290 657.820 168.430 658.240 ; + END + END rw0_rd_out[36] + PIN rw0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 172.890 657.820 173.030 658.240 ; + END + END rw0_rd_out[37] + PIN rw0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 177.490 657.820 177.630 658.240 ; + END + END rw0_rd_out[38] + PIN rw0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 182.090 657.820 182.230 658.240 ; + END + END rw0_rd_out[39] + PIN rw0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 186.690 657.820 186.830 658.240 ; + END + END rw0_rd_out[40] + PIN rw0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 191.290 657.820 191.430 658.240 ; + END + END rw0_rd_out[41] + PIN rw0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 195.890 657.820 196.030 658.240 ; + END + END rw0_rd_out[42] + PIN rw0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 200.490 657.820 200.630 658.240 ; + END + END rw0_rd_out[43] + PIN rw0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 205.090 657.820 205.230 658.240 ; + END + END rw0_rd_out[44] + PIN rw0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 209.690 657.820 209.830 658.240 ; + END + END rw0_rd_out[45] + PIN rw0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 214.290 657.820 214.430 658.240 ; + END + END rw0_rd_out[46] + PIN rw0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 218.890 657.820 219.030 658.240 ; + END + END rw0_rd_out[47] + PIN rw0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 223.490 657.820 223.630 658.240 ; + END + END rw0_rd_out[48] + PIN rw0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 228.090 657.820 228.230 658.240 ; + END + END rw0_rd_out[49] + PIN rw0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 232.690 657.820 232.830 658.240 ; + END + END rw0_rd_out[50] + PIN rw0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 237.290 657.820 237.430 658.240 ; + END + END rw0_rd_out[51] + PIN rw0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 241.890 657.820 242.030 658.240 ; + END + END rw0_rd_out[52] + PIN rw0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 246.490 657.820 246.630 658.240 ; + END + END rw0_rd_out[53] + PIN rw0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 251.090 657.820 251.230 658.240 ; + END + END rw0_rd_out[54] + PIN rw0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 255.690 657.820 255.830 658.240 ; + END + END rw0_rd_out[55] + PIN rw0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 260.290 657.820 260.430 658.240 ; + END + END rw0_rd_out[56] + PIN rw0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 264.890 657.820 265.030 658.240 ; + END + END rw0_rd_out[57] + PIN rw0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 269.490 657.820 269.630 658.240 ; + END + END rw0_rd_out[58] + PIN rw0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 274.090 657.820 274.230 658.240 ; + END + END rw0_rd_out[59] + PIN rw0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 278.690 657.820 278.830 658.240 ; + END + END rw0_rd_out[60] + PIN rw0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 283.290 657.820 283.430 658.240 ; + END + END rw0_rd_out[61] + PIN rw0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 287.890 657.820 288.030 658.240 ; + END + END rw0_rd_out[62] + PIN rw0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 292.490 657.820 292.630 658.240 ; + END + END rw0_rd_out[63] + PIN rw0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 547.930 0.900 548.230 ; + END + END rw0_addr_in[0] + PIN rw0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 564.930 0.900 565.230 ; + END + END rw0_addr_in[1] + PIN rw0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 581.930 0.900 582.230 ; + END + END rw0_addr_in[2] + PIN rw0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 598.930 0.900 599.230 ; + END + END rw0_addr_in[3] + PIN rw0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 615.930 0.900 616.230 ; + END + END rw0_addr_in[4] + PIN rw0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 547.930 316.480 548.230 ; + END + END rw0_addr_in[5] + PIN rw0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 564.930 316.480 565.230 ; + END + END rw0_addr_in[6] + PIN rw0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 581.930 316.480 582.230 ; + END + END rw0_addr_in[7] + PIN rw0_addr_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 315.580 598.930 316.480 599.230 ; + END + END rw0_addr_in[8] + PIN rw0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 297.090 657.820 297.230 658.240 ; + END + END rw0_we_in + PIN rw0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 301.690 657.820 301.830 658.240 ; + END + END rw0_ce_in + PIN rw0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 306.290 657.820 306.430 658.240 ; + END + END rw0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met4 ; + RECT 2.160 4.080 3.360 654.160 ; + RECT 13.040 4.080 14.240 654.160 ; + RECT 23.920 4.080 25.120 654.160 ; + RECT 34.800 4.080 36.000 654.160 ; + RECT 45.680 4.080 46.880 654.160 ; + RECT 56.560 4.080 57.760 654.160 ; + RECT 67.440 4.080 68.640 654.160 ; + RECT 78.320 4.080 79.520 654.160 ; + RECT 89.200 4.080 90.400 654.160 ; + RECT 100.080 4.080 101.280 654.160 ; + RECT 110.960 4.080 112.160 654.160 ; + RECT 121.840 4.080 123.040 654.160 ; + RECT 132.720 4.080 133.920 654.160 ; + RECT 143.600 4.080 144.800 654.160 ; + RECT 154.480 4.080 155.680 654.160 ; + RECT 165.360 4.080 166.560 654.160 ; + RECT 176.240 4.080 177.440 654.160 ; + RECT 187.120 4.080 188.320 654.160 ; + RECT 198.000 4.080 199.200 654.160 ; + RECT 208.880 4.080 210.080 654.160 ; + RECT 219.760 4.080 220.960 654.160 ; + RECT 230.640 4.080 231.840 654.160 ; + RECT 241.520 4.080 242.720 654.160 ; + RECT 252.400 4.080 253.600 654.160 ; + RECT 263.280 4.080 264.480 654.160 ; + RECT 274.160 4.080 275.360 654.160 ; + RECT 285.040 4.080 286.240 654.160 ; + RECT 295.920 4.080 297.120 654.160 ; + RECT 306.800 4.080 308.000 654.160 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met4 ; + RECT 2.160 4.080 3.360 654.160 ; + RECT 13.040 4.080 14.240 654.160 ; + RECT 23.920 4.080 25.120 654.160 ; + RECT 34.800 4.080 36.000 654.160 ; + RECT 45.680 4.080 46.880 654.160 ; + RECT 56.560 4.080 57.760 654.160 ; + RECT 67.440 4.080 68.640 654.160 ; + RECT 78.320 4.080 79.520 654.160 ; + RECT 89.200 4.080 90.400 654.160 ; + RECT 100.080 4.080 101.280 654.160 ; + RECT 110.960 4.080 112.160 654.160 ; + RECT 121.840 4.080 123.040 654.160 ; + RECT 132.720 4.080 133.920 654.160 ; + RECT 143.600 4.080 144.800 654.160 ; + RECT 154.480 4.080 155.680 654.160 ; + RECT 165.360 4.080 166.560 654.160 ; + RECT 176.240 4.080 177.440 654.160 ; + RECT 187.120 4.080 188.320 654.160 ; + RECT 198.000 4.080 199.200 654.160 ; + RECT 208.880 4.080 210.080 654.160 ; + RECT 219.760 4.080 220.960 654.160 ; + RECT 230.640 4.080 231.840 654.160 ; + RECT 241.520 4.080 242.720 654.160 ; + RECT 252.400 4.080 253.600 654.160 ; + RECT 263.280 4.080 264.480 654.160 ; + RECT 274.160 4.080 275.360 654.160 ; + RECT 285.040 4.080 286.240 654.160 ; + RECT 295.920 4.080 297.120 654.160 ; + RECT 306.800 4.080 308.000 654.160 ; + END + END VDD + OBS + LAYER met1 ; + RECT 0 0 316.480 658.240 ; + LAYER met2 ; + RECT 0 0 316.480 658.240 ; + LAYER met3 ; + RECT 0 0 316.480 658.240 ; + LAYER met4 ; + RECT 0 0 316.480 658.240 ; + END +END fakeram_64x512_1rw + +END LIBRARY diff --git a/designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x64_1rw.lef b/designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x64_1rw.lef new file mode 100644 index 0000000..d2d536a --- /dev/null +++ b/designs/sky130hd/SYNtzulA/sram/lef/fakeram_64x64_1rw.lef @@ -0,0 +1,1879 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_64x64_1rw + FOREIGN fakeram_64x64_1rw 0 0 ; + SYMMETRY X Y R90 ; + SIZE 189.980 BY 233.920 ; + CLASS BLOCK ; + PIN rw0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 3.930 0.900 4.230 ; + END + END rw0_wmask_in[0] + PIN rw0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 10.050 0.900 10.350 ; + END + END rw0_wmask_in[1] + PIN rw0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 16.170 0.900 16.470 ; + END + END rw0_wmask_in[2] + PIN rw0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 22.290 0.900 22.590 ; + END + END rw0_wmask_in[3] + PIN rw0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 28.410 0.900 28.710 ; + END + END rw0_wmask_in[4] + PIN rw0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 34.530 0.900 34.830 ; + END + END rw0_wmask_in[5] + PIN rw0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 40.650 0.900 40.950 ; + END + END rw0_wmask_in[6] + PIN rw0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 46.770 0.900 47.070 ; + END + END rw0_wmask_in[7] + PIN rw0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 52.890 0.900 53.190 ; + END + END rw0_wmask_in[8] + PIN rw0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 59.010 0.900 59.310 ; + END + END rw0_wmask_in[9] + PIN rw0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 65.130 0.900 65.430 ; + END + END rw0_wmask_in[10] + PIN rw0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 71.250 0.900 71.550 ; + END + END rw0_wmask_in[11] + PIN rw0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 77.370 0.900 77.670 ; + END + END rw0_wmask_in[12] + PIN rw0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 83.490 0.900 83.790 ; + END + END rw0_wmask_in[13] + PIN rw0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 89.610 0.900 89.910 ; + END + END rw0_wmask_in[14] + PIN rw0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 95.730 0.900 96.030 ; + END + END rw0_wmask_in[15] + PIN rw0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 3.930 189.980 4.230 ; + END + END rw0_wmask_in[16] + PIN rw0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 10.050 189.980 10.350 ; + END + END rw0_wmask_in[17] + PIN rw0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 16.170 189.980 16.470 ; + END + END rw0_wmask_in[18] + PIN rw0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 22.290 189.980 22.590 ; + END + END rw0_wmask_in[19] + PIN rw0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 28.410 189.980 28.710 ; + END + END rw0_wmask_in[20] + PIN rw0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 34.530 189.980 34.830 ; + END + END rw0_wmask_in[21] + PIN rw0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 40.650 189.980 40.950 ; + END + END rw0_wmask_in[22] + PIN rw0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 46.770 189.980 47.070 ; + END + END rw0_wmask_in[23] + PIN rw0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 52.890 189.980 53.190 ; + END + END rw0_wmask_in[24] + PIN rw0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 59.010 189.980 59.310 ; + END + END rw0_wmask_in[25] + PIN rw0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 65.130 189.980 65.430 ; + END + END rw0_wmask_in[26] + PIN rw0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 71.250 189.980 71.550 ; + END + END rw0_wmask_in[27] + PIN rw0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 77.370 189.980 77.670 ; + END + END rw0_wmask_in[28] + PIN rw0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 83.490 189.980 83.790 ; + END + END rw0_wmask_in[29] + PIN rw0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 89.610 189.980 89.910 ; + END + END rw0_wmask_in[30] + PIN rw0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 95.730 189.980 96.030 ; + END + END rw0_wmask_in[31] + PIN rw0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 2.690 233.500 2.830 233.920 ; + END + END rw0_wmask_in[32] + PIN rw0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 4.990 233.500 5.130 233.920 ; + END + END rw0_wmask_in[33] + PIN rw0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 7.290 233.500 7.430 233.920 ; + END + END rw0_wmask_in[34] + PIN rw0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 9.590 233.500 9.730 233.920 ; + END + END rw0_wmask_in[35] + PIN rw0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 11.890 233.500 12.030 233.920 ; + END + END rw0_wmask_in[36] + PIN rw0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 14.190 233.500 14.330 233.920 ; + END + END rw0_wmask_in[37] + PIN rw0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 16.490 233.500 16.630 233.920 ; + END + END rw0_wmask_in[38] + PIN rw0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 18.790 233.500 18.930 233.920 ; + END + END rw0_wmask_in[39] + PIN rw0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 21.090 233.500 21.230 233.920 ; + END + END rw0_wmask_in[40] + PIN rw0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 23.390 233.500 23.530 233.920 ; + END + END rw0_wmask_in[41] + PIN rw0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 25.690 233.500 25.830 233.920 ; + END + END rw0_wmask_in[42] + PIN rw0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 27.990 233.500 28.130 233.920 ; + END + END rw0_wmask_in[43] + PIN rw0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 30.290 233.500 30.430 233.920 ; + END + END rw0_wmask_in[44] + PIN rw0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 32.590 233.500 32.730 233.920 ; + END + END rw0_wmask_in[45] + PIN rw0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 34.890 233.500 35.030 233.920 ; + END + END rw0_wmask_in[46] + PIN rw0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 37.190 233.500 37.330 233.920 ; + END + END rw0_wmask_in[47] + PIN rw0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 39.490 233.500 39.630 233.920 ; + END + END rw0_wmask_in[48] + PIN rw0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 41.790 233.500 41.930 233.920 ; + END + END rw0_wmask_in[49] + PIN rw0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 44.090 233.500 44.230 233.920 ; + END + END rw0_wmask_in[50] + PIN rw0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 46.390 233.500 46.530 233.920 ; + END + END rw0_wmask_in[51] + PIN rw0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 48.690 233.500 48.830 233.920 ; + END + END rw0_wmask_in[52] + PIN rw0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 50.990 233.500 51.130 233.920 ; + END + END rw0_wmask_in[53] + PIN rw0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 53.290 233.500 53.430 233.920 ; + END + END rw0_wmask_in[54] + PIN rw0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 55.590 233.500 55.730 233.920 ; + END + END rw0_wmask_in[55] + PIN rw0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 57.890 233.500 58.030 233.920 ; + END + END rw0_wmask_in[56] + PIN rw0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 60.190 233.500 60.330 233.920 ; + END + END rw0_wmask_in[57] + PIN rw0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 62.490 233.500 62.630 233.920 ; + END + END rw0_wmask_in[58] + PIN rw0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 64.790 233.500 64.930 233.920 ; + END + END rw0_wmask_in[59] + PIN rw0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 67.090 233.500 67.230 233.920 ; + END + END rw0_wmask_in[60] + PIN rw0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 69.390 233.500 69.530 233.920 ; + END + END rw0_wmask_in[61] + PIN rw0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 71.690 233.500 71.830 233.920 ; + END + END rw0_wmask_in[62] + PIN rw0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 73.990 233.500 74.130 233.920 ; + END + END rw0_wmask_in[63] + PIN rw0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 101.850 0.900 102.150 ; + END + END rw0_wd_in[0] + PIN rw0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 107.970 0.900 108.270 ; + END + END rw0_wd_in[1] + PIN rw0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 114.090 0.900 114.390 ; + END + END rw0_wd_in[2] + PIN rw0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 120.210 0.900 120.510 ; + END + END rw0_wd_in[3] + PIN rw0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 126.330 0.900 126.630 ; + END + END rw0_wd_in[4] + PIN rw0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 132.450 0.900 132.750 ; + END + END rw0_wd_in[5] + PIN rw0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 138.570 0.900 138.870 ; + END + END rw0_wd_in[6] + PIN rw0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 144.690 0.900 144.990 ; + END + END rw0_wd_in[7] + PIN rw0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 150.810 0.900 151.110 ; + END + END rw0_wd_in[8] + PIN rw0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 156.930 0.900 157.230 ; + END + END rw0_wd_in[9] + PIN rw0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 163.050 0.900 163.350 ; + END + END rw0_wd_in[10] + PIN rw0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 169.170 0.900 169.470 ; + END + END rw0_wd_in[11] + PIN rw0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 175.290 0.900 175.590 ; + END + END rw0_wd_in[12] + PIN rw0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 181.410 0.900 181.710 ; + END + END rw0_wd_in[13] + PIN rw0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 187.530 0.900 187.830 ; + END + END rw0_wd_in[14] + PIN rw0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 193.650 0.900 193.950 ; + END + END rw0_wd_in[15] + PIN rw0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 101.850 189.980 102.150 ; + END + END rw0_wd_in[16] + PIN rw0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 107.970 189.980 108.270 ; + END + END rw0_wd_in[17] + PIN rw0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 114.090 189.980 114.390 ; + END + END rw0_wd_in[18] + PIN rw0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 120.210 189.980 120.510 ; + END + END rw0_wd_in[19] + PIN rw0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 126.330 189.980 126.630 ; + END + END rw0_wd_in[20] + PIN rw0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 132.450 189.980 132.750 ; + END + END rw0_wd_in[21] + PIN rw0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 138.570 189.980 138.870 ; + END + END rw0_wd_in[22] + PIN rw0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 144.690 189.980 144.990 ; + END + END rw0_wd_in[23] + PIN rw0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 150.810 189.980 151.110 ; + END + END rw0_wd_in[24] + PIN rw0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 156.930 189.980 157.230 ; + END + END rw0_wd_in[25] + PIN rw0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 163.050 189.980 163.350 ; + END + END rw0_wd_in[26] + PIN rw0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 169.170 189.980 169.470 ; + END + END rw0_wd_in[27] + PIN rw0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 175.290 189.980 175.590 ; + END + END rw0_wd_in[28] + PIN rw0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 181.410 189.980 181.710 ; + END + END rw0_wd_in[29] + PIN rw0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 187.530 189.980 187.830 ; + END + END rw0_wd_in[30] + PIN rw0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 193.650 189.980 193.950 ; + END + END rw0_wd_in[31] + PIN rw0_wd_in[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 2.690 0.000 2.830 0.420 ; + END + END rw0_wd_in[32] + PIN rw0_wd_in[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 5.450 0.000 5.590 0.420 ; + END + END rw0_wd_in[33] + PIN rw0_wd_in[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 8.210 0.000 8.350 0.420 ; + END + END rw0_wd_in[34] + PIN rw0_wd_in[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 10.970 0.000 11.110 0.420 ; + END + END rw0_wd_in[35] + PIN rw0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 13.730 0.000 13.870 0.420 ; + END + END rw0_wd_in[36] + PIN rw0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 16.490 0.000 16.630 0.420 ; + END + END rw0_wd_in[37] + PIN rw0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 19.250 0.000 19.390 0.420 ; + END + END rw0_wd_in[38] + PIN rw0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 22.010 0.000 22.150 0.420 ; + END + END rw0_wd_in[39] + PIN rw0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 24.770 0.000 24.910 0.420 ; + END + END rw0_wd_in[40] + PIN rw0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 27.530 0.000 27.670 0.420 ; + END + END rw0_wd_in[41] + PIN rw0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 30.290 0.000 30.430 0.420 ; + END + END rw0_wd_in[42] + PIN rw0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 33.050 0.000 33.190 0.420 ; + END + END rw0_wd_in[43] + PIN rw0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 35.810 0.000 35.950 0.420 ; + END + END rw0_wd_in[44] + PIN rw0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 38.570 0.000 38.710 0.420 ; + END + END rw0_wd_in[45] + PIN rw0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 41.330 0.000 41.470 0.420 ; + END + END rw0_wd_in[46] + PIN rw0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 44.090 0.000 44.230 0.420 ; + END + END rw0_wd_in[47] + PIN rw0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 46.850 0.000 46.990 0.420 ; + END + END rw0_wd_in[48] + PIN rw0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 49.610 0.000 49.750 0.420 ; + END + END rw0_wd_in[49] + PIN rw0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 52.370 0.000 52.510 0.420 ; + END + END rw0_wd_in[50] + PIN rw0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 55.130 0.000 55.270 0.420 ; + END + END rw0_wd_in[51] + PIN rw0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 57.890 0.000 58.030 0.420 ; + END + END rw0_wd_in[52] + PIN rw0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 60.650 0.000 60.790 0.420 ; + END + END rw0_wd_in[53] + PIN rw0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 63.410 0.000 63.550 0.420 ; + END + END rw0_wd_in[54] + PIN rw0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 66.170 0.000 66.310 0.420 ; + END + END rw0_wd_in[55] + PIN rw0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 68.930 0.000 69.070 0.420 ; + END + END rw0_wd_in[56] + PIN rw0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 71.690 0.000 71.830 0.420 ; + END + END rw0_wd_in[57] + PIN rw0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 74.450 0.000 74.590 0.420 ; + END + END rw0_wd_in[58] + PIN rw0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 77.210 0.000 77.350 0.420 ; + END + END rw0_wd_in[59] + PIN rw0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 79.970 0.000 80.110 0.420 ; + END + END rw0_wd_in[60] + PIN rw0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 82.730 0.000 82.870 0.420 ; + END + END rw0_wd_in[61] + PIN rw0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 85.490 0.000 85.630 0.420 ; + END + END rw0_wd_in[62] + PIN rw0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 88.250 0.000 88.390 0.420 ; + END + END rw0_wd_in[63] + PIN rw0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 91.010 0.000 91.150 0.420 ; + END + END rw0_rd_out[0] + PIN rw0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 93.770 0.000 93.910 0.420 ; + END + END rw0_rd_out[1] + PIN rw0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 96.530 0.000 96.670 0.420 ; + END + END rw0_rd_out[2] + PIN rw0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 99.290 0.000 99.430 0.420 ; + END + END rw0_rd_out[3] + PIN rw0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 102.050 0.000 102.190 0.420 ; + END + END rw0_rd_out[4] + PIN rw0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 104.810 0.000 104.950 0.420 ; + END + END rw0_rd_out[5] + PIN rw0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 107.570 0.000 107.710 0.420 ; + END + END rw0_rd_out[6] + PIN rw0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 110.330 0.000 110.470 0.420 ; + END + END rw0_rd_out[7] + PIN rw0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 113.090 0.000 113.230 0.420 ; + END + END rw0_rd_out[8] + PIN rw0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 115.850 0.000 115.990 0.420 ; + END + END rw0_rd_out[9] + PIN rw0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 118.610 0.000 118.750 0.420 ; + END + END rw0_rd_out[10] + PIN rw0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 121.370 0.000 121.510 0.420 ; + END + END rw0_rd_out[11] + PIN rw0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 124.130 0.000 124.270 0.420 ; + END + END rw0_rd_out[12] + PIN rw0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 126.890 0.000 127.030 0.420 ; + END + END rw0_rd_out[13] + PIN rw0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 129.650 0.000 129.790 0.420 ; + END + END rw0_rd_out[14] + PIN rw0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 132.410 0.000 132.550 0.420 ; + END + END rw0_rd_out[15] + PIN rw0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 135.170 0.000 135.310 0.420 ; + END + END rw0_rd_out[16] + PIN rw0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 137.930 0.000 138.070 0.420 ; + END + END rw0_rd_out[17] + PIN rw0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 140.690 0.000 140.830 0.420 ; + END + END rw0_rd_out[18] + PIN rw0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 143.450 0.000 143.590 0.420 ; + END + END rw0_rd_out[19] + PIN rw0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 146.210 0.000 146.350 0.420 ; + END + END rw0_rd_out[20] + PIN rw0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 148.970 0.000 149.110 0.420 ; + END + END rw0_rd_out[21] + PIN rw0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 151.730 0.000 151.870 0.420 ; + END + END rw0_rd_out[22] + PIN rw0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 154.490 0.000 154.630 0.420 ; + END + END rw0_rd_out[23] + PIN rw0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 157.250 0.000 157.390 0.420 ; + END + END rw0_rd_out[24] + PIN rw0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 160.010 0.000 160.150 0.420 ; + END + END rw0_rd_out[25] + PIN rw0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 162.770 0.000 162.910 0.420 ; + END + END rw0_rd_out[26] + PIN rw0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 165.530 0.000 165.670 0.420 ; + END + END rw0_rd_out[27] + PIN rw0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 168.290 0.000 168.430 0.420 ; + END + END rw0_rd_out[28] + PIN rw0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 171.050 0.000 171.190 0.420 ; + END + END rw0_rd_out[29] + PIN rw0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 173.810 0.000 173.950 0.420 ; + END + END rw0_rd_out[30] + PIN rw0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 176.570 0.000 176.710 0.420 ; + END + END rw0_rd_out[31] + PIN rw0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 76.290 233.500 76.430 233.920 ; + END + END rw0_rd_out[32] + PIN rw0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 78.590 233.500 78.730 233.920 ; + END + END rw0_rd_out[33] + PIN rw0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 80.890 233.500 81.030 233.920 ; + END + END rw0_rd_out[34] + PIN rw0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 83.190 233.500 83.330 233.920 ; + END + END rw0_rd_out[35] + PIN rw0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 85.490 233.500 85.630 233.920 ; + END + END rw0_rd_out[36] + PIN rw0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 87.790 233.500 87.930 233.920 ; + END + END rw0_rd_out[37] + PIN rw0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 90.090 233.500 90.230 233.920 ; + END + END rw0_rd_out[38] + PIN rw0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 92.390 233.500 92.530 233.920 ; + END + END rw0_rd_out[39] + PIN rw0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 94.690 233.500 94.830 233.920 ; + END + END rw0_rd_out[40] + PIN rw0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 96.990 233.500 97.130 233.920 ; + END + END rw0_rd_out[41] + PIN rw0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 99.290 233.500 99.430 233.920 ; + END + END rw0_rd_out[42] + PIN rw0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 101.590 233.500 101.730 233.920 ; + END + END rw0_rd_out[43] + PIN rw0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 103.890 233.500 104.030 233.920 ; + END + END rw0_rd_out[44] + PIN rw0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 106.190 233.500 106.330 233.920 ; + END + END rw0_rd_out[45] + PIN rw0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 108.490 233.500 108.630 233.920 ; + END + END rw0_rd_out[46] + PIN rw0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 110.790 233.500 110.930 233.920 ; + END + END rw0_rd_out[47] + PIN rw0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 113.090 233.500 113.230 233.920 ; + END + END rw0_rd_out[48] + PIN rw0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 115.390 233.500 115.530 233.920 ; + END + END rw0_rd_out[49] + PIN rw0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 117.690 233.500 117.830 233.920 ; + END + END rw0_rd_out[50] + PIN rw0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 119.990 233.500 120.130 233.920 ; + END + END rw0_rd_out[51] + PIN rw0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 122.290 233.500 122.430 233.920 ; + END + END rw0_rd_out[52] + PIN rw0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 124.590 233.500 124.730 233.920 ; + END + END rw0_rd_out[53] + PIN rw0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 126.890 233.500 127.030 233.920 ; + END + END rw0_rd_out[54] + PIN rw0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 129.190 233.500 129.330 233.920 ; + END + END rw0_rd_out[55] + PIN rw0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 131.490 233.500 131.630 233.920 ; + END + END rw0_rd_out[56] + PIN rw0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 133.790 233.500 133.930 233.920 ; + END + END rw0_rd_out[57] + PIN rw0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 136.090 233.500 136.230 233.920 ; + END + END rw0_rd_out[58] + PIN rw0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 138.390 233.500 138.530 233.920 ; + END + END rw0_rd_out[59] + PIN rw0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 140.690 233.500 140.830 233.920 ; + END + END rw0_rd_out[60] + PIN rw0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 142.990 233.500 143.130 233.920 ; + END + END rw0_rd_out[61] + PIN rw0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 145.290 233.500 145.430 233.920 ; + END + END rw0_rd_out[62] + PIN rw0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 147.590 233.500 147.730 233.920 ; + END + END rw0_rd_out[63] + PIN rw0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 199.770 0.900 200.070 ; + END + END rw0_addr_in[0] + PIN rw0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 205.890 0.900 206.190 ; + END + END rw0_addr_in[1] + PIN rw0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 0.000 212.010 0.900 212.310 ; + END + END rw0_addr_in[2] + PIN rw0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 199.770 189.980 200.070 ; + END + END rw0_addr_in[3] + PIN rw0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 205.890 189.980 206.190 ; + END + END rw0_addr_in[4] + PIN rw0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met3 ; + RECT 189.080 212.010 189.980 212.310 ; + END + END rw0_addr_in[5] + PIN rw0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 149.890 233.500 150.030 233.920 ; + END + END rw0_we_in + PIN rw0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 152.190 233.500 152.330 233.920 ; + END + END rw0_ce_in + PIN rw0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER met2 ; + RECT 154.490 233.500 154.630 233.920 ; + END + END rw0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met4 ; + RECT 2.160 4.080 3.360 229.840 ; + RECT 13.040 4.080 14.240 229.840 ; + RECT 23.920 4.080 25.120 229.840 ; + RECT 34.800 4.080 36.000 229.840 ; + RECT 45.680 4.080 46.880 229.840 ; + RECT 56.560 4.080 57.760 229.840 ; + RECT 67.440 4.080 68.640 229.840 ; + RECT 78.320 4.080 79.520 229.840 ; + RECT 89.200 4.080 90.400 229.840 ; + RECT 100.080 4.080 101.280 229.840 ; + RECT 110.960 4.080 112.160 229.840 ; + RECT 121.840 4.080 123.040 229.840 ; + RECT 132.720 4.080 133.920 229.840 ; + RECT 143.600 4.080 144.800 229.840 ; + RECT 154.480 4.080 155.680 229.840 ; + RECT 165.360 4.080 166.560 229.840 ; + RECT 176.240 4.080 177.440 229.840 ; + RECT 187.120 4.080 188.320 229.840 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met4 ; + RECT 2.160 4.080 3.360 229.840 ; + RECT 13.040 4.080 14.240 229.840 ; + RECT 23.920 4.080 25.120 229.840 ; + RECT 34.800 4.080 36.000 229.840 ; + RECT 45.680 4.080 46.880 229.840 ; + RECT 56.560 4.080 57.760 229.840 ; + RECT 67.440 4.080 68.640 229.840 ; + RECT 78.320 4.080 79.520 229.840 ; + RECT 89.200 4.080 90.400 229.840 ; + RECT 100.080 4.080 101.280 229.840 ; + RECT 110.960 4.080 112.160 229.840 ; + RECT 121.840 4.080 123.040 229.840 ; + RECT 132.720 4.080 133.920 229.840 ; + RECT 143.600 4.080 144.800 229.840 ; + RECT 154.480 4.080 155.680 229.840 ; + RECT 165.360 4.080 166.560 229.840 ; + RECT 176.240 4.080 177.440 229.840 ; + RECT 187.120 4.080 188.320 229.840 ; + END + END VDD + OBS + LAYER met1 ; + RECT 0 0 189.980 233.920 ; + LAYER met2 ; + RECT 0 0 189.980 233.920 ; + LAYER met3 ; + RECT 0 0 189.980 233.920 ; + LAYER met4 ; + RECT 0 0 189.980 233.920 ; + END +END fakeram_64x64_1rw + +END LIBRARY diff --git a/designs/sky130hd/SYNtzulA/sram/lib/fakeram_48x256_1rw.lib b/designs/sky130hd/SYNtzulA/sram/lib/fakeram_48x256_1rw.lib new file mode 100644 index 0000000..392459a --- /dev/null +++ b/designs/sky130hd/SYNtzulA/sram/lib/fakeram_48x256_1rw.lib @@ -0,0 +1,468 @@ +library(fakeram_48x256_1rw) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-25 02:05:06Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 1.8; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 1.8; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 1.110; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_48x256_1rw_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_48x256_1rw_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_48x256_1rw_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_48x256_1rw_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_48x256_1rw_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_48x256_1rw_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 48; + bit_from : 47; + bit_to : 0 ; + downto : true ; + } + type (fakeram_48x256_1rw_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } + type (fakeram_48x256_1rw_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_48x256_1rw) { + area : 121391.424; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 48; + } + pin(rw0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.440 ; + internal_power(){ + rise_power(fakeram_48x256_1rw_energy_template_clkslew) { + index_1 ("0.044, 1.110"); + values ("22.354, 22.354") + } + fall_power(fakeram_48x256_1rw_energy_template_clkslew) { + index_1 ("0.044, 1.110"); + values ("22.354, 22.354") + } + } + } + + bus(rw0_rd_out) { + bus_type : fakeram_48x256_1rw_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "rw0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_48x256_1rw_mem_out_delay_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.005, 0.500"); + values ( \ + "0.621, 0.621", \ + "0.621, 0.621" \ + ) + } + cell_fall(fakeram_48x256_1rw_mem_out_delay_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.005, 0.500"); + values ( \ + "0.621, 0.621", \ + "0.621, 0.621" \ + ) + } + rise_transition(fakeram_48x256_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.044, 1.110") + } + fall_transition(fakeram_48x256_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.044, 1.110") + } + } + } + pin(rw0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_48x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.224, 0.224") + } + fall_power(fakeram_48x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.224, 0.224") + } + } + } + pin(rw0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_48x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.224, 0.224") + } + fall_power(fakeram_48x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.224, 0.224") + } + } + } + bus(rw0_addr_in) { + bus_type : fakeram_48x256_1rw_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_48x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.224, 0.224") + } + fall_power(fakeram_48x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.224, 0.224") + } + } + } + bus(rw0_wd_in) { + bus_type : fakeram_48x256_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_48x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.224, 0.224") + } + fall_power(fakeram_48x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.224, 0.224") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_48x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.224, 0.224") + } + fall_power(fakeram_48x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.224, 0.224") + } + } + } + bus(rw0_wmask_in) { + bus_type : fakeram_48x256_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_48x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_48x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.224, 0.224") + } + fall_power(fakeram_48x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.224, 0.224") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_48x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.224, 0.224") + } + fall_power(fakeram_48x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.224, 0.224") + } + } + } + cell_leakage_power : 179.407; +} + +} diff --git a/designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x1024_1rw.lib b/designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x1024_1rw.lib new file mode 100644 index 0000000..6b0f09a --- /dev/null +++ b/designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x1024_1rw.lib @@ -0,0 +1,468 @@ +library(fakeram_64x1024_1rw) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-25 02:05:08Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 1.8; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 1.8; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 1.110; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_64x1024_1rw_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_64x1024_1rw_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_64x1024_1rw_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_64x1024_1rw_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_64x1024_1rw_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_64x1024_1rw_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x1024_1rw_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 10; + bit_from : 9; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x1024_1rw_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_64x1024_1rw) { + area : 366973.206; + interface_timing : true; + memory() { + type : ram; + address_width : 10; + word_width : 64; + } + pin(rw0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.537 ; + internal_power(){ + rise_power(fakeram_64x1024_1rw_energy_template_clkslew) { + index_1 ("0.044, 1.110"); + values ("43.468, 43.468") + } + fall_power(fakeram_64x1024_1rw_energy_template_clkslew) { + index_1 ("0.044, 1.110"); + values ("43.468, 43.468") + } + } + } + + bus(rw0_rd_out) { + bus_type : fakeram_64x1024_1rw_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "rw0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_64x1024_1rw_mem_out_delay_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.005, 0.500"); + values ( \ + "0.658, 0.658", \ + "0.658, 0.658" \ + ) + } + cell_fall(fakeram_64x1024_1rw_mem_out_delay_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.005, 0.500"); + values ( \ + "0.658, 0.658", \ + "0.658, 0.658" \ + ) + } + rise_transition(fakeram_64x1024_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.044, 1.110") + } + fall_transition(fakeram_64x1024_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.044, 1.110") + } + } + } + pin(rw0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x1024_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.435, 0.435") + } + fall_power(fakeram_64x1024_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.435, 0.435") + } + } + } + pin(rw0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x1024_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.435, 0.435") + } + fall_power(fakeram_64x1024_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.435, 0.435") + } + } + } + bus(rw0_addr_in) { + bus_type : fakeram_64x1024_1rw_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x1024_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.435, 0.435") + } + fall_power(fakeram_64x1024_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.435, 0.435") + } + } + } + bus(rw0_wd_in) { + bus_type : fakeram_64x1024_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_64x1024_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.435, 0.435") + } + fall_power(fakeram_64x1024_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.435, 0.435") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_64x1024_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.435, 0.435") + } + fall_power(fakeram_64x1024_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.435, 0.435") + } + } + } + bus(rw0_wmask_in) { + bus_type : fakeram_64x1024_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x1024_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_64x1024_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.435, 0.435") + } + fall_power(fakeram_64x1024_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.435, 0.435") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_64x1024_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.435, 0.435") + } + fall_power(fakeram_64x1024_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.435, 0.435") + } + } + } + cell_leakage_power : 751.101; +} + +} diff --git a/designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x2048_1rw.lib b/designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x2048_1rw.lib new file mode 100644 index 0000000..69dbeba --- /dev/null +++ b/designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x2048_1rw.lib @@ -0,0 +1,468 @@ +library(fakeram_64x2048_1rw) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-25 02:05:09Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 1.8; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 1.8; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 1.110; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_64x2048_1rw_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_64x2048_1rw_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_64x2048_1rw_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_64x2048_1rw_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_64x2048_1rw_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_64x2048_1rw_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x2048_1rw_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 11; + bit_from : 10; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x2048_1rw_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_64x2048_1rw) { + area : 682854.912; + interface_timing : true; + memory() { + type : ram; + address_width : 11; + word_width : 64; + } + pin(rw0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.595 ; + internal_power(){ + rise_power(fakeram_64x2048_1rw_energy_template_clkslew) { + index_1 ("0.044, 1.110"); + values ("51.484, 51.484") + } + fall_power(fakeram_64x2048_1rw_energy_template_clkslew) { + index_1 ("0.044, 1.110"); + values ("51.484, 51.484") + } + } + } + + bus(rw0_rd_out) { + bus_type : fakeram_64x2048_1rw_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "rw0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_64x2048_1rw_mem_out_delay_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.005, 0.500"); + values ( \ + "0.682, 0.682", \ + "0.682, 0.682" \ + ) + } + cell_fall(fakeram_64x2048_1rw_mem_out_delay_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.005, 0.500"); + values ( \ + "0.682, 0.682", \ + "0.682, 0.682" \ + ) + } + rise_transition(fakeram_64x2048_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.044, 1.110") + } + fall_transition(fakeram_64x2048_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.044, 1.110") + } + } + } + pin(rw0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x2048_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.515, 0.515") + } + fall_power(fakeram_64x2048_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.515, 0.515") + } + } + } + pin(rw0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x2048_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.515, 0.515") + } + fall_power(fakeram_64x2048_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.515, 0.515") + } + } + } + bus(rw0_addr_in) { + bus_type : fakeram_64x2048_1rw_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x2048_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.515, 0.515") + } + fall_power(fakeram_64x2048_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.515, 0.515") + } + } + } + bus(rw0_wd_in) { + bus_type : fakeram_64x2048_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_64x2048_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.515, 0.515") + } + fall_power(fakeram_64x2048_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.515, 0.515") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_64x2048_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.515, 0.515") + } + fall_power(fakeram_64x2048_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.515, 0.515") + } + } + } + bus(rw0_wmask_in) { + bus_type : fakeram_64x2048_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x2048_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_64x2048_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.515, 0.515") + } + fall_power(fakeram_64x2048_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.515, 0.515") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_64x2048_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.515, 0.515") + } + fall_power(fakeram_64x2048_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.515, 0.515") + } + } + } + cell_leakage_power : 1373.360; +} + +} diff --git a/designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x256_1rw.lib b/designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x256_1rw.lib new file mode 100644 index 0000000..78ba4f4 --- /dev/null +++ b/designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x256_1rw.lib @@ -0,0 +1,468 @@ +library(fakeram_64x256_1rw) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-25 02:05:06Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 1.8; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 1.8; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 1.110; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_64x256_1rw_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_64x256_1rw_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_64x256_1rw_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_64x256_1rw_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_64x256_1rw_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_64x256_1rw_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x256_1rw_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x256_1rw_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_64x256_1rw) { + area : 162110.477; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 64; + } + pin(rw0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.595 ; + internal_power(){ + rise_power(fakeram_64x256_1rw_energy_template_clkslew) { + index_1 ("0.044, 1.110"); + values ("21.113, 21.113") + } + fall_power(fakeram_64x256_1rw_energy_template_clkslew) { + index_1 ("0.044, 1.110"); + values ("21.113, 21.113") + } + } + } + + bus(rw0_rd_out) { + bus_type : fakeram_64x256_1rw_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "rw0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_64x256_1rw_mem_out_delay_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.005, 0.500"); + values ( \ + "0.558, 0.558", \ + "0.558, 0.558" \ + ) + } + cell_fall(fakeram_64x256_1rw_mem_out_delay_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.005, 0.500"); + values ( \ + "0.558, 0.558", \ + "0.558, 0.558" \ + ) + } + rise_transition(fakeram_64x256_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.044, 1.110") + } + fall_transition(fakeram_64x256_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.044, 1.110") + } + } + } + pin(rw0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.211, 0.211") + } + fall_power(fakeram_64x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.211, 0.211") + } + } + } + pin(rw0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.211, 0.211") + } + fall_power(fakeram_64x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.211, 0.211") + } + } + } + bus(rw0_addr_in) { + bus_type : fakeram_64x256_1rw_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.211, 0.211") + } + fall_power(fakeram_64x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.211, 0.211") + } + } + } + bus(rw0_wd_in) { + bus_type : fakeram_64x256_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_64x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.211, 0.211") + } + fall_power(fakeram_64x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.211, 0.211") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_64x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.211, 0.211") + } + fall_power(fakeram_64x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.211, 0.211") + } + } + } + bus(rw0_wmask_in) { + bus_type : fakeram_64x256_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_64x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.211, 0.211") + } + fall_power(fakeram_64x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.211, 0.211") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_64x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.211, 0.211") + } + fall_power(fakeram_64x256_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.211, 0.211") + } + } + } + cell_leakage_power : 264.800; +} + +} diff --git a/designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x512_1rw.lib b/designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x512_1rw.lib new file mode 100644 index 0000000..b4dd97e --- /dev/null +++ b/designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x512_1rw.lib @@ -0,0 +1,468 @@ +library(fakeram_64x512_1rw) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-25 02:05:07Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 1.8; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 1.8; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 1.110; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_64x512_1rw_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_64x512_1rw_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_64x512_1rw_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_64x512_1rw_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_64x512_1rw_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_64x512_1rw_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x512_1rw_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 9; + bit_from : 8; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x512_1rw_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_64x512_1rw) { + area : 208319.795; + interface_timing : true; + memory() { + type : ram; + address_width : 9; + word_width : 64; + } + pin(rw0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.500 ; + internal_power(){ + rise_power(fakeram_64x512_1rw_energy_template_clkslew) { + index_1 ("0.044, 1.110"); + values ("41.769, 41.769") + } + fall_power(fakeram_64x512_1rw_energy_template_clkslew) { + index_1 ("0.044, 1.110"); + values ("41.769, 41.769") + } + } + } + + bus(rw0_rd_out) { + bus_type : fakeram_64x512_1rw_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "rw0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_64x512_1rw_mem_out_delay_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.005, 0.500"); + values ( \ + "0.686, 0.686", \ + "0.686, 0.686" \ + ) + } + cell_fall(fakeram_64x512_1rw_mem_out_delay_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.005, 0.500"); + values ( \ + "0.686, 0.686", \ + "0.686, 0.686" \ + ) + } + rise_transition(fakeram_64x512_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.044, 1.110") + } + fall_transition(fakeram_64x512_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.044, 1.110") + } + } + } + pin(rw0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x512_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.418, 0.418") + } + fall_power(fakeram_64x512_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.418, 0.418") + } + } + } + pin(rw0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x512_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.418, 0.418") + } + fall_power(fakeram_64x512_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.418, 0.418") + } + } + } + bus(rw0_addr_in) { + bus_type : fakeram_64x512_1rw_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x512_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.418, 0.418") + } + fall_power(fakeram_64x512_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.418, 0.418") + } + } + } + bus(rw0_wd_in) { + bus_type : fakeram_64x512_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_64x512_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.418, 0.418") + } + fall_power(fakeram_64x512_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.418, 0.418") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_64x512_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.418, 0.418") + } + fall_power(fakeram_64x512_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.418, 0.418") + } + } + } + bus(rw0_wmask_in) { + bus_type : fakeram_64x512_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_64x512_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.418, 0.418") + } + fall_power(fakeram_64x512_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.418, 0.418") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_64x512_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.418, 0.418") + } + fall_power(fakeram_64x512_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.418, 0.418") + } + } + } + cell_leakage_power : 420.368; +} + +} diff --git a/designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x64_1rw.lib b/designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x64_1rw.lib new file mode 100644 index 0000000..57df18f --- /dev/null +++ b/designs/sky130hd/SYNtzulA/sram/lib/fakeram_64x64_1rw.lib @@ -0,0 +1,468 @@ +library(fakeram_64x64_1rw) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-25 02:05:05Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 1.8; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 1.8; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 1.110; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_64x64_1rw_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_64x64_1rw_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_64x64_1rw_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_64x64_1rw_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_64x64_1rw_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_64x64_1rw_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x64_1rw_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x64_1rw_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_64x64_1rw) { + area : 44440.122; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 64; + } + pin(rw0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.394 ; + internal_power(){ + rise_power(fakeram_64x64_1rw_energy_template_clkslew) { + index_1 ("0.044, 1.110"); + values ("15.950, 15.950") + } + fall_power(fakeram_64x64_1rw_energy_template_clkslew) { + index_1 ("0.044, 1.110"); + values ("15.950, 15.950") + } + } + } + + bus(rw0_rd_out) { + bus_type : fakeram_64x64_1rw_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "rw0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_64x64_1rw_mem_out_delay_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.005, 0.500"); + values ( \ + "0.567, 0.567", \ + "0.567, 0.567" \ + ) + } + cell_fall(fakeram_64x64_1rw_mem_out_delay_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.005, 0.500"); + values ( \ + "0.567, 0.567", \ + "0.567, 0.567" \ + ) + } + rise_transition(fakeram_64x64_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.044, 1.110") + } + fall_transition(fakeram_64x64_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.044, 1.110") + } + } + } + pin(rw0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x64_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.160, 0.160") + } + fall_power(fakeram_64x64_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.160, 0.160") + } + } + } + pin(rw0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x64_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.160, 0.160") + } + fall_power(fakeram_64x64_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.160, 0.160") + } + } + } + bus(rw0_addr_in) { + bus_type : fakeram_64x64_1rw_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x64_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.160, 0.160") + } + fall_power(fakeram_64x64_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.160, 0.160") + } + } + } + bus(rw0_wd_in) { + bus_type : fakeram_64x64_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_64x64_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.160, 0.160") + } + fall_power(fakeram_64x64_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.160, 0.160") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_64x64_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.160, 0.160") + } + fall_power(fakeram_64x64_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.160, 0.160") + } + } + } + bus(rw0_wmask_in) { + bus_type : fakeram_64x64_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1rw_constraint_template) { + index_1 ("0.044, 1.110"); + index_2 ("0.044, 1.110"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_64x64_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.160, 0.160") + } + fall_power(fakeram_64x64_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.160, 0.160") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_64x64_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.160, 0.160") + } + fall_power(fakeram_64x64_1rw_energy_template_sigslew) { + index_1 ("0.044, 1.110"); + values ("0.160, 0.160") + } + } + } + cell_leakage_power : 79.056; +} + +} diff --git a/designs/src/SYNtzulA/BUILD.bazel b/designs/src/SYNtzulA/BUILD.bazel new file mode 100644 index 0000000..fe429b2 --- /dev/null +++ b/designs/src/SYNtzulA/BUILD.bazel @@ -0,0 +1,66 @@ +filegroup( + name = "rtl_release", + srcs = [ + "SYNtzulATop.v", + "macros.v", + "config.txt", + ], +) + +# update-rtl mode: init submodule, patch, sv2v, cat plain .v files +genrule( + name = "rtl_dev_gen", + srcs = [], + outs = [ + "dev_SYNtzulATop.v", + "dev_macros.v", + ], + local = True, + cmd = """ + WORKSPACE_ROOT=$$(readlink -f $(location //:tools/update_rtl.sh) | sed 's|/tools/update_rtl.sh||') + cd $$WORKSPACE_ROOT + + DESIGN_SRC=designs/src/SYNtzulA + DEV_DIR=$$DESIGN_SRC/dev + REPO_DIR=$$DEV_DIR/repo + RTL_DIR=$$REPO_DIR/rtl + + # Init submodule + git submodule update --init $$REPO_DIR >&2 + + # Setup + bash $$DEV_DIR/setup.sh >&2 + + # Patch (ignore already-applied) + patch -p1 -N --silent --directory=$$REPO_DIR \ + < $$DEV_DIR/patch-synsnn.patch > /dev/null 2>&1 || [ $$? -eq 1 ] + + # define.v first so macros are visible to everything after + cat $$RTL_DIR/define.v > $(location dev_SYNtzulATop.v) + + # sv2v: convert .sv files, -I so sv2v resolves includes during conversion + SV_FILES=$$(find $$RTL_DIR -mindepth 2 -maxdepth 2 -name "*.sv") + $$DEV_DIR/sv2v --top SYNtzulATop -w stdout \ + -I $$RTL_DIR \ + $$SV_FILES \ + >> $(location dev_SYNtzulATop.v) + + # Append plain .v files (excluding define.v at rtl root) + V_FILES=$$(find $$RTL_DIR -mindepth 2 -maxdepth 2 -name "*.v") + for f in $$V_FILES; do + cat $$f >> $(location dev_SYNtzulATop.v) + done + + cp $$DESIGN_SRC/macros.v $(location dev_macros.v) + """, + tools = ["//:tools/update_rtl.sh"], +) + +alias( + name = "rtl", + actual = select({ + "//:update_rtl": ":rtl_dev_gen", + "//conditions:default": ":rtl_release", + }), + visibility = ["//visibility:public"], +) \ No newline at end of file diff --git a/designs/src/SYNtzulA/SYNtzulATop.v b/designs/src/SYNtzulA/SYNtzulATop.v new file mode 100644 index 0000000..650fb3b --- /dev/null +++ b/designs/src/SYNtzulA/SYNtzulATop.v @@ -0,0 +1,10177 @@ +`default_nettype wire +`ifdef SIM //se sto simulando + `define POTENTIAL + //`define IEEG + `define EMG + + `ifdef IEEG + `define PATH "ieeg" + `define CONFIG_PATH "rtl/config/ieeg/config.txt" + `elsif EMG + `define PATH "emg" + `define CONFIG_PATH "rtl/config/emg/config.txt" + `endif + + //`define CONFIGURABILITY + `define ACCESSIBILITY + //`define UART_HP + `define LOW_POWER + +`else //se sto facendo la sintesi con ORFS + `define RTL + `define POTENTIAL + //`define IEEG + `define EMG + + `ifdef IEEG + `define PATH "ieeg" + `define CONFIG_PATH "rtl/config/ieeg/config.txt" + `elsif EMG + `define PATH "emg" + `define CONFIG_PATH "rtl/config/emg/config.txt" + `endif + + //`define CONFIGURABILITY + `define ACCESSIBILITY + //`define UART_HP + `define LOW_POWER +`endif +`define FUNCTIONAL +(* use_dsp = "yes" *) module accumulator ( + clk, + ce1, + ce2, + ce3, + rst, + clear_and_go, + clear, + a, + b, + presubmult_out +); + parameter SIZEIN = 16; + input clk; + input ce1; + input ce2; + input ce3; + input rst; + input clear_and_go; + input clear; + input signed [SIZEIN - 1:0] a; + input signed [SIZEIN - 1:0] b; + output wire signed [(2 * SIZEIN) - 1:0] presubmult_out; + reg signed [SIZEIN - 1:0] a_reg; + reg signed [SIZEIN - 1:0] b_reg; + reg signed [SIZEIN:0] add_reg; + reg signed [2 * SIZEIN:0] p_reg; + always @(posedge clk) + if (rst | clear) begin + a_reg <= 0; + b_reg <= 0; + add_reg <= 0; + p_reg <= 0; + end + else begin + if (ce1) begin + a_reg <= a; + b_reg <= b; + end + if (ce2) + add_reg <= a_reg + b_reg; + if (ce3) begin + if (clear_and_go) + p_reg <= add_reg; + else + p_reg <= p_reg + add_reg; + end + end + assign presubmult_out = p_reg; +endmodule +(* use_dsp = "simd" *) module adder_simd ( + clk, + en, + a_0, + a_1, + b_0, + b_1, + out_0, + out_1 +); + parameter N = 2; + parameter W = 15; + input clk; + input en; + input [W - 1:0] a_0; + input [W - 1:0] a_1; + input [W - 1:0] b_0; + input [W - 1:0] b_1; + output reg signed [W:0] out_0; + output reg signed [W:0] out_1; + integer i; + reg signed [W - 1:0] a_r [N - 1:0]; + reg signed [W - 1:0] b_r [N - 1:0]; + always @(posedge clk) + if (en) begin + a_r[0] <= a_0; + b_r[0] <= b_0; + out_0 <= a_r[0] + b_r[0]; + a_r[1] <= a_1; + b_r[1] <= b_1; + out_1 <= a_r[1] + b_r[1]; + end +endmodule +module bram_fifo ( + clk, + rst, + DI, + rden, + wren, + DO +); + parameter DATA_WIDTH = 25; + parameter DEPTH = 256; + input clk; + input rst; + input [DATA_WIDTH - 1:0] DI; + input rden; + input wren; + output wire [DATA_WIDTH - 1:0] DO; + function integer clogb2; + input integer depth; + for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1) + depth = depth >> 1; + endfunction + reg [clogb2(DEPTH - 1) - 1:0] rd_cnt; + reg [clogb2(DEPTH - 1) - 1:0] wr_cnt; + always @(posedge clk) + if (rst) + rd_cnt <= 0; + else if (rden) begin + if (rd_cnt < (DEPTH - 1)) + rd_cnt <= rd_cnt + 1'b1; + else + rd_cnt <= 0; + end + always @(posedge clk) + if (rst) + wr_cnt <= 0; + else if (wren) begin + if (wr_cnt < (DEPTH - 1)) + wr_cnt <= wr_cnt + 1'b1; + else + wr_cnt <= 0; + end + ihp_dualport_256x48_dualmem #( + .RAM_WIDTH(DATA_WIDTH), + .RAM_DEPTH(DEPTH), + .RAM_PERFORMANCE("LOW_LATENCY"), + .INIT_FILE("") + ) fifo_ram( + .addra(wr_cnt), + .addrb(rd_cnt), + .dina(DI), + .clk(clk), + .wea(wren), + .ena(wren), + .enb(rden), + .rst(rst), + .regceb(1'b1), + .doutb(DO) + ); +endmodule +module BRAM_singlePort_readFirst ( + addra, + addrb, + dina, + clk, + wea, + ena, + enb, + rst, + regceb, + doutb +); + parameter RAM_WIDTH = 4; + parameter RAM_DEPTH = 64; + parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE"; + parameter INIT_FILE = ""; + function integer clogb2; + input integer depth; + for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1) + depth = depth >> 1; + endfunction + input [clogb2(RAM_DEPTH - 1) - 1:0] addra; + input [clogb2(RAM_DEPTH - 1) - 1:0] addrb; + input [RAM_WIDTH - 1:0] dina; + input clk; + input wea; + input ena; + input enb; + input rst; + input regceb; + output wire [RAM_WIDTH - 1:0] doutb; + reg [RAM_WIDTH - 1:0] ram [RAM_DEPTH - 1:0]; + reg [RAM_WIDTH - 1:0] ram_data_b = {RAM_WIDTH {1'b0}}; + genvar _gv_idx_1; + generate + for (_gv_idx_1 = 0; _gv_idx_1 < 16; _gv_idx_1 = _gv_idx_1 + 1) begin : genblk1 + localparam idx = _gv_idx_1; + wire [RAM_WIDTH - 1:0] tmp; + assign tmp = ram[idx]; + end + if (INIT_FILE != "") begin : use_init_file + initial $readmemh(INIT_FILE, ram, 0, RAM_DEPTH - 1); + end + else begin : init_bram_to_zero + integer ram_index; + initial for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1) + ram[ram_index] = {RAM_WIDTH {1'b0}}; + end + endgenerate + always @(posedge clk) + if (ena) begin + if (wea) + ram[addra] <= dina; + end + always @(posedge clk) + if (enb) + ram_data_b <= ram[addrb]; + generate + if (RAM_PERFORMANCE == "LOW_LATENCY") begin : no_output_register + assign doutb = ram_data_b; + end + else begin : output_register + reg [RAM_WIDTH - 1:0] doutb_reg = {RAM_WIDTH {1'b0}}; + always @(posedge clk) + if (rst) + doutb_reg <= {RAM_WIDTH {1'b0}}; + else if (regceb) + doutb_reg <= ram_data_b; + assign doutb = doutb_reg; + end + endgenerate +endmodule +module conv ( + clk, + rst, + en, + acc_clear_and_go, + acc_clear, + weights_in, + spikes, + out, + valid +); + parameter WEIGHTS = 4; + parameter DATA_WIDTH = 15; + input clk; + input rst; + input en; + input acc_clear_and_go; + input acc_clear; + input signed [(WEIGHTS * DATA_WIDTH) - 1:0] weights_in; + input [WEIGHTS - 1:0] spikes; + output wire [(2 * (DATA_WIDTH + 1)) - 1:0] out; + output wire valid; + localparam SUM = WEIGHTS / 2; + localparam PIPE = 5; + wire signed [DATA_WIDTH - 1:0] weights [WEIGHTS - 1:0]; + assign weights[0] = weights_in[DATA_WIDTH - 1:0]; + assign weights[1] = weights_in[(2 * DATA_WIDTH) - 1:DATA_WIDTH]; + assign weights[2] = weights_in[(3 * DATA_WIDTH) - 1:2 * DATA_WIDTH]; + assign weights[3] = weights_in[(4 * DATA_WIDTH) - 1:3 * DATA_WIDTH]; + reg [4:0] en_shift; + integer i; + always @(posedge clk) + if (rst) + en_shift <= 0; + else begin + en_shift[0] <= en; + for (i = 1; i < PIPE; i = i + 1) + en_shift[i] <= en_shift[i - 1]; + end + wire signed [DATA_WIDTH - 1:0] weights_a [SUM - 1:0]; + wire signed [DATA_WIDTH - 1:0] weights_b [SUM - 1:0]; + assign weights_a[0] = weights[2]; + assign weights_a[1] = weights[3]; + assign weights_b[0] = weights[0]; + assign weights_b[1] = weights[1]; + wire [DATA_WIDTH - 1:0] spike_a [SUM - 1:0]; + wire [DATA_WIDTH - 1:0] spike_b [SUM - 1:0]; + assign spike_a[1] = {DATA_WIDTH {spikes[WEIGHTS - 1]}}; + assign spike_a[0] = {DATA_WIDTH {spikes[WEIGHTS - 2]}}; + assign spike_b[1] = {DATA_WIDTH {spikes[WEIGHTS - 3]}}; + assign spike_b[0] = {DATA_WIDTH {spikes[WEIGHTS - 4]}}; + wire [DATA_WIDTH - 1:0] anded_weights_a [SUM - 1:0]; + wire [DATA_WIDTH - 1:0] anded_weights_b [SUM - 1:0]; + assign anded_weights_a[0] = weights_a[0] & spike_a[0]; + assign anded_weights_a[1] = weights_a[1] & spike_a[1]; + assign anded_weights_b[0] = weights_b[0] & spike_b[0]; + assign anded_weights_b[1] = weights_b[1] & spike_b[1]; + wire signed [DATA_WIDTH:0] double_adder_out [SUM - 1:0]; + wire double_adder_en; + assign double_adder_en = en | en_shift[0]; + adder_simd #( + .N(SUM), + .W(DATA_WIDTH) + ) double_adder( + .clk(clk), + .en(double_adder_en), + .a_0(anded_weights_a[0]), + .a_1(anded_weights_a[1]), + .b_0(anded_weights_b[0]), + .b_1(anded_weights_b[1]), + .out_0(double_adder_out[0]), + .out_1(double_adder_out[1]) + ); + wire [(2 * (DATA_WIDTH + 1)) - 1:0] acc_out; + accumulator #(.SIZEIN(DATA_WIDTH + 1)) acc( + .clk(clk), + .ce1(en_shift[1]), + .ce2(en_shift[2]), + .ce3(en_shift[3]), + .rst(rst), + .clear_and_go(acc_clear_and_go), + .clear(acc_clear), + .a(double_adder_out[0]), + .b(double_adder_out[1]), + .presubmult_out(acc_out) + ); + assign valid = en_shift[4]; + assign out = (valid ? acc_out : 0); +endmodule +module encoding_slot ( + clk, + rst, + en, + data_in, + detect, + spike_bin, + valid_bin, + active_group_out_bin, + inference_done, + o_sample_mem_dat, + i_sample_mem_adr, + i_sample_mem_rd_en, + i_sample_mem_wr_en, + i_sample_mem_dat, + bypass, + enb_debug +); + parameter BYPASS = 0; + parameter CHANNELS = 128; + parameter ORDER = 2; + parameter WINDOW = 8192; + parameter REF_PERIOD = 16; + parameter DW = 15; + input clk; + input rst; + input en; + input signed [15:0] data_in; + input detect; + output reg [3:0] spike_bin; + output reg valid_bin; + output reg active_group_out_bin; + input inference_done; + output wire [15:0] o_sample_mem_dat; + function integer clogb2; + input integer depth; + for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1) + depth = depth >> 1; + endfunction + input wire [clogb2(CHANNELS - 1) - 1:0] i_sample_mem_adr; + input wire i_sample_mem_rd_en; + input wire i_sample_mem_wr_en; + input wire [15:0] i_sample_mem_dat; + input wire bypass; + input wire enb_debug; + wire signed [DW - 1:0] data_out_buffer; + wire input_buffer_valid; + input_buffer #( + .CHANNELS(CHANNELS), + .DW(DW) + ) input_buffer_i( + .clk(clk), + .rst(rst), + .en(en), + .data_in(data_in), + .valid(input_buffer_valid), + .data_out(data_out_buffer), + .external_access_en(i_sample_mem_rd_en), + .external_addr(i_sample_mem_adr), + .external_data_out(o_sample_mem_dat), + .external_access_wren(i_sample_mem_wr_en), + .external_data_in(i_sample_mem_dat), + .enb_debug(enb_debug) + ); + wire [3:0] spike_bin_int; + wire valid_bin_int; + wire active_group_out_bin_int; + generate + if (BYPASS) begin : genblk1 + always @(posedge clk) begin + spike_bin <= spike_bin_int; + valid_bin <= valid_bin_int; + active_group_out_bin <= active_group_out_bin_int; + end + end + else begin : genblk1 + always @(posedge clk) + if (bypass) begin + spike_bin <= data_out_buffer[3:0]; + valid_bin <= input_buffer_valid; + active_group_out_bin <= |data_out_buffer[3:0]; + end + else begin + spike_bin <= spike_bin_int; + valid_bin <= valid_bin_int; + active_group_out_bin <= active_group_out_bin_int; + end + end + endgenerate +endmodule +module encoding_slot_emg ( + clk, + rst, + en, + data_in, + spike_bin, + valid_bin, + active_group_out_bin +); + parameter CHANNELS = 128; + parameter DW = 8; + input clk; + input rst; + input en; + input signed [DW - 1:0] data_in; + output wire [3:0] spike_bin; + output wire valid_bin; + output wire active_group_out_bin; + localparam SPIKE = 4; + function integer clogb2; + input integer depth; + for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1) + depth = depth >> 1; + endfunction + localparam CHANNELS_L2 = clogb2(CHANNELS - 1); + wire [1:0] dm_spike; + wire pos_spike; + wire neg_spike; + wire dm_valid; + delta_modulator_multichannel #( + .CHANNELS(CHANNELS), + .WIDTH(DW) + ) delta_modulator_1( + .clk(clk), + .rst(rst), + .en(en), + .samples(data_in), + .pos_spike(pos_spike), + .neg_spike(neg_spike), + .valid(dm_valid) + ); + wire ag1; + wire ag2; + wire [1:0] s2p_out_1; + wire [1:0] s2p_out_2; + s2p #(.P(2)) s2p_1( + .clk(clk), + .rst(rst), + .en(dm_valid), + .spike_s(pos_spike), + .spike_p(s2p_out_1), + .valid(valid_bin), + .active_group(ag1) + ); + s2p #(.P(2)) s2p_2( + .clk(clk), + .rst(rst), + .en(dm_valid), + .spike_s(neg_spike), + .spike_p(s2p_out_2), + .valid(), + .active_group(ag2) + ); + assign active_group_out_bin = ag1 | ag2; + assign spike_bin = {s2p_out_1[1], s2p_out_2[1], s2p_out_1[0], s2p_out_2[0]}; +endmodule +module input_buffer ( + clk, + rst, + en, + data_in, + valid, + data_out, + external_access_en, + external_addr, + external_data_out, + external_access_wren, + external_data_in, + enb_debug +); + parameter CHANNELS = 128; + parameter DW = 15; + input clk; + input rst; + input en; + input signed [15:0] data_in; + output reg valid; + output wire signed [DW - 1:0] data_out; + input external_access_en; + function integer clogb2; + input integer depth; + for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1) + depth = depth >> 1; + endfunction + input [clogb2(CHANNELS - 1) - 1:0] external_addr; + output wire signed [15:0] external_data_out; + input external_access_wren; + input signed [15:0] external_data_in; + input enb_debug; + localparam SIMD = (DW == 8 ? 1 : 0); + localparam CHANNELS_INT = (SIMD ? CHANNELS / 2 : CHANNELS); + reg [clogb2(CHANNELS_INT - 1) - 1:0] pointer; + reg read_flag; + reg slow_stream_out; + generate + if (SIMD) begin : genblk1 + always @(posedge clk) + if (rst) + slow_stream_out <= 0; + else if (read_flag) + slow_stream_out <= ~slow_stream_out; + end + else begin : genblk1 + always @(*) slow_stream_out = 1; + end + endgenerate + wire [15:0] data_in_mux; + assign data_in_mux = (external_access_wren ? external_data_in : data_in); + wire wr_en; + assign wr_en = en | external_access_wren; + wire [15:0] mem_out; + wire [clogb2(CHANNELS_INT - 1) - 1:0] adr; + ihp_single_port_256x48 #( + .RAM_WIDTH(16), + .RAM_DEPTH(CHANNELS_INT), + .RAM_PERFORMANCE("LOW_LATENCY"), + .INIT_FILE("") + ) buffer( + .addra(adr), + .addrb(adr), + .dina(data_in_mux), + .clk(clk), + .wea(wr_en), + .ena(wr_en), + .enb(enb_debug), + .rst(rst), + .regceb(1'b1), + .doutb(mem_out) + ); + assign adr = (external_access_en | external_access_wren ? external_addr : pointer); + always @(posedge clk) + if (rst) + pointer <= 0; + else if (wr_en) begin + if (pointer < CHANNELS_INT) + pointer <= pointer + 1'b1; + else + pointer <= 0; + end + else if (read_flag && slow_stream_out) begin + if (pointer < CHANNELS_INT) + pointer <= pointer + 1'b1; + else + pointer <= 0; + end + always @(posedge clk) + if (rst) + read_flag <= 1'b0; + else if (wr_en && (pointer == (CHANNELS_INT - 1))) + read_flag <= 1'b1; + else if ((read_flag && slow_stream_out) && (pointer == (CHANNELS_INT - 1))) + read_flag <= 1'b0; + always @(posedge clk) + if (rst) + valid <= 0; + else + valid <= read_flag; + generate + if (SIMD) begin : genblk2 + assign data_out = (slow_stream_out ? mem_out[15:8] : mem_out[7:0]); + end + else begin : genblk2 + assign data_out = mem_out; + end + endgenerate + assign external_data_out = mem_out; +endmodule +module integrator ( + clk, + rst, + en, + detection, + output_old, + decay, + stimolo, + threshold, + valid, + spike, + output_new +); + parameter WIDTH = 25; + input clk; + input rst; + input en; + input detection; + input [WIDTH - 1:0] output_old; + input [13:0] decay; + input [WIDTH - 1:0] stimolo; + input [WIDTH - 1:0] threshold; + output wire valid; + output wire spike; + output wire [WIDTH - 1:0] output_new; + localparam P_SIZE = WIDTH + 13; + reg signed [WIDTH - 1:0] r_output_old; + reg signed [13:0] r_decay; + reg signed [P_SIZE - 1:0] p; + reg signed [WIDTH - 1:0] p_shift; + reg signed [WIDTH - 1:0] r_stimolo [2:0]; + reg signed [WIDTH - 1:0] r_threshold [3:0]; + (* use_dsp = "yes" *) reg signed [WIDTH - 1:0] comparator_in; + reg [3:0] en_shift; + reg [P_SIZE - 1:0] supporto_1; + reg [P_SIZE - 1:0] supporto_2; + integer i; + always @(posedge clk) + if (rst) begin + en_shift <= 0; + r_output_old <= 0; + r_decay <= 0; + p <= 0; + p_shift <= 0; + comparator_in <= 0; + for (i = 0; i < 4; i = i + 1) + r_threshold[i] <= 0; + for (i = 0; i < 3; i = i + 1) + r_stimolo[i] <= 0; + end + else begin + en_shift[0] <= en; + r_output_old <= output_old; + r_decay <= decay; + r_stimolo[0] <= stimolo; + r_threshold[0] <= threshold; + en_shift[1] <= en_shift[0]; + p <= r_output_old * r_decay; + r_stimolo[1] <= r_stimolo[0]; + r_threshold[1] <= r_threshold[0]; + en_shift[2] <= en_shift[1]; + if (p[P_SIZE - 1]) begin + supporto_1 = ~p + 1'b1; + supporto_2 = supporto_1[P_SIZE - 1:12]; + p_shift <= ~supporto_2 + 1'b1; + end + else + p_shift <= p[P_SIZE - 1:12]; + r_stimolo[2] <= r_stimolo[1]; + r_threshold[2] <= r_threshold[1]; + en_shift[3] <= en_shift[2]; + comparator_in <= p_shift + r_stimolo[2]; + r_threshold[3] <= r_threshold[2]; + end + assign spike = ((comparator_in >= r_threshold[3]) & detection ? 1'b1 : 1'b0); + assign output_new = (spike ? 0 : comparator_in); + assign valid = en_shift[3]; +endmodule +module integrator_and_fifo ( + clk, + rst, + en, + detection, + decay, + stimolo, + threshold, + valid, + spike, + output_new +); + parameter DEPTH = 256; + parameter WIDTH = 25; + input clk; + input rst; + input en; + input detection; + input [13:0] decay; + input [WIDTH - 1:0] stimolo; + input [WIDTH - 1:0] threshold; + output wire valid; + output wire spike; + output wire [WIDTH - 1:0] output_new; + wire [WIDTH - 1:0] output_old; + bram_fifo #( + .DATA_WIDTH(WIDTH), + .DEPTH(DEPTH) + ) fifo_i( + .clk(clk), + .rst(rst), + .DI(output_new), + .rden(en), + .wren(valid), + .DO(output_old) + ); + reg en_d; + reg [WIDTH - 1:0] stimolo_d; + always @(posedge clk) + if (rst) begin + en_d <= 0; + stimolo_d <= 0; + end + else begin + en_d <= en; + if (en) + stimolo_d <= stimolo; + end + integrator #(.WIDTH(WIDTH)) integrator_i( + .clk(clk), + .rst(rst), + .en(en_d), + .detection(detection), + .output_old(output_old), + .decay(decay), + .stimolo(stimolo_d), + .threshold(threshold), + .valid(valid), + .spike(spike), + .output_new(output_new) + ); +endmodule +module layer_lp ( + clk, + rst, + en, + spike_in, + active_group_in, + weight_rd_addr, + acc_clear, + acc_clear_and_go, + convolution_pipe_full, + layer_id, + valid, + spike_out, + active_group_out, + valid_potential, + neuron_lp_voltage, + integrated_neuron, + weight_mem_L1_wren, + weight_mem_L1_wr_addr, + weight_mem_L1_data_in, + weight_mem_L1_data_out, + weight_mem_L1_ena, + weight_mem_L2_wren, + weight_mem_L2_wr_addr, + weight_mem_L2_data_in, + weight_mem_L2_data_out, + weight_mem_L2_ena, + weight_debug, + weight_en_debug, + enb_debug +); + parameter WIDTH = 25; + parameter NEURON = 256; + parameter LAYERS = 4; + parameter WEIGHTS_FILE_1 = "weights_1.txt"; + parameter WEIGHTS_FILE_2 = "weights_2.txt"; + parameter [13:0] current_decay_1 = 0; + parameter [13:0] current_decay_2 = 0; + parameter [13:0] current_decay_3 = 0; + parameter [13:0] current_decay_4 = 0; + parameter [13:0] voltage_decay_1 = 3681; + parameter [13:0] voltage_decay_2 = 3681; + parameter [13:0] voltage_decay_3 = 3681; + parameter [13:0] voltage_decay_4 = 3681; + parameter [WIDTH - 1:0] threshold_1 = 6; + parameter [WIDTH - 1:0] threshold_2 = 6; + parameter [WIDTH - 1:0] threshold_3 = 6; + parameter [WIDTH - 1:0] threshold_4 = 6; + parameter WEIGHT_DEPTH = 8192; + input clk; + input rst; + input en; + input [3:0] spike_in; + input active_group_in; + function integer clogb2; + input integer depth; + for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1) + depth = depth >> 1; + endfunction + input [clogb2(WEIGHT_DEPTH - 1) - 1:0] weight_rd_addr; + input acc_clear; + input acc_clear_and_go; + output wire convolution_pipe_full; + input [clogb2(LAYERS - 1) - 1:0] layer_id; + output wire valid; + output wire [1:0] spike_out; + output wire active_group_out; + output reg valid_potential; + output wire signed [WIDTH - 1:0] neuron_lp_voltage; + output wire integrated_neuron; + input [7:0] weight_mem_L1_wren; + input [clogb2(WEIGHT_DEPTH - 1) - 1:0] weight_mem_L1_wr_addr; + input [15:0] weight_mem_L1_data_in; + output wire [15:0] weight_mem_L1_data_out; + input weight_mem_L1_ena; + input [7:0] weight_mem_L2_wren; + input [clogb2(WEIGHT_DEPTH - 1) - 1:0] weight_mem_L2_wr_addr; + input [15:0] weight_mem_L2_data_in; + output wire [15:0] weight_mem_L2_data_out; + input weight_mem_L2_ena; + output wire [7:0] weight_debug; + output wire weight_en_debug; + input enb_debug; + assign weight_en_debug = en; + assign weight_debug = weight_rd_addr[7:0]; + localparam WEIGHT = 8; + wire signed [31:0] weights; + weights_mem_ihp #( + .RAM_WIDTH(16), + .RAM_DEPTH(WEIGHT_DEPTH) + ) weight_mem( + .addra1(weight_mem_L1_wr_addr), + .dina1(weight_mem_L1_data_in), + .wea1(weight_mem_L1_wren[0]), + .ena1(weight_mem_L1_ena), + .addra2(weight_mem_L2_wr_addr), + .dina2(weight_mem_L2_data_in), + .wea2(weight_mem_L2_wren[0]), + .ena2(weight_mem_L2_ena), + .enb(enb_debug), + .clk(clk), + .rst(rst), + .regceb(1'b1), + .addrb(weight_rd_addr), + .doutb(weights) + ); + wire [17:0] stimulus; + conv #( + .WEIGHTS(4), + .DATA_WIDTH(WEIGHT) + ) conv_i( + .clk(clk), + .rst(rst), + .en(en), + .acc_clear_and_go(acc_clear_and_go), + .acc_clear(acc_clear), + .weights_in(weights), + .spikes(spike_in), + .out(stimulus), + .valid(convolution_pipe_full) + ); + neuron_lp #( + .DEPTH(NEURON), + .WIDTH(WIDTH), + .WEIGHT(WEIGHT), + .LAYERS(LAYERS) + ) neuron_lp_i( + .clk(clk), + .rst(rst), + .en(acc_clear_and_go), + .current_decay_1(current_decay_1), + .voltage_decay_1(voltage_decay_1), + .threshold_1(threshold_1), + .current_decay_2(current_decay_2), + .voltage_decay_2(voltage_decay_2), + .threshold_2(threshold_2), + .current_decay_3(current_decay_3), + .voltage_decay_3(voltage_decay_3), + .threshold_3(threshold_3), + .current_decay_4(current_decay_4), + .voltage_decay_4(voltage_decay_4), + .threshold_4(threshold_4), + .synaptic_current(stimulus), + .layer_id(layer_id), + .valid(valid), + .spike_p(spike_out), + .active_group(active_group_out), + .voltage_ready(integrated_neuron), + .voltage(neuron_lp_voltage) + ); + function integer max; + input integer a; + input integer b; + if (a > b) + max = a; + else + max = b; + endfunction +endmodule +module neuron_lp ( + clk, + rst, + en, + current_decay_1, + voltage_decay_1, + threshold_1, + current_decay_2, + voltage_decay_2, + threshold_2, + current_decay_3, + voltage_decay_3, + threshold_3, + current_decay_4, + voltage_decay_4, + threshold_4, + synaptic_current, + layer_id, + valid, + spike_p, + active_group, + voltage_ready, + voltage +); + parameter DEPTH = 256; + parameter WIDTH = 25; + parameter WEIGHT = 8; + parameter LAYERS = 4; + input clk; + input rst; + input en; + input [13:0] current_decay_1; + input [13:0] voltage_decay_1; + input [WIDTH - 1:0] threshold_1; + input [13:0] current_decay_2; + input [13:0] voltage_decay_2; + input [WIDTH - 1:0] threshold_2; + input [13:0] current_decay_3; + input [13:0] voltage_decay_3; + input [WIDTH - 1:0] threshold_3; + input [13:0] current_decay_4; + input [13:0] voltage_decay_4; + input [WIDTH - 1:0] threshold_4; + input [(2 * (WEIGHT + 1)) - 1:0] synaptic_current; + function integer clogb2; + input integer depth; + for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1) + depth = depth >> 1; + endfunction + input [clogb2(LAYERS - 1) - 1:0] layer_id; + output wire valid; + output wire [1:0] spike_p; + output wire active_group; + output wire voltage_ready; + output wire [WIDTH - 1:0] voltage; + localparam CURRENT_WIDTH = 2 * (WEIGHT + 1); + wire [13:0] current_decay; + wire [13:0] voltage_decay; + wire [WIDTH - 1:0] threshold; + assign current_decay = (layer_id == 0 ? current_decay_1 : (layer_id == 1 ? current_decay_2 : (layer_id == 2 ? current_decay_3 : current_decay_4))); + assign voltage_decay = (layer_id == 0 ? voltage_decay_1 : (layer_id == 1 ? voltage_decay_2 : (layer_id == 2 ? voltage_decay_3 : voltage_decay_4))); + assign threshold = (layer_id == 0 ? threshold_1 : (layer_id == 1 ? threshold_2 : (layer_id == 2 ? threshold_3 : threshold_4))); + wire [WIDTH - 1:0] current; + wire [WIDTH - 1:0] synaptic_current_ext; + wire spike_s; + integrator_and_fifo #( + .DEPTH(DEPTH), + .WIDTH(WIDTH) + ) Voltage_i( + .clk(clk), + .rst(rst), + .en(en), + .detection(1'b1), + .decay(voltage_decay), + .stimolo(synaptic_current), + .threshold(threshold), + .valid(voltage_ready), + .spike(spike_s), + .output_new(voltage) + ); + s2p #(.P(2)) s2p_i( + .clk(clk), + .rst(rst), + .en(voltage_ready), + .spike_s(spike_s), + .spike_p(spike_p), + .valid(valid), + .active_group(active_group) + ); +endmodule +module s2p ( + clk, + rst, + en, + spike_s, + spike_p, + valid, + active_group +); + parameter P = 2; + input clk; + input rst; + input en; + input spike_s; + output reg [P - 1:0] spike_p; + output reg valid; + output reg active_group; + wire end_cnt; + always @(posedge clk) + if (rst) + valid <= 0; + else + valid <= end_cnt; + function integer clogb2; + input integer depth; + for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1) + depth = depth >> 1; + endfunction + reg [clogb2(P - 1) - 1:0] cnt; + always @(posedge clk) + if (rst) + cnt <= 0; + else if (en) + cnt <= cnt + 1'b1; + assign end_cnt = (cnt == (P - 1)) & en; + integer i; + always @(posedge clk) + if (rst) + spike_p <= 0; + else if (en) begin + spike_p[0] <= spike_s; + for (i = 1; i < P; i = i + 1) + spike_p[i] <= spike_p[i - 1]; + end + else if (valid) + spike_p <= 0; + always @(posedge clk) + if (rst) + active_group <= 0; + else if (en) + active_group <= (active_group && ~valid) | spike_s; + else if (valid) + active_group <= 0; +endmodule +module snn_lp ( + clk, + rst, + en, + spike_in, + active_group_in, + valid, + valid_spike, + spike_out, + integrated_neuron, + weight_mem_L1_wren, + weight_mem_L1_wr_addr, + weight_mem_L1_data_in, + weight_mem_L1_data_out, + weight_mem_L1_ena, + weight_mem_L2_wren, + weight_mem_L2_wr_addr, + weight_mem_L2_data_in, + weight_mem_L2_data_out, + weight_mem_L2_ena, + weight_mem_L3_wren, + weight_mem_L3_wr_addr, + weight_mem_L3_data_in, + weight_mem_L3_data_out, + weight_mem_L3_ena, + weight_mem_L4_wren, + weight_mem_L4_wr_addr, + weight_mem_L4_data_in, + weight_mem_L4_data_out, + weight_mem_L4_ena, + o_spike_mem_dat, + i_spike_mem_adr, + i_spike_mem_rd_en, + i_spike_mem_wr_en, + i_spike_mem_dat, + snn_input_channels, + neuron_1, + neuron_2, + neuron_3, + neuron_4, + layers, + output_buffer_ren, + output_buffer_addr, + output_buffer_out, + output_buffer_wr_en_debug, + p1, + p2, + enb_debug +); + parameter WIDTH = 16; + parameter MAX_SYNAPSES = 128; + parameter MAX_NEURONS = 128; + parameter LAYERS = 4; + parameter INPUT_SPIKE_1 = 32; + parameter NEURON_1 = 64; + parameter WEIGHTS_FILE_1 = "weights_1.txt"; + parameter [13:0] current_decay_1 = 0; + parameter [13:0] voltage_decay_1 = 4054; + parameter [WIDTH - 1:0] threshold_1 = 19; + parameter INPUT_SPIKE_2 = NEURON_1; + parameter NEURON_2 = 128; + parameter WEIGHTS_FILE_2 = "weights_2.txt"; + parameter [13:0] current_decay_2 = 0; + parameter [13:0] voltage_decay_2 = 4054; + parameter [WIDTH - 1:0] threshold_2 = 17; + parameter INPUT_SPIKE_3 = NEURON_2; + parameter NEURON_3 = 64; + parameter WEIGHTS_FILE_3 = "weights_3.txt"; + parameter [13:0] current_decay_3 = 0; + parameter [13:0] voltage_decay_3 = 4054; + parameter [WIDTH - 1:0] threshold_3 = 11; + parameter INPUT_SPIKE_4 = NEURON_3; + parameter NEURON_4 = 16; + parameter WEIGHTS_FILE_4 = "weights_4.txt"; + parameter [13:0] current_decay_4 = 0; + parameter [13:0] voltage_decay_4 = 4055; + parameter [WIDTH - 1:0] threshold_4 = 32767; + parameter WEIGHT_DEPTH_12 = 8192; + parameter WEIGHT_DEPTH_34 = 8192; + input clk; + input rst; + input en; + input [3:0] spike_in; + input active_group_in; + output wire valid; + output wire valid_spike; + output wire [3:0] spike_out; + output wire integrated_neuron; + input [7:0] weight_mem_L1_wren; + function integer clogb2; + input integer depth; + for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1) + depth = depth >> 1; + endfunction + input [clogb2(WEIGHT_DEPTH_12 - 1) - 1:0] weight_mem_L1_wr_addr; + input [15:0] weight_mem_L1_data_in; + output wire [15:0] weight_mem_L1_data_out; + input weight_mem_L1_ena; + input [7:0] weight_mem_L2_wren; + input [clogb2(WEIGHT_DEPTH_12 - 1) - 1:0] weight_mem_L2_wr_addr; + input [15:0] weight_mem_L2_data_in; + output wire [15:0] weight_mem_L2_data_out; + input weight_mem_L2_ena; + input [7:0] weight_mem_L3_wren; + input [clogb2(WEIGHT_DEPTH_34 - 1) - 1:0] weight_mem_L3_wr_addr; + input [15:0] weight_mem_L3_data_in; + output wire [15:0] weight_mem_L3_data_out; + input weight_mem_L3_ena; + input [7:0] weight_mem_L4_wren; + input [clogb2(WEIGHT_DEPTH_34 - 1) - 1:0] weight_mem_L4_wr_addr; + input [15:0] weight_mem_L4_data_in; + output wire [15:0] weight_mem_L4_data_out; + input weight_mem_L4_ena; + output wire [7:0] o_spike_mem_dat; + input wire [7:0] i_spike_mem_adr; + input wire [1:0] i_spike_mem_rd_en; + input wire [1:0] i_spike_mem_wr_en; + input wire [3:0] i_spike_mem_dat; + input wire [clogb2(MAX_SYNAPSES - 1) - 1:0] snn_input_channels; + input wire [clogb2(MAX_NEURONS - 1) - 1:0] neuron_1; + input wire [clogb2(MAX_NEURONS - 1) - 1:0] neuron_2; + input wire [clogb2(MAX_NEURONS - 1) - 1:0] neuron_3; + input wire [clogb2(MAX_NEURONS - 1) - 1:0] neuron_4; + input wire [2:0] layers; + input output_buffer_ren; + input [7:0] output_buffer_addr; + output wire [31:0] output_buffer_out; + output wire output_buffer_wr_en_debug; + output wire signed [WIDTH - 1:0] p1; + output wire signed [WIDTH - 1:0] p2; + input enb_debug; + wire output_buffer_wr_en; + assign output_buffer_wr_en_debug = output_buffer_wr_en; + wire signed [WIDTH - 1:0] voltage_1; + assign p1 = voltage_1; + wire signed [WIDTH - 1:0] voltage_2; + assign p2 = voltage_2; + localparam LAYERS_LOG2 = clogb2(LAYERS - 1); + localparam TOTAL_NEURONS = ((NEURON_1 + NEURON_2) + NEURON_3) + NEURON_4; + localparam SYN_G1_L2 = clogb2((INPUT_SPIKE_1 / 4) - 1); + localparam SYN_G2_L2 = clogb2((INPUT_SPIKE_2 / 4) - 1); + localparam SYN_G3_L2 = clogb2((INPUT_SPIKE_3 / 4) - 1); + localparam SYN_G4_L2 = clogb2((INPUT_SPIKE_4 / 4) - 1); + function integer max4; + input integer a; + input integer b; + input integer c; + input integer d; + max4 = ((a > b ? a : b) > (c > d ? c : d) ? (a > b ? a : b) : (c > d ? c : d)); + endfunction + localparam MAX_LAYER = max4(INPUT_SPIKE_1 * NEURON_1, INPUT_SPIKE_2 * NEURON_2, INPUT_SPIKE_3 * NEURON_3, INPUT_SPIKE_4 * NEURON_4) / 8; + localparam P1 = clogb2(MAX_LAYER) - clogb2((NEURON_1 * INPUT_SPIKE_1) / 8); + localparam P2 = clogb2(MAX_LAYER) - clogb2((NEURON_2 * INPUT_SPIKE_2) / 8); + localparam P3 = clogb2(MAX_LAYER) - clogb2((NEURON_3 * INPUT_SPIKE_3) / 8); + localparam P4 = clogb2(MAX_LAYER) - clogb2((NEURON_4 * INPUT_SPIKE_4) / 8); + localparam WEIGHT_ADDRESS_SIZE = (clogb2((MAX_NEURONS / 2) - 1) + clogb2((MAX_SYNAPSES / 4) - 1)) + clogb2(LAYERS - 1); + wire v1; + wire v2; + wire [1:0] s1; + wire [1:0] s2; + wire ag1; + wire ag2; + wire convolution_valid; + wire integrated_neuron_1; + reg [LAYERS_LOG2 - 1:0] layer_counter; + reg layer_enable_dd; + wire [3:0] spike_mem_out; + wire [WEIGHT_ADDRESS_SIZE - 1:0] weight_rd_addr; + wire layer_integrated; + wire convolution_pipe_full; + layer_lp #( + .WIDTH(WIDTH), + .NEURON(TOTAL_NEURONS / 2), + .LAYERS(LAYERS), + .WEIGHTS_FILE_1(WEIGHTS_FILE_1), + .WEIGHTS_FILE_2(WEIGHTS_FILE_2), + .current_decay_1(current_decay_1), + .current_decay_2(current_decay_2), + .current_decay_3(current_decay_3), + .current_decay_4(current_decay_4), + .voltage_decay_1(voltage_decay_1), + .voltage_decay_2(voltage_decay_2), + .voltage_decay_3(voltage_decay_3), + .voltage_decay_4(voltage_decay_4), + .threshold_1(threshold_1), + .threshold_2(threshold_2), + .threshold_3(threshold_3), + .threshold_4(threshold_4), + .WEIGHT_DEPTH(2 ** WEIGHT_ADDRESS_SIZE) + ) layer_lp_l1_i( + .clk(clk), + .rst(rst), + .en(layer_enable_dd), + .spike_in(spike_mem_out), + .active_group_in(), + .weight_rd_addr(weight_rd_addr), + .acc_clear(layer_integrated), + .acc_clear_and_go(convolution_valid), + .convolution_pipe_full(convolution_pipe_full), + .layer_id(layer_counter), + .valid(v1), + .spike_out(s1), + .active_group_out(ag1), + .integrated_neuron(integrated_neuron_1), + .neuron_lp_voltage(voltage_1), + .weight_mem_L1_wren(weight_mem_L1_wren), + .weight_mem_L1_wr_addr(weight_mem_L1_wr_addr), + .weight_mem_L1_data_in(weight_mem_L1_data_in), + .weight_mem_L1_data_out(weight_mem_L1_data_out), + .weight_mem_L1_ena(weight_mem_L1_ena), + .weight_mem_L2_wren(weight_mem_L2_wren), + .weight_mem_L2_wr_addr(weight_mem_L2_wr_addr), + .weight_mem_L2_data_in(weight_mem_L2_data_in), + .weight_mem_L2_data_out(weight_mem_L2_data_out), + .weight_mem_L2_ena(weight_mem_L2_ena), + .enb_debug(enb_debug) + ); + wire integrated_neuron_2; + layer_lp #( + .WIDTH(WIDTH), + .NEURON(TOTAL_NEURONS / 2), + .LAYERS(LAYERS), + .WEIGHTS_FILE_1(WEIGHTS_FILE_3), + .WEIGHTS_FILE_2(WEIGHTS_FILE_4), + .current_decay_1(current_decay_1), + .current_decay_2(current_decay_2), + .current_decay_3(current_decay_3), + .current_decay_4(current_decay_4), + .voltage_decay_1(voltage_decay_1), + .voltage_decay_2(voltage_decay_2), + .voltage_decay_3(voltage_decay_3), + .voltage_decay_4(voltage_decay_4), + .threshold_1(threshold_1), + .threshold_2(threshold_2), + .threshold_3(threshold_3), + .threshold_4(threshold_4), + .WEIGHT_DEPTH(2 ** WEIGHT_ADDRESS_SIZE) + ) layer_lp_l2_i( + .clk(clk), + .rst(rst), + .en(layer_enable_dd), + .spike_in(spike_mem_out), + .active_group_in(), + .weight_rd_addr(weight_rd_addr), + .acc_clear(layer_integrated), + .acc_clear_and_go(convolution_valid), + .convolution_pipe_full(convolution_pipe_full), + .layer_id(layer_counter), + .valid(v2), + .spike_out(s2), + .active_group_out(ag2), + .neuron_lp_voltage(voltage_2), + .integrated_neuron(integrated_neuron_2), + .weight_mem_L1_wren(weight_mem_L3_wren), + .weight_mem_L1_wr_addr(weight_mem_L3_wr_addr), + .weight_mem_L1_data_in(weight_mem_L3_data_in), + .weight_mem_L1_data_out(weight_mem_L3_data_out), + .weight_mem_L1_ena(weight_mem_L3_ena), + .weight_mem_L2_wren(weight_mem_L4_wren), + .weight_mem_L2_wr_addr(weight_mem_L4_wr_addr), + .weight_mem_L2_data_in(weight_mem_L4_data_in), + .weight_mem_L2_data_out(weight_mem_L4_data_out), + .weight_mem_L2_ena(weight_mem_L4_ena), + .enb_debug(enb_debug) + ); + wire [3:0] spike12; + assign spike12 = {s1[1], s2[1], s1[0], s2[0]}; + wire valid12; + assign valid12 = v1 && v2; + assign spike_out = spike12; + reg [clogb2((MAX_NEURONS / 2) - 1) - 1:0] neuron_cnt; + reg [clogb2((MAX_SYNAPSES / 4) - 1) - 1:0] spike_wr_addr; + reg spike_written; + reg [clogb2(LAYERS - 1) - 1:0] spike_written_counter; + wire [clogb2((MAX_SYNAPSES / 4) - 1) - 1:0] SYNAPSES; + assign SYNAPSES = (spike_written_counter == 0 ? (INPUT_SPIKE_1 / 4) - 1 : (spike_written_counter == 1 ? (INPUT_SPIKE_2 / 4) - 1 : (spike_written_counter == 2 ? (INPUT_SPIKE_3 / 4) - 1 : (INPUT_SPIKE_4 / 4) - 1))); + wire spike_cnt_en; + assign spike_cnt_en = en | (v1 & (layer_counter != (LAYERS - 1))); + always @(posedge clk) + if (rst) + spike_wr_addr <= 0; + else if (spike_cnt_en) begin + if (spike_wr_addr == SYNAPSES) + spike_wr_addr <= 0; + else + spike_wr_addr <= spike_wr_addr + 1'b1; + end + always @(posedge clk) + if (rst) + spike_written <= 0; + else if (spike_cnt_en && (spike_wr_addr == SYNAPSES)) + spike_written <= 1; + else + spike_written <= 0; + always @(posedge clk) + if (rst) + spike_written_counter <= 0; + else if (spike_written) + spike_written_counter <= spike_written_counter + 1'b1; + wire [clogb2((MAX_NEURONS / 2) - 1) - 1:0] NEURON; + assign NEURON = (layer_counter == 0 ? (NEURON_1 / 2) - 1 : (layer_counter == 1 ? (NEURON_2 / 2) - 1 : (layer_counter == 2 ? (NEURON_3 / 2) - 1 : (NEURON_4 / 2) - 1))); + wire stream_out_done; + wire stream_out_done_1; + wire stream_out_done_2; + assign stream_out_done = stream_out_done_2 || stream_out_done_1; + always @(posedge clk) + if (rst) + neuron_cnt <= 0; + else if (stream_out_done) begin + if (neuron_cnt < NEURON) + neuron_cnt <= neuron_cnt + 1'b1; + else + neuron_cnt <= 0; + end + wire layer_dispatched; + assign layer_dispatched = stream_out_done && (neuron_cnt == NEURON); + wire inference_done; + always @(posedge clk) + if (rst) + layer_counter <= 0; + else if (layer_integrated) begin + if (layer_counter < LAYERS) + layer_counter = layer_counter + 1'b1; + end + assign inference_done = (layer_counter == LAYERS) && layer_integrated; + reg layer_enable; + reg layer_enable_d; + wire stream_out_1; + wire stream_out_2; + always @(posedge clk) + if (rst) + layer_enable <= 0; + else if (stream_out_1 | stream_out_2) + layer_enable <= 1; + else if (stream_out_done && (neuron_cnt == NEURON)) + layer_enable <= 0; + always @(posedge clk) + if (rst) begin + layer_enable_d <= 0; + layer_enable_dd <= 0; + end + else begin + layer_enable_d <= layer_enable; + layer_enable_dd <= layer_enable_d; + end + wire [clogb2((MAX_SYNAPSES / 4) - 1) - 1:0] words_to_read; + wire [clogb2((MAX_SYNAPSES / 4) - 1) - 1:0] words_to_read_1; + wire [clogb2((MAX_SYNAPSES / 4) - 1) - 1:0] words_to_read_2; + assign words_to_read = (layer_counter[0] ? words_to_read_2 : words_to_read_1); + reg [clogb2((MAX_SYNAPSES / 4) - 1) - 1:0] convolution_valid_cnt; + always @(posedge clk) + if (rst) + convolution_valid_cnt <= 0; + else if (convolution_pipe_full) begin + if (convolution_valid_cnt < words_to_read) + convolution_valid_cnt <= convolution_valid_cnt + 1'b1; + else + convolution_valid_cnt <= 0; + end + assign convolution_valid = (convolution_valid_cnt == words_to_read) && convolution_pipe_full; + assign integrated_neuron = integrated_neuron_1; + reg integrated_neuron_r; + always @(posedge clk) + if (rst) + integrated_neuron_r <= integrated_neuron; + else + integrated_neuron_r <= integrated_neuron; + reg [clogb2((MAX_NEURONS / 2) - 1) - 1:0] integrated_neurons_cnt; + reg [clogb2((MAX_NEURONS / 2) - 1) - 1:0] integrated_neurons_cnt_d; + always @(posedge clk) + if (rst) + integrated_neurons_cnt <= 0; + else if (integrated_neuron) begin + if (integrated_neurons_cnt < NEURON) + integrated_neurons_cnt <= integrated_neurons_cnt + 1'b1; + else + integrated_neurons_cnt <= 0; + end + always @(posedge clk) + if (rst) + integrated_neurons_cnt_d <= 0; + else + integrated_neurons_cnt_d <= integrated_neurons_cnt; + assign layer_integrated = integrated_neuron_r && (integrated_neurons_cnt_d == NEURON); + wire empty; + wire empty_1; + wire empty_2; + wire stack_en_1; + assign stack_en_1 = (((v1 && v2) && (ag1 || ag2)) && layer_counter[0]) || (en & active_group_in); + assign stream_out_1 = (spike_written && ~spike_written_counter[0]) || (stream_out_done_1 && (neuron_cnt != NEURON)); + wire [clogb2((MAX_SYNAPSES / 4) - 1) - 1:0] spike_rd_addr_1; + stack #( + .DATA_WIDTH(clogb2((MAX_SYNAPSES / 4) - 1)), + .DEPTH(MAX_SYNAPSES / 4) + ) stack_1( + .clk(clk), + .rst(rst), + .din(spike_wr_addr), + .wr_en(stack_en_1), + .clear(layer_integrated && ~layer_counter[0]), + .stream_out(stream_out_1), + .dout(spike_rd_addr_1), + .done(stream_out_done_1), + .active_entries(words_to_read_1), + .empty(empty_1) + ); + wire stack_en_2; + assign stack_en_2 = ((v1 && v2) && (ag1 || ag2)) && ~layer_counter[0]; + assign stream_out_2 = (spike_written && spike_written_counter[0]) || (stream_out_done_2 && (neuron_cnt != NEURON)); + wire [clogb2((MAX_SYNAPSES / 4) - 1) - 1:0] spike_rd_addr_2; + stack #( + .DATA_WIDTH(clogb2((MAX_SYNAPSES / 4) - 1)), + .DEPTH(MAX_SYNAPSES / 4) + ) stack_2( + .clk(clk), + .rst(rst), + .din(spike_wr_addr), + .wr_en(stack_en_2), + .clear(layer_integrated && layer_counter[0]), + .stream_out(stream_out_2), + .dout(spike_rd_addr_2), + .done(stream_out_done_2), + .active_entries(words_to_read_2), + .empty(empty_2) + ); + wire [clogb2((MAX_SYNAPSES / 4) - 1) - 1:0] spike_rd_addr; + assign spike_rd_addr = (layer_counter[0] ? spike_rd_addr_2 : spike_rd_addr_1); + assign empty = (layer_counter[0] ? empty_2 : empty_1); + wire [3:0] spike_mem_out_1; + wire spike_wr_en_1; + wire [3:0] spike_mem_out_2; + wire spike_wr_en_2; + assign spike_wr_en_1 = ((v1 && v2) && layer_counter[0]) || (en & active_group_in); + assign spike_wr_en_2 = (v1 && v2) && ~layer_counter[0]; + wire [3:0] spike_mem_in_1; + assign spike_mem_in_1 = (en ? spike_in : spike12); + wire [clogb2((MAX_SYNAPSES / 4) - 1) - 1:0] spike_rd_addr_1_mux; + wire [clogb2((MAX_SYNAPSES / 4) - 1) - 1:0] spike_rd_addr_2_mux; + wire [clogb2((MAX_SYNAPSES / 4) - 1) - 1:0] spike_wr_addr_mux; + assign spike_rd_addr_1_mux = (i_spike_mem_rd_en[0] ? i_spike_mem_adr : spike_rd_addr_1); + assign spike_rd_addr_2_mux = (i_spike_mem_rd_en[1] ? i_spike_mem_adr : spike_rd_addr_2); + assign o_spike_mem_dat = {spike_mem_out_2, spike_mem_out_1}; + assign spike_wr_addr_mux = spike_wr_addr; + BRAM_singlePort_readFirst #( + .RAM_WIDTH(4), + .RAM_DEPTH(MAX_SYNAPSES / 4), + .RAM_PERFORMANCE("HIGH_PERFORMANCE"), + .INIT_FILE("") + ) spike_mem_1( + .addra(spike_wr_addr_mux), + .addrb(spike_rd_addr_1_mux), + .dina(spike_mem_in_1), + .clk(clk), + .wea(spike_wr_en_1), + .ena(spike_wr_en_1), + .enb(1'b1), + .rst(rst), + .regceb(1'b1), + .doutb(spike_mem_out_1) + ); + BRAM_singlePort_readFirst #( + .RAM_WIDTH(4), + .RAM_DEPTH(MAX_SYNAPSES / 4), + .RAM_PERFORMANCE("HIGH_PERFORMANCE"), + .INIT_FILE("") + ) spike_mem_2( + .addra(spike_wr_addr_mux), + .addrb(spike_rd_addr_2_mux), + .dina(spike12), + .clk(clk), + .wea(spike_wr_en_2), + .ena(spike_wr_en_2), + .enb(1'b1), + .rst(rst), + .regceb(1'b1), + .doutb(spike_mem_out_2) + ); + assign spike_mem_out = (empty ? 4'b0000 : (layer_counter[0] ? spike_mem_out_2 : spike_mem_out_1)); + assign weight_rd_addr = (layer_counter == 0 ? {layer_counter, {P1 {1'b0}}, neuron_cnt[clogb2((NEURON_1 / 2) - 1) - 1:0], spike_rd_addr[SYN_G1_L2 - 1:0]} : (layer_counter == 1 ? {layer_counter, {P2 {1'b0}}, neuron_cnt[clogb2((NEURON_2 / 2) - 1) - 1:0], spike_rd_addr[SYN_G2_L2 - 1:0]} : (layer_counter == 2 ? {layer_counter, {P3 {1'b0}}, neuron_cnt[clogb2((NEURON_3 / 2) - 1) - 1:0], spike_rd_addr[SYN_G3_L2 - 1:0]} : {layer_counter, {P4 {1'b0}}, neuron_cnt[clogb2((NEURON_4 / 2) - 1) - 1:0], spike_rd_addr[SYN_G4_L2 - 1:0]}))); + wire [31:0] output_buffer_din; + assign output_buffer_wr_en = integrated_neuron && (layer_counter == 3); + assign output_buffer_din = {voltage_2, voltage_1}; + ihp_single_port_256x48 #( + .RAM_WIDTH(2 * WIDTH), + .RAM_DEPTH(NEURON_4 / 2), + .RAM_PERFORMANCE("LOW_LATENCY"), + .INIT_FILE("") + ) output_buffer( + .addra(integrated_neurons_cnt), + .addrb(output_buffer_addr), + .dina(output_buffer_din), + .clk(clk), + .wea(output_buffer_wr_en), + .ena(output_buffer_wr_en), + .enb(output_buffer_ren), + .rst(rst), + .regceb(1'b1), + .doutb(output_buffer_out) + ); + assign valid = (integrated_neuron_r && (integrated_neurons_cnt_d == NEURON)) && (layer_counter == (LAYERS - 1)); + assign valid_spike = valid12 && (layer_counter == (LAYERS - 1)); + function integer max; + input integer j; + input integer k; + if (j > k) + max = j; + endfunction +endmodule +module Syntzulu ( + clk_enc, + clk_snn, + rst, + en, + data_in, + detect, + encoding_bypass, + valid, + v, + f1, + f2, + f3, + f4, + neuron_lp_voltage, + integrated_neuron, + weight_mem_L1_wren, + weight_mem_L1_wr_addr, + weight_mem_L1_data_in, + weight_mem_L1_data_out, + weight_mem_L1_ena, + weight_mem_L2_wren, + weight_mem_L2_wr_addr, + weight_mem_L2_data_in, + weight_mem_L2_data_out, + weight_mem_L2_ena, + weight_mem_L3_wren, + weight_mem_L3_wr_addr, + weight_mem_L3_data_in, + weight_mem_L3_data_out, + weight_mem_L3_ena, + weight_mem_L4_wren, + weight_mem_L4_wr_addr, + weight_mem_L4_data_in, + weight_mem_L4_data_out, + weight_mem_L4_ena, + o_spike_mem_dat, + i_spike_mem_adr, + i_spike_mem_rd_en, + i_spike_mem_wr_en, + i_spike_mem_dat, + o_sample_mem_dat, + i_sample_mem_adr, + i_sample_mem_rd_en, + i_sample_mem_wr_en, + i_sample_mem_dat, + snn_input_channels, + neuron_1, + neuron_2, + neuron_3, + neuron_4, + layers, + output_buffer_ren, + output_buffer_addr, + output_buffer_out, + output_buffer_wr_en_debug, + p1, + p2, + enb_debug +); + parameter ENCODING_BYPASS = 0; + parameter CHANNELS = 16; + parameter ORDER = 2; + parameter WINDOW = 8192; + parameter REF_PERIOD = 1024; + parameter DW = 8; + parameter WIDTH = 16; + parameter MAX_SYNAPSES = 128; + parameter MAX_NEURONS = 128; + parameter LAYERS = 4; + parameter INPUT_SPIKE_1 = 32; + parameter NEURON_1 = 64; + parameter WEIGHTS_FILE_1 = "weights_1.txt"; + parameter [13:0] current_decay_1 = 0; + parameter [13:0] voltage_decay_1 = 4054; + parameter [WIDTH - 1:0] threshold_1 = 19; + parameter INPUT_SPIKE_2 = NEURON_1; + parameter NEURON_2 = 128; + parameter WEIGHTS_FILE_2 = "weights_2.txt"; + parameter [13:0] current_decay_2 = 0; + parameter [13:0] voltage_decay_2 = 4054; + parameter [WIDTH - 1:0] threshold_2 = 17; + parameter INPUT_SPIKE_3 = NEURON_2; + parameter NEURON_3 = 64; + parameter WEIGHTS_FILE_3 = "weights_3.txt"; + parameter [13:0] current_decay_3 = 0; + parameter [13:0] voltage_decay_3 = 4054; + parameter [WIDTH - 1:0] threshold_3 = 11; + parameter INPUT_SPIKE_4 = NEURON_3; + parameter NEURON_4 = 16; + parameter WEIGHTS_FILE_4 = "weights_4.txt"; + parameter [13:0] current_decay_4 = 0; + parameter [13:0] voltage_decay_4 = 4055; + parameter [WIDTH - 1:0] threshold_4 = 32767; + parameter WEIGHT_DEPTH_12 = 8192; + parameter WEIGHT_DEPTH_34 = 8192; + input clk_enc; + input clk_snn; + input rst; + input en; + input signed [15:0] data_in; + input detect; + input encoding_bypass; + output wire valid; + output wire signed [WIDTH - 1:0] v; + output wire signed [WIDTH - 1:0] f1; + output wire signed [WIDTH - 1:0] f2; + output wire signed [WIDTH - 1:0] f3; + output wire signed [WIDTH - 1:0] f4; + output wire signed [WIDTH - 1:0] neuron_lp_voltage; + output wire integrated_neuron; + input [7:0] weight_mem_L1_wren; + function integer clogb2; + input integer depth; + for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1) + depth = depth >> 1; + endfunction + input [clogb2(WEIGHT_DEPTH_12 - 1) - 1:0] weight_mem_L1_wr_addr; + input [15:0] weight_mem_L1_data_in; + output wire [15:0] weight_mem_L1_data_out; + input weight_mem_L1_ena; + input [7:0] weight_mem_L2_wren; + input [clogb2(WEIGHT_DEPTH_12 - 1) - 1:0] weight_mem_L2_wr_addr; + input [15:0] weight_mem_L2_data_in; + output wire [15:0] weight_mem_L2_data_out; + input weight_mem_L2_ena; + input [7:0] weight_mem_L3_wren; + input [clogb2(WEIGHT_DEPTH_34 - 1) - 1:0] weight_mem_L3_wr_addr; + input [15:0] weight_mem_L3_data_in; + output wire [15:0] weight_mem_L3_data_out; + input weight_mem_L3_ena; + input [7:0] weight_mem_L4_wren; + input [clogb2(WEIGHT_DEPTH_34 - 1) - 1:0] weight_mem_L4_wr_addr; + input [15:0] weight_mem_L4_data_in; + output wire [15:0] weight_mem_L4_data_out; + input weight_mem_L4_ena; + output wire [7:0] o_spike_mem_dat; + input wire [7:0] i_spike_mem_adr; + input wire [1:0] i_spike_mem_rd_en; + input wire [1:0] i_spike_mem_wr_en; + input wire [3:0] i_spike_mem_dat; + output wire [15:0] o_sample_mem_dat; + input wire [7:0] i_sample_mem_adr; + input wire i_sample_mem_rd_en; + input wire i_sample_mem_wr_en; + input wire [15:0] i_sample_mem_dat; + input wire [clogb2(MAX_SYNAPSES - 1) - 1:0] snn_input_channels; + input wire [clogb2(MAX_NEURONS - 1) - 1:0] neuron_1; + input wire [clogb2(MAX_NEURONS - 1) - 1:0] neuron_2; + input wire [clogb2(MAX_NEURONS - 1) - 1:0] neuron_3; + input wire [clogb2(MAX_NEURONS - 1) - 1:0] neuron_4; + input wire [2:0] layers; + input output_buffer_ren; + input [7:0] output_buffer_addr; + output wire [31:0] output_buffer_out; + output wire output_buffer_wr_en_debug; + output wire signed [WIDTH - 1:0] p1; + output wire signed [WIDTH - 1:0] p2; + input enb_debug; + localparam SPIKE = 4; + wire [3:0] spike_bin; + wire valid_bin; + wire active_group_out_bin; + wire valid_potential; + encoding_slot #( + .BYPASS(ENCODING_BYPASS), + .CHANNELS(CHANNELS), + .ORDER(ORDER), + .WINDOW(WINDOW), + .REF_PERIOD(REF_PERIOD), + .DW(DW) + ) encoding_slot_i( + .clk(clk_enc), + .rst(rst), + .en(en), + .data_in(data_in), + .detect(detect), + .spike_bin(spike_bin), + .valid_bin(valid_bin), + .active_group_out_bin(active_group_out_bin), + .inference_done(valid_potential), + .o_sample_mem_dat(o_sample_mem_dat), + .i_sample_mem_adr(i_sample_mem_adr), + .i_sample_mem_rd_en(i_sample_mem_rd_en), + .i_sample_mem_wr_en(i_sample_mem_wr_en), + .i_sample_mem_dat(i_sample_mem_dat), + .bypass(encoding_bypass), + .enb_debug(enb_debug) + ); + wire [3:0] spike_out_snn; + wire valid_spike; + snn_lp #( + .WIDTH(WIDTH), + .MAX_SYNAPSES(MAX_SYNAPSES), + .MAX_NEURONS(MAX_SYNAPSES), + .INPUT_SPIKE_1(INPUT_SPIKE_1), + .NEURON_1(NEURON_1), + .WEIGHTS_FILE_1(WEIGHTS_FILE_1), + .current_decay_1(current_decay_1), + .voltage_decay_1(voltage_decay_1), + .threshold_1(threshold_1), + .INPUT_SPIKE_2(INPUT_SPIKE_2), + .NEURON_2(NEURON_2), + .WEIGHTS_FILE_2(WEIGHTS_FILE_2), + .current_decay_2(current_decay_2), + .voltage_decay_2(voltage_decay_2), + .threshold_2(threshold_2), + .INPUT_SPIKE_3(INPUT_SPIKE_3), + .NEURON_3(NEURON_3), + .WEIGHTS_FILE_3(WEIGHTS_FILE_3), + .current_decay_3(current_decay_3), + .voltage_decay_3(voltage_decay_3), + .threshold_3(threshold_3), + .INPUT_SPIKE_4(INPUT_SPIKE_4), + .NEURON_4(NEURON_4), + .WEIGHTS_FILE_4(WEIGHTS_FILE_4), + .current_decay_4(current_decay_4), + .voltage_decay_4(voltage_decay_4), + .threshold_4(threshold_4), + .WEIGHT_DEPTH_12(WEIGHT_DEPTH_12), + .WEIGHT_DEPTH_34(WEIGHT_DEPTH_34) + ) snn_lp_i( + .clk(clk_snn), + .rst(rst), + .en(valid_bin), + .spike_in(spike_bin), + .active_group_in(active_group_out_bin), + .valid(valid_potential), + .valid_spike(valid_spike), + .spike_out(spike_out_snn), + .integrated_neuron(integrated_neuron), + .weight_mem_L1_wren(weight_mem_L1_wren), + .weight_mem_L1_wr_addr(weight_mem_L1_wr_addr), + .weight_mem_L1_data_in(weight_mem_L1_data_in), + .weight_mem_L1_data_out(weight_mem_L1_data_out), + .weight_mem_L1_ena(weight_mem_L1_ena), + .weight_mem_L2_wren(weight_mem_L2_wren), + .weight_mem_L2_wr_addr(weight_mem_L2_wr_addr), + .weight_mem_L2_data_in(weight_mem_L2_data_in), + .weight_mem_L2_data_out(weight_mem_L2_data_out), + .weight_mem_L2_ena(weight_mem_L2_ena), + .weight_mem_L3_wren(weight_mem_L3_wren), + .weight_mem_L3_wr_addr(weight_mem_L3_wr_addr), + .weight_mem_L3_data_in(weight_mem_L3_data_in), + .weight_mem_L3_data_out(weight_mem_L3_data_out), + .weight_mem_L3_ena(weight_mem_L3_ena), + .weight_mem_L4_wren(weight_mem_L4_wren), + .weight_mem_L4_wr_addr(weight_mem_L4_wr_addr), + .weight_mem_L4_data_in(weight_mem_L4_data_in), + .weight_mem_L4_data_out(weight_mem_L4_data_out), + .weight_mem_L4_ena(weight_mem_L4_ena), + .o_spike_mem_dat(o_spike_mem_dat), + .i_spike_mem_adr(i_spike_mem_adr), + .i_spike_mem_rd_en(i_spike_mem_rd_en), + .i_spike_mem_wr_en(i_spike_mem_wr_en), + .i_spike_mem_dat(i_spike_mem_dat), + .snn_input_channels(snn_input_channels), + .neuron_1(neuron_1), + .neuron_2(neuron_2), + .neuron_3(neuron_3), + .neuron_4(neuron_4), + .layers(layers), + .output_buffer_ren(output_buffer_ren), + .output_buffer_addr(output_buffer_addr), + .output_buffer_out(output_buffer_out), + .output_buffer_wr_en_debug(output_buffer_wr_en_debug), + .p1(p1), + .p2(p2), + .enb_debug(enb_debug) + ); + assign valid = valid_potential; +endmodule +//////////////////////////////////////////////////////////////////////// +// +// Copyright 2023 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//////////////////////////////////////////////////////////////////////// + +`celldefine +module RM_IHPSG13_1P_1024x64_c2_bm_bist #(parameter INIT_FILE="") ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [9:0] A_ADDR; + input [63:0] A_DIN; + input A_DLY; + output [63:0] A_DOUT; + input [63:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [9:0] A_BIST_ADDR; + input [63:0] A_BIST_DIN; + input [63:0] A_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(64), + .P_ADDR_WIDTH(10), + .INIT_FILE(INIT_FILE), + .DEPTH(1024) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [9:0] A_ADDR_DELAY; + wire [63:0] A_DIN_DELAY; + wire [63:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [9:0] A_BIST_ADDR_DELAY; + wire [63:0] A_BIST_DIN_DELAY; + wire [63:0] A_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(64), + .P_ADDR_WIDTH(10), + .INIT_FILE(INIT_FILE), + .DEPTH(1024) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine +//////////////////////////////////////////////////////////////////////// +// +// Copyright 2023 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//////////////////////////////////////////////////////////////////////// + +`celldefine +module RM_IHPSG13_1P_2048x64_c2_bm_bist #(parameter INIT_FILE="") ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [10:0] A_ADDR; + input [63:0] A_DIN; + input A_DLY; + output [63:0] A_DOUT; + input [63:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [10:0] A_BIST_ADDR; + input [63:0] A_BIST_DIN; + input [63:0] A_BIST_BM; + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(64), + .P_ADDR_WIDTH(11), + .INIT_FILE(INIT_FILE), + .DEPTH(2048) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [10:0] A_ADDR_DELAY; + wire [63:0] A_DIN_DELAY; + wire [63:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [10:0] A_BIST_ADDR_DELAY; + wire [63:0] A_BIST_DIN_DELAY; + wire [63:0] A_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(64), + .P_ADDR_WIDTH(11), + .INIT_FILE(INIT_FILE), + .DEPTH(2048) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine +//////////////////////////////////////////////////////////////////////// +// +// Copyright 2023 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//////////////////////////////////////////////////////////////////////// + +`celldefine +module RM_IHPSG13_1P_256x48_c2_bm_bist #(parameter INIT_FILE="") ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [7:0] A_ADDR; + input [47:0] A_DIN; + input A_DLY; + output [47:0] A_DOUT; + input [47:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [7:0] A_BIST_ADDR; + input [47:0] A_BIST_DIN; + input [47:0] A_BIST_BM; + + wire [47:0] debug; + assign debug = A_DIN; + + + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(48), + .P_ADDR_WIDTH(8), + .INIT_FILE(INIT_FILE), + .DEPTH(256) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [7:0] A_ADDR_DELAY; + wire [47:0] A_DIN_DELAY; + wire [47:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [7:0] A_BIST_ADDR_DELAY; + wire [47:0] A_BIST_DIN_DELAY; + wire [47:0] A_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(48), + .P_ADDR_WIDTH(8), + .INIT_FILE(INIT_FILE) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine +//////////////////////////////////////////////////////////////////////// +// +// Copyright 2023 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//////////////////////////////////////////////////////////////////////// + +`celldefine +module RM_IHPSG13_1P_256x64_c2_bm_bist #(parameter INIT_FILE="") ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [7:0] A_ADDR; + input [63:0] A_DIN; + input A_DLY; + output [63:0] A_DOUT; + input [63:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [7:0] A_BIST_ADDR; + input [63:0] A_BIST_DIN; + input [63:0] A_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(64), + .P_ADDR_WIDTH(8), + .INIT_FILE(INIT_FILE) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [7:0] A_ADDR_DELAY; + wire [63:0] A_DIN_DELAY; + wire [63:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [7:0] A_BIST_ADDR_DELAY; + wire [63:0] A_BIST_DIN_DELAY; + wire [63:0] A_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(64), + .P_ADDR_WIDTH(8), + .INIT_FILE(INIT_FILE) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine +//////////////////////////////////////////////////////////////////////// +// +// Copyright 2023 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//////////////////////////////////////////////////////////////////////// + +`celldefine +module RM_IHPSG13_1P_512x64_c2_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [8:0] A_ADDR; + input [63:0] A_DIN; + input A_DLY; + output [63:0] A_DOUT; + input [63:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [8:0] A_BIST_ADDR; + input [63:0] A_BIST_DIN; + input [63:0] A_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(64), + .P_ADDR_WIDTH(9) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [8:0] A_ADDR_DELAY; + wire [63:0] A_DIN_DELAY; + wire [63:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [8:0] A_BIST_ADDR_DELAY; + wire [63:0] A_BIST_DIN_DELAY; + wire [63:0] A_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(64), + .P_ADDR_WIDTH(9) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine +//////////////////////////////////////////////////////////////////////// +// +// Copyright 2023 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//////////////////////////////////////////////////////////////////////// + +`celldefine +module RM_IHPSG13_1P_64x64_c2_bm_bist ( + A_CLK, + A_MEN, + A_WEN, + A_REN, + A_ADDR, + A_DIN, + A_DLY, + A_DOUT, + A_BM, + A_BIST_CLK, + A_BIST_EN, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM +); + + input A_CLK; + input A_MEN; + input A_WEN; + input A_REN; + input [5:0] A_ADDR; + input [63:0] A_DIN; + input A_DLY; + output [63:0] A_DOUT; + input [63:0] A_BM; + input A_BIST_CLK; + input A_BIST_EN; + input A_BIST_MEN; + input A_BIST_WEN; + input A_BIST_REN; + input [5:0] A_BIST_ADDR; + input [63:0] A_BIST_DIN; + input [63:0] A_BIST_BM; + + +`ifdef FUNCTIONAL // functional // + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(64), + .P_ADDR_WIDTH(6) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK), + .A_MEN(A_MEN), + .A_WEN(A_WEN), + .A_REN(A_REN), + .A_ADDR(A_ADDR), + .A_DLY(A_DLY), + .A_DIN(A_DIN), + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(A_BIST_CLK), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN), + .A_BIST_WEN(A_BIST_WEN), + .A_BIST_REN(A_BIST_REN), + .A_BIST_ADDR(A_BIST_ADDR), + .A_BIST_DIN(A_BIST_DIN), + .A_BIST_BM(A_BIST_BM) + ); + +`else + + wire A_CLK_DELAY; + wire A_MEN_DELAY; + wire A_WEN_DELAY; + wire A_REN_DELAY; + wire [5:0] A_ADDR_DELAY; + wire [63:0] A_DIN_DELAY; + wire [63:0] A_BM_DELAY; + wire A_BIST_CLK_DELAY; + wire A_BIST_MEN_DELAY; + wire A_BIST_WEN_DELAY; + wire A_BIST_REN_DELAY; + wire [5:0] A_BIST_ADDR_DELAY; + wire [63:0] A_BIST_DIN_DELAY; + wire [63:0] A_BIST_BM_DELAY; + + reg notifier; + + wire A_RW_ACCESS = (A_WEN || A_REN) && A_MEN; + wire A_W_ACCESS = A_WEN && A_MEN; + wire A_BIST_RW_ACCESS = (A_BIST_WEN || A_BIST_REN) && A_BIST_MEN; + wire A_BIST_W_ACCESS = A_BIST_WEN && A_BIST_MEN; + + + + SRAM_1P_behavioral_bm_bist #( + .P_DATA_WIDTH(64), + .P_ADDR_WIDTH(6) + ) i_SRAM_1P_behavioral_bm_bist ( + .A_CLK(A_CLK_DELAY), + .A_MEN(A_MEN_DELAY), + .A_WEN(A_WEN_DELAY), + .A_REN(A_REN_DELAY), + .A_ADDR(A_ADDR_DELAY), + .A_DLY(A_DLY), + .A_DIN(A_DIN_DELAY), + .A_DOUT(A_DOUT), + .A_BM(A_BM_DELAY), + .A_BIST_CLK(A_BIST_CLK_DELAY), + .A_BIST_EN(A_BIST_EN), + .A_BIST_MEN(A_BIST_MEN_DELAY), + .A_BIST_WEN(A_BIST_WEN_DELAY), + .A_BIST_REN(A_BIST_REN_DELAY), + .A_BIST_ADDR(A_BIST_ADDR_DELAY), + .A_BIST_DIN(A_BIST_DIN_DELAY), + .A_BIST_BM(A_BIST_BM_DELAY) + ); + + + specify + + (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); + $width(posedge A_CLK, 1.0,0,notifier); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, posedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_MEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_MEN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_REN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_REN_DELAY); + $setuphold(posedge A_CLK &&& A_MEN, negedge A_WEN, 1.0, 1.0,notifier,,,A_CLK_DELAY, A_WEN_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, posedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + $setuphold(posedge A_CLK &&& A_RW_ACCESS, negedge A_ADDR, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_ADDR_DELAY); + + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_DIN, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_DIN_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, posedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + $setuphold(posedge A_CLK &&& A_W_ACCESS, negedge A_BM, 1.0 ,1.0, notifier,,,A_CLK_DELAY, A_BM_DELAY); + (posedge A_BIST_CLK *> (A_DOUT : A_BIST_DIN)) = (1.0, 1.0); + $width(posedge A_BIST_CLK, 1.0,0,notifier); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, posedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_MEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_MEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_REN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_REN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_MEN, negedge A_BIST_WEN, 1.0, 1.0,notifier,,,A_BIST_CLK_DELAY, A_BIST_WEN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, posedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_RW_ACCESS, negedge A_BIST_ADDR, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_ADDR_DELAY); + + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_DIN, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_DIN_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, posedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + $setuphold(posedge A_BIST_CLK &&& A_BIST_W_ACCESS, negedge A_BIST_BM, 1.0 ,1.0, notifier,,,A_BIST_CLK_DELAY, A_BIST_BM_DELAY); + + + endspecify + +`endif + +endmodule +`endcelldefine +//////////////////////////////////////////////////////////////////////// +// +// Copyright 2023 IHP PDK Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//////////////////////////////////////////////////////////////////////// + +//aggiunto da me, di default non lo aveva aggiunto + +module SRAM_1P_behavioral_bm_bist ( + + A_ADDR, + A_DIN, + A_BM, + A_MEN, // Memory enable input -> if disabled, the memory is deactivated + A_WEN, // Common write enable input (bytes maskable with BM[23:0]) + A_REN, // Read enable input -> if enabled for read access when WEN=1 --> Write-through + A_CLK, // Clock input + A_DLY, // Delay selection signals + A_DOUT, + + A_BIST_EN, + A_BIST_ADDR, + A_BIST_DIN, + A_BIST_BM, + A_BIST_MEN, + A_BIST_WEN, + A_BIST_REN, + A_BIST_CLK + + ); + +parameter P_DATA_WIDTH=24; +parameter P_ADDR_WIDTH=14; +parameter DEPTH = 256; +parameter INIT_FILE=""; + +input wire [P_ADDR_WIDTH-1:0] A_ADDR; +input wire [P_DATA_WIDTH-1:0] A_DIN; +input wire [P_DATA_WIDTH-1:0] A_BM; // write bit mask, write enabled on bit [i] if BM[i]=1'b1 +input wire A_MEN; // Memory enable input -> if disabled, the memory is deactivated +input wire A_WEN; // Common write enable input (bytes maskable with BM[23:0]) +input wire A_REN; // Read enable input -> if enabled for read access when WEN=1 --> Write-through +input wire A_CLK; // Clock input +input wire A_DLY; // Delay selection signals +output wire [P_DATA_WIDTH-1:0] A_DOUT; // 24 Data outputs + +input wire A_BIST_EN; +input wire [P_ADDR_WIDTH-1:0] A_BIST_ADDR; +input wire [P_DATA_WIDTH-1:0] A_BIST_DIN; +input wire [P_DATA_WIDTH-1:0] A_BIST_BM; +input wire A_BIST_MEN; +input wire A_BIST_WEN; +input wire A_BIST_REN; +input wire A_BIST_CLK; + + + +// +// reg [P_DATA_WIDTH-1:0] memory [0:2**(P_ADDR_WIDTH)-1]; // memory +// reg [P_DATA_WIDTH-1:0] dr_r; +// +// wire [63:0] debug1, debug2, debug3; +// assign debug1 = memory[0]; +// assign debug2 = memory[2048]; +// assign debug3 = memory[3000]; + +wire [P_ADDR_WIDTH-1:0] ADDR_MUX; +wire [P_DATA_WIDTH-1:0] DIN_MUX; +wire [P_DATA_WIDTH-1:0] BM_MUX; +wire MEN_MUX; +wire WEN_MUX; +wire REN_MUX; +wire CLK_MUX; + +//BIST-MUX +assign ADDR_MUX =(A_BIST_EN==1'b1)? A_BIST_ADDR:A_ADDR; +assign DIN_MUX =(A_BIST_EN==1'b1)? A_BIST_DIN :A_DIN; +assign BM_MUX =(A_BIST_EN==1'b1)? A_BIST_BM :A_BM; +assign MEN_MUX =(A_BIST_EN==1'b1)? A_BIST_MEN :A_MEN; +assign WEN_MUX =(A_BIST_EN==1'b1)? A_BIST_WEN :A_WEN; +assign REN_MUX =(A_BIST_EN==1'b1)? A_BIST_REN :A_REN; +assign CLK_MUX =(A_BIST_EN==1'b1)? A_BIST_CLK :A_CLK; + +generate + if (P_ADDR_WIDTH == 6 && P_DATA_WIDTH == 64) begin : gen_fakeram_64x64 + fakeram_64x64_1rw i_fakeram ( + .rw0_clk (CLK_MUX), + .rw0_ce_in (MEN_MUX), + .rw0_addr_in (ADDR_MUX), + .rw0_we_in (WEN_MUX), + .rw0_wd_in (DIN_MUX), + .rw0_wmask_in (BM_MUX), + .rw0_rd_out (A_DOUT) + ); + end + else if (P_ADDR_WIDTH == 8 && P_DATA_WIDTH == 48) begin : gen_fakeram_48x256 + fakeram_48x256_1rw i_fakeram ( + .rw0_clk (CLK_MUX), + .rw0_ce_in (MEN_MUX), + .rw0_addr_in (ADDR_MUX), + .rw0_we_in (WEN_MUX), + .rw0_wd_in (DIN_MUX), + .rw0_wmask_in (BM_MUX), + .rw0_rd_out (A_DOUT) + ); + end + else if (P_ADDR_WIDTH == 8 && P_DATA_WIDTH == 64) begin : gen_fakeram_64x256 + fakeram_64x256_1rw i_fakeram ( + .rw0_clk (CLK_MUX), + .rw0_ce_in (MEN_MUX), + .rw0_addr_in (ADDR_MUX), + .rw0_we_in (WEN_MUX), + .rw0_wd_in (DIN_MUX), + .rw0_wmask_in (BM_MUX), + .rw0_rd_out (A_DOUT) + ); + end + else if (P_ADDR_WIDTH == 9 && P_DATA_WIDTH == 64) begin : gen_fakeram_64x512 + fakeram_64x512_1rw i_fakeram ( + .rw0_clk (CLK_MUX), + .rw0_ce_in (MEN_MUX), + .rw0_addr_in (ADDR_MUX), + .rw0_we_in (WEN_MUX), + .rw0_wd_in (DIN_MUX), + .rw0_wmask_in (BM_MUX), + .rw0_rd_out (A_DOUT) + ); + end + else if (P_ADDR_WIDTH == 10 && P_DATA_WIDTH == 64) begin : gen_fakeram_64x1024 + fakeram_64x1024_1rw i_fakeram ( + .rw0_clk (CLK_MUX), + .rw0_ce_in (MEN_MUX), + .rw0_addr_in (ADDR_MUX), + .rw0_we_in (WEN_MUX), + .rw0_wd_in (DIN_MUX), + .rw0_wmask_in (BM_MUX), + .rw0_rd_out (A_DOUT) + ); + end + else if (P_ADDR_WIDTH == 11 && P_DATA_WIDTH == 64) begin : gen_fakeram_64x2048 + fakeram_64x2048_1rw i_fakeram ( + .rw0_clk (CLK_MUX), + .rw0_ce_in (MEN_MUX), + .rw0_addr_in (ADDR_MUX), + .rw0_we_in (WEN_MUX), + .rw0_wd_in (DIN_MUX), + .rw0_wmask_in (BM_MUX), + .rw0_rd_out (A_DOUT) + ); + end + else begin : gen_unsupported + initial begin + $error("SRAM_1P_behavioral_bm_bist: Unsupported configuration P_ADDR_WIDTH=%0d P_DATA_WIDTH=%0d", + P_ADDR_WIDTH, P_DATA_WIDTH); + $fatal(1, "Unsupported SRAM configuration, aborting simulation."); + end + end +endgenerate + + + // The following code either initializes the memory values to a specified file or to all zeros to match hardware + // generate + // if (INIT_FILE != "") begin: use_init_file + // initial + // $readmemh(INIT_FILE, memory, 0, DEPTH-1); + // end else begin: init_bram_to_zero + // integer ram_index; + // initial + // for (ram_index = 0; ram_index < DEPTH; ram_index = ram_index + 1) + // memory[ram_index] = {P_DATA_WIDTH{1'b0}}; + // end + // endgenerate + + +// +// wire [63:0] debug200; +// wire [63:0] debug400; + +// assign debug200 = memory[200]; +// assign debug400 = memory[400]; + +endmodule +module ihp_dualport_256x48_dualmem #( + parameter RAM_WIDTH = 4, + parameter RAM_DEPTH = 64, + parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE", + parameter INIT_FILE = "" +) +( + input [10:0] addra, + input [10:0] addrb, + input [31:0] dina, + input clk, + input wea, + input ena, + input enb, + input rst, + input regceb, + + output reg [31:0] doutb +); + + +wire en_w; +assign en_w = ena && wea; + +parameter R0_W1 = 0, WAIT_1 = 1, R1_W0 = 2, WAIT_2 = 3, INIT = 4; +reg [2:0] state, state_next; +wire NEXT; + +always@(posedge clk) begin + if(rst) + state <= INIT; + else + state <= state_next; +end + +always@(*) begin + case(state) + INIT: state_next = NEXT ? R0_W1 : INIT; + + R0_W1: state_next = NEXT ? WAIT_1 : R0_W1; + WAIT_1: state_next = R1_W0; + R1_W0: state_next = NEXT ? WAIT_2 : R1_W0; + WAIT_2: state_next = R0_W1; + default: state_next = INIT; + endcase +end + +reg [5:0] control; +reg [9:0] AD_0, AD_1; +wire [31:0] DO_0, DO_1; + +wire en_0, ren0, wren0, en_1, ren1, wren1; +assign {en_0, ren0, wren0, en_1, ren1, wren1} = control; + +always@(*) begin + case(state) + + INIT: begin control = {1'b0, 1'b0, 1'b0, en_w, 1'b0, en_w}; AD_0 = addrb; AD_1 = addra; doutb = 32'b0; end + + R0_W1: begin control = {enb, enb, 1'b0, en_w, 1'b0, en_w}; AD_0 = addrb; AD_1 = addra; doutb = DO_0; end + WAIT_1: begin control = {enb, enb, 1'b0, en_w, 1'b0, en_w}; AD_0 = addrb; AD_1 = addra; doutb = DO_0; end + + R1_W0: begin control = {en_w, 1'b0, en_w, enb, enb, 1'b0}; AD_0 = addra; AD_1 = addrb; doutb = DO_1; end + WAIT_2: begin control = {en_w, 1'b0, en_w, enb, enb, 1'b0}; AD_0 = addra; AD_1 = addrb; doutb = DO_1; end + + default: begin control = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}; AD_0 = 10'b0; AD_1 = 10'b0; doutb = 32'b0; end + endcase +end + + + + +RM_IHPSG13_1P_256x48_c2_bm_bist mem0( + .A_CLK(clk), + .A_MEN(en_0), + .A_WEN(wren0), + .A_REN(ren0), + .A_ADDR(AD_0), + .A_DIN(dina), + .A_DLY(1'b0), + .A_DOUT(DO_0), + .A_BM(48'hFFFFFFFFFFFF), + + + .A_BIST_CLK(1'b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_WEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_ADDR(1'b0), + .A_BIST_DIN(1'b0), + .A_BIST_BM(1'b0) +); + +RM_IHPSG13_1P_256x48_c2_bm_bist mem1( + .A_CLK(clk), + .A_MEN(en_1), + .A_WEN(wren1), + .A_REN(ren1), + .A_ADDR(AD_1), + .A_DIN(dina), + .A_DLY(1'b0), + .A_DOUT(DO_1), + .A_BM(48'hFFFFFFFFFFFF), + + + .A_BIST_CLK(1'b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_WEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_ADDR(1'b0), + .A_BIST_DIN(1'b0), + .A_BIST_BM(1'b0) +); + +parameter IDLE = 0, WAIT = 1, FINISH = 2; +reg [1:0] state2, state2_next; + +always@(posedge clk) begin + if(rst) + state2 <= IDLE; + else + state2 <= state2_next; +end + +always@(state, addra, addrb) begin + case(state2) + IDLE: state2_next = ((addra == 0) && (addrb == 0)) ? IDLE : WAIT; + WAIT: state2_next = ((addra == 0) && (addrb == 0)) ? FINISH : WAIT; + FINISH: state2_next = IDLE; + default state2_next = IDLE; + endcase +end + +assign NEXT = (state2 == FINISH) ? 1 : 0; + + +endmodule + +/* + _______ ____ + |__ __| _ \ + | | | |_) | + | | | _ < + | | | |_) | + |_| |____/ + +*/ + + + +module ihp_dualport_256x48_dualmem_tb #( + parameter RAM_WIDTH = 4, + parameter RAM_DEPTH = 64, + parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE", + parameter INIT_FILE = "" +) +( + input [10:0] addra, + input [10:0] addrb, + input [31:0] dina, + input clk, + input wea, + input ena, + input enb, + input rst, + input regceb, + + output reg [31:0] doutb +); + + + +assign en_w = ena && wea; + +parameter R0_W1 = 0, WAIT_1 = 1, R1_W0 = 2, WAIT_2 = 3; +reg [1:0] state, state_next; +wire NEXT; + +always@(posedge clk) begin + if(rst) + state <= R0_W1; + else + state <= state_next; +end + +always@(*) begin + case(state) + R0_W1: state_next = NEXT ? WAIT_1 : R0_W1; + WAIT_1: state_next = R1_W0; + R1_W0: state_next = NEXT ? WAIT_2 : R1_W0; + WAIT_2: state_next = R0_W1; + endcase +end + +reg [5:0] control; +reg [9:0] AD_0, AD_1; +wire [31:0] DO_0, DO_1; + + +wire en_0, ren0, wren0, en_1, ren1, wren1; +assign {en_0, ren0, wren0, en_1, ren1, wren1} = control; + +always@(*) begin + case(state) + + R0_W1: begin control = {enb, enb, 1'b0, en_w, 1'b0, en_w}; AD_0 = addrb; AD_1 = addra; doutb = DO_0; end + WAIT_1: begin control = {enb, enb, 1'b0, en_w, 1'b0, en_w}; AD_0 = addrb; AD_1 = addra; doutb = DO_0; end + + R1_W0: begin control = {en_w, 1'b0, en_w, enb, enb, 1'b0}; AD_0 = addra; AD_1 = addrb; doutb = DO_1; end + WAIT_2: begin control = {en_w, 1'b0, en_w, enb, enb, 1'b0}; AD_0 = addra; AD_1 = addrb; doutb = DO_1; end + + endcase +end + + + + +RM_IHPSG13_1P_256x48_c2_bm_bist #(.INIT_FILE(INIT_FILE)) mem0( + .A_CLK(clk), + .A_MEN(en_0), + .A_WEN(wren0), + .A_REN(ren0), + .A_ADDR(AD_0), + .A_DIN(dina), + .A_DLY(1'b0), + .A_DOUT(DO_0), + .A_BM(48'hFFFFFFFFFFFF), + + + .A_BIST_CLK(1'b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_WEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_ADDR(1'b0), + .A_BIST_DIN(1'b0), + .A_BIST_BM(1'b0) +); + +RM_IHPSG13_1P_256x48_c2_bm_bist mem1( + .A_CLK(clk), + .A_MEN(en_1), + .A_WEN(wren1), + .A_REN(ren1), + .A_ADDR(AD_1), + .A_DIN(dina), + .A_DLY(1'b0), + .A_DOUT(DO_1), + .A_BM(48'hFFFFFFFFFFFF), + + + .A_BIST_CLK(1'b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_WEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_ADDR(1'b0), + .A_BIST_DIN(1'b0), + .A_BIST_BM(1'b0) +); + +parameter IDLE = 0, WAIT = 1, FINISH = 2; +reg [1:0] state2, state2_next; + +always@(posedge clk) begin + if(rst) + state2 <= IDLE; + else + state2 <= state2_next; +end + +always@(state, addra, addrb) begin + case(state2) + IDLE: state2_next = ((addra == 0) && (addrb == 0)) ? IDLE : WAIT; + WAIT: state2_next = ((addra == 0) && (addrb == 0)) ? FINISH : WAIT; + FINISH: state2_next = IDLE; + default state2_next = IDLE; + endcase +end + +assign NEXT = (state2 == FINISH) ? 1 : 0; + + + +endmodule + + + + + +module ihp_ram # (parameter memfile="") +( + input wire clk, + input wire [3:0] we, + input wire [9:0] addr, + input wire [63:0] dina, + output wire [63:0] dout, + input wire enb_debug + +); + + wire [31:0] BM; + reg [7:0] B1, B2, B3, B4; + + + wire wea; + + assign wea = (|we); + //bitmask + always @(posedge clk) begin + if (we[0]) B1 = 8'hFF; else B1 = 8'h00; + if (we[1]) B2 = 8'hFF; else B2 = 8'h00; + if (we[2]) B3 = 8'hFF; else B3 = 8'h00; + if (we[3]) B4 = 8'hFF; else B4 = 8'h00; + end + + assign BM = wea ? {32'hFFFFFFFF, B4, B3, B2, B1} : 32'hFFFFFFFF; + + + +`ifdef SIM +RM_IHPSG13_1P_1024x64_c2_bm_bist #(.INIT_FILE(memfile)) ram( + .A_CLK(clk), + + .A_MEN(enb_debug), + .A_WEN(wea), + .A_REN(enb_debug), + + .A_ADDR(addr), + .A_DIN(dina), + .A_DLY(1'b0), + .A_DOUT(dout), + .A_BM(BM), + + + .A_BIST_CLK(1'b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_WEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_ADDR(1'b0), + .A_BIST_DIN(1'b0), + .A_BIST_BM(1'b0) +); + + +`else + +RM_IHPSG13_1P_1024x64_c2_bm_bist ram( + + .A_CLK(clk), + + .A_MEN(enb_debug), + .A_WEN(wea), + .A_REN(enb_debug), + + .A_ADDR(addr), + .A_DIN(dina), + .A_DLY(1'b0), + .A_DOUT(dout), + .A_BM(BM), + + + .A_BIST_CLK(1'b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_WEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_ADDR(1'b0), + .A_BIST_DIN(1'b0), + .A_BIST_BM(1'b0) + +); + +`endif + + + +endmodule +module ihp_single_port_256x48 #( + parameter RAM_WIDTH = 4, + parameter RAM_DEPTH = 64, + parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE", + parameter INIT_FILE = "" +) +( + input [7:0] addra, + input [7:0] addrb, + input [47:0] dina, + input clk, + input wea, + input ena, + input enb, + input rst, + input regceb, + + output [47:0] doutb +); + +wire MEN; +wire WEN; +wire REN; + +assign MEN = ena || enb ; +assign WEN = ena || wea ; +assign REN = enb ; + +wire [7:0] ADDR; +assign ADDR = WEN ? addra : addrb; + +wire [47:0] ram_data_b; + +`ifdef SIM +RM_IHPSG13_1P_256x48_c2_bm_bist #(.INIT_FILE(INIT_FILE)) single_port( + .A_CLK(clk), + .A_MEN(MEN), + .A_WEN(WEN), + .A_REN(REN), + .A_ADDR(ADDR), + .A_DIN(dina), + .A_DLY(1'b0), + .A_DOUT(ram_data_b), + .A_BM(48'hFFFFFFFFFFFF), + + + .A_BIST_CLK(1'b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_WEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_ADDR(1'b0), + .A_BIST_DIN(1'b0), + .A_BIST_BM(1'b0) +); + + +`else + +RM_IHPSG13_1P_256x48_c2_bm_bist single_port( + .A_CLK(clk), + .A_MEN(MEN), + .A_WEN(WEN), + .A_REN(REN), + .A_ADDR(ADDR), + .A_DIN(dina), + .A_DLY(1'b0), + .A_DOUT(ram_data_b), + .A_BM(48'hFFFFFFFFFFFF), + + + .A_BIST_CLK(1'b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_WEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_ADDR(1'b0), + .A_BIST_DIN(1'b0), + .A_BIST_BM(1'b0) +); + +`endif + + + + // The following code generates HIGH_PERFORMANCE (use output register) or LOW_LATENCY (no output register) + generate + if (RAM_PERFORMANCE == "LOW_LATENCY") begin: no_output_register + + // The following is a 1 clock cycle read latency at the cost of a longer clock-to-out timing + assign doutb = ram_data_b; + + end else begin: output_register + + // The following is a 2 clock cycle read latency with improve clock-to-out timing + + reg [RAM_WIDTH-1:0] doutb_reg = {RAM_WIDTH{1'b0}}; + + always @(posedge clk) + if (rst) + doutb_reg <= {RAM_WIDTH{1'b0}}; + else if (regceb) + doutb_reg <= ram_data_b; + + assign doutb = doutb_reg; + + end + endgenerate + +endmodule + +module ihp_single_port_256x64 #( + parameter RAM_WIDTH = 4, + parameter RAM_DEPTH = 64, + parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE", + parameter INIT_FILE = "" +) +( + input [7:0] addra, + input [7:0] addrb, + input [63:0] dina, + input clk, + input wea, + input ena, + input enb, + input rst, + input regceb, + + output [63:0] doutb +); + + +assign MEN = ena || enb ; +assign WEN = ena || wea ; +assign REN = enb ; + +wire [7:0] ADDR; +assign ADDR = WEN ? addra : addrb; + +wire [47:0] ram_data_b; + +`ifdef SIM +RM_IHPSG13_1P_256x64_c2_bm_bist #(.INIT_FILE(INIT_FILE)) single_port( + .A_CLK(clk), + .A_MEN(MEN), + .A_WEN(WEN), + .A_REN(REN), + .A_ADDR(ADDR), + .A_DIN(dina), + .A_DLY(1'b0), + .A_DOUT(ram_data_b), + .A_BM(64'hFFFFFFFFFFFFFFFF), + + + .A_BIST_CLK(1'b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_WEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_ADDR(1'b0), + .A_BIST_DIN(1'b0), + .A_BIST_BM(1'b0) +); + + +`else + +RM_IHPSG13_1P_256x64_c2_bm_bist single_port( + .A_CLK(clk), + .A_MEN(MEN), + .A_WEN(WEN), + .A_REN(REN), + .A_ADDR(ADDR), + .A_DIN(dina), + .A_DLY(1'b0), + .A_DOUT(ram_data_b), + .A_BM(64'hFFFFFFFFFFFFFFFF), + + + .A_BIST_CLK(1'b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_WEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_ADDR(1'b0), + .A_BIST_DIN(1'b0), + .A_BIST_BM(1'b0) +); + +`endif + + + + // The following code generates HIGH_PERFORMANCE (use output register) or LOW_LATENCY (no output register) + generate + if (RAM_PERFORMANCE == "LOW_LATENCY") begin: no_output_register + + // The following is a 1 clock cycle read latency at the cost of a longer clock-to-out timing + assign doutb = ram_data_b; + + end else begin: output_register + + // The following is a 2 clock cycle read latency with improve clock-to-out timing + + reg [RAM_WIDTH-1:0] doutb_reg = {RAM_WIDTH{1'b0}}; + + always @(posedge clk) + if (rst) + doutb_reg <= {RAM_WIDTH{1'b0}}; + else if (regceb) + doutb_reg <= ram_data_b; + + assign doutb = doutb_reg; + + end + endgenerate + +endmodule + + + + + + + + + + + + + + + + + + + +module weights_mem_ihp #( + parameter RAM_DEPTH = 4096, + parameter RAM_WIDTH = 32, + parameter INIT_FILE = "" +) +( + input [11:0] addra1, + input [15:0] dina1, + input ena1, + input wea1, + + input [11:0] addra2, + input [15:0] dina2, + input ena2, + input wea2, + + input [11:0] addrb, + input clk, + input enb, + input rst, + input regceb, + + output reg [31:0] doutb + ); + + wire [31:0] doutb_tmp; + wire A_MEN; + wire A_WEN; + wire A_REN; + reg [10:0] A_ADDR; + reg [63:0] A_BM; + wire [63:0] A_DOUT; + reg [63:0] A_DIN; + + assign A_MEN = ena1 || ena2 || enb ; + assign A_WEN = ena1 || ena2; + assign A_REN = enb; + + assign doutb_tmp = addrb[11] ? A_DOUT[63:32] : A_DOUT[31:0]; + + + //MASCHERA + always@(*) begin + + if(ena1) begin + if (addra1[11]) begin + A_BM = 64'hFFFF000000000000; + A_DIN = {dina1, 48'h000000000000}; end + else begin + A_BM = 64'h00000000FFFF0000; + A_DIN = {32'h000000000000, dina1, 16'h0000}; end + end + + else if (ena2) begin + if (addra2[11]) begin + A_BM = 64'h0000FFFF00000000; + A_DIN = {16'h0000, dina2, 32'h00000000}; end + else begin + A_BM = 64'h000000000000FFFF; + A_DIN = {48'h000000000000, dina2}; end + end + + else begin + A_BM = 64'h0000000000000000; + A_DIN = 64'h0000000000000000; end + + end + + //INDIRIZZO + always@(*) begin + if(ena1) + A_ADDR = addra1[10:0]; + + else if(ena2) + A_ADDR = addra2[10:0]; + + else + A_ADDR = addrb[10:0]; + end + + + + RM_IHPSG13_1P_2048x64_c2_bm_bist mem( + .A_CLK(clk), + .A_MEN(A_MEN), //Memory enable, activates memory for read/write. + .A_WEN(A_WEN), //Write enable, triggers write operation to memory. + .A_REN(A_REN), //Read enable, triggers read operation from memory. + .A_ADDR(A_ADDR), + .A_DIN(A_DIN), + .A_DLY(1'b0), //Delay control, possibly for timing adjustments. + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(1'b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_WEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_ADDR(1'b0), + .A_BIST_DIN(1'b0), + .A_BIST_BM(1'b0) + ); + + +always@(posedge clk) begin + if(rst) + doutb <= 0; + else + doutb <= doutb_tmp; +end + + + +endmodule + + + + +module weights_mem_ihp_qc #( + parameter RAM_DEPTH = 4096, + parameter RAM_WIDTH = 32, + parameter INIT_FILE = "" +) +( + input [10:0] addra1, + input [15:0] dina1, + input ena1, + input wea1, + + input [10:0] addrb, + input clk, + input enb, + input rst, + input regceb, + + output reg [31:0] doutb +); + + wire [31:0] doutb_tmp; + wire A_MEN; + wire A_WEN; + wire A_REN; + reg [10:0] A_ADDR; + reg [63:0] A_BM; + wire [63:0] A_DOUT; + reg [63:0] A_DIN; + + assign A_MEN = ena1 || enb ; + assign A_WEN = ena1; + assign A_REN = enb; + + assign doutb_tmp = addrb[10] ? A_DOUT[63:32] : A_DOUT[31:0]; + + + //MASCHERA + always@(*) begin + + if(ena1) begin + if (addra1[10]) begin + A_BM = 64'hFFFF000000000000; + A_DIN = {dina1, 48'h000000000000}; end + else begin + A_BM = 64'h00000000FFFF0000; + A_DIN = {32'h000000000000, dina1, 16'h0000}; end + end + else begin + A_BM = 64'h0000000000000000; + A_DIN = 64'h0000000000000000; end + end + + //INDIRIZZO + always@(*) begin + if(ena1) + A_ADDR = addra1[9:0]; + else + A_ADDR = addrb[9:0]; + end + +`ifdef SIM + + RM_IHPSG13_1P_1024x64_c2_bm_bist #(.INIT_FILE(INIT_FILE)) mem( + .A_CLK(clk), + .A_MEN(A_MEN), //Memory enable, activates memory for read/write. + .A_WEN(A_WEN), //Write enable, triggers write operation to memory. + .A_REN(A_REN), //Read enable, triggers read operation from memory. + .A_ADDR(A_ADDR), + .A_DIN(A_DIN), + .A_DLY(1'b0), //Delay control, possibly for timing adjustments. + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(1'b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_WEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_ADDR(1'b0), + .A_BIST_DIN(1'b0), + .A_BIST_BM(1'b0) + ); +`else + RM_IHPSG13_1P_1024x64_c2_bm_bist mem( + .A_CLK(clk), + .A_MEN(A_MEN), //Memory enable, activates memory for read/write. + .A_WEN(A_WEN), //Write enable, triggers write operation to memory. + .A_REN(A_REN), //Read enable, triggers read operation from memory. + .A_ADDR(A_ADDR), + .A_DIN(A_DIN), + .A_DLY(1'b0), //Delay control, possibly for timing adjustments. + .A_DOUT(A_DOUT), + .A_BM(A_BM), + .A_BIST_CLK(1'b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_WEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_ADDR(1'b0), + .A_BIST_DIN(1'b0), + .A_BIST_BM(1'b0) + ); + + +`endif + +always@(posedge clk) begin + if(rst) + doutb <= 0; + else + doutb <= doutb_tmp; +end + + + +endmodule + + +module weights_mem_ihp_qc_2048x64 #( + parameter RAM_DEPTH = 4096, + parameter RAM_WIDTH = 32, + parameter INIT_FILE = "" +) +( + input [10:0] addra1, + input [15:0] dina1, + input ena1, + input wea1, + + input [10:0] addrb, + input clk, + input enb, + input rst, + input regceb, + + output reg [63:0] doutb +); + + //wire [31:0] doutb_tmp; + wire A_MEN; + wire A_WEN; + wire A_REN; + //reg [10:0] A_ADDR; + //reg [63:0] A_BM; + wire [63:0] A_DOUT; + reg [63:0] A_DIN; + + assign A_MEN = ena1 || enb ; + assign A_WEN = ena1; + assign A_REN = enb; + + +`ifdef SIM + + RM_IHPSG13_1P_2048x64_c2_bm_bist #(.INIT_FILE(INIT_FILE)) mem( + .A_CLK(clk), + .A_MEN(A_MEN), //Memory enable, activates memory for read/write. + .A_WEN(A_WEN), //Write enable, triggers write operation to memory. + .A_REN(A_REN), //Read enable, triggers read operation from memory. + .A_ADDR(addrb), + .A_DIN(A_DIN), + .A_DLY(1'b0), //Delay control, possibly for timing adjustments. + .A_DOUT(A_DOUT), + .A_BM(64'hFFFFFFFFFFFFFFFF), + .A_BIST_CLK(1'b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_WEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_ADDR(1'b0), + .A_BIST_DIN(1'b0), + .A_BIST_BM(1'b0) + ); +`else + RM_IHPSG13_1P_2048x64_c2_bm_bist mem( + .A_CLK(clk), + .A_MEN(A_MEN), //Memory enable, activates memory for read/write. + .A_WEN(A_WEN), //Write enable, triggers write operation to memory. + .A_REN(A_REN), //Read enable, triggers read operation from memory. + .A_ADDR(addrb), + .A_DIN(A_DIN), + .A_DLY(1'b0), //Delay control, possibly for timing adjustments. + .A_DOUT(A_DOUT), + .A_BM(64'hFFFFFFFFFFFFFFFF), + .A_BIST_CLK(1'b0), + .A_BIST_EN(1'b0), + .A_BIST_MEN(1'b0), + .A_BIST_WEN(1'b0), + .A_BIST_REN(1'b0), + .A_BIST_ADDR(1'b0), + .A_BIST_DIN(1'b0), + .A_BIST_BM(1'b0) + ); + + +`endif + +always@(posedge clk) begin + if(rst) + doutb <= 0; + else + doutb <= A_DOUT; +end + + + +endmodule + + + +module serv_aligner + ( + input wire clk, + input wire rst, + // serv_top + input wire [31:0] i_ibus_adr, + input wire i_ibus_cyc, + output wire [31:0] o_ibus_rdt, + output wire o_ibus_ack, + // serv_rf_top + output wire [31:0] o_wb_ibus_adr, + output wire o_wb_ibus_cyc, + input wire [31:0] i_wb_ibus_rdt, + input wire i_wb_ibus_ack); + + wire [31:0] ibus_rdt_concat; + wire ack_en; + + reg [15:0] lower_hw; + reg ctrl_misal ; + + /* From SERV core to Memory + + o_wb_ibus_adr: Carries address of instruction to memory. In case of misaligned access, + which is caused by pc+2 due to compressed instruction, next instruction is fetched + by pc+4 and concatenation is done to make the instruction aligned. + + o_wb_ibus_cyc: Simply forwarded from SERV to Memory and is only altered by memory or SERV core. + */ + assign o_wb_ibus_adr = ctrl_misal ? (i_ibus_adr+32'b100) : i_ibus_adr; + assign o_wb_ibus_cyc = i_ibus_cyc; + + /* From Memory to SERV core + + o_ibus_ack: Instruction bus acknowledge is send to SERV only when the aligned instruction, + either compressed or un-compressed, is ready to dispatch. + + o_ibus_rdt: Carries the instruction from memory to SERV core. It can be either aligned + instruction coming from memory or made aligned by two bus transactions and concatenation. + */ + assign o_ibus_ack = i_wb_ibus_ack & ack_en; + assign o_ibus_rdt = ctrl_misal ? ibus_rdt_concat : i_wb_ibus_rdt; + + /* 16-bit register used to hold the upper half word of the current instruction in-case + concatenation will be required with the upper half word of upcoming instruction + */ + always @(posedge clk) begin + if(i_wb_ibus_ack)begin + lower_hw <= i_wb_ibus_rdt[31:16]; + end + end + + assign ibus_rdt_concat = {i_wb_ibus_rdt[15:0],lower_hw}; + + /* Two control signals: ack_en, ctrl_misal are set to control the bus transactions between + SERV core and the memory + */ + assign ack_en = !(i_ibus_adr[1] & !ctrl_misal); + + always @(posedge clk ) begin + if(rst) + ctrl_misal <= 0; + else if(i_wb_ibus_ack & i_ibus_adr[1]) + ctrl_misal <= !ctrl_misal; + end + +endmodule +`default_nettype none +module serv_alu + ( + input wire clk, + //State + input wire i_en, + input wire i_cnt0, + output wire o_cmp, + //Control + input wire i_sub, + input wire [1:0] i_bool_op, + input wire i_cmp_eq, + input wire i_cmp_sig, + input wire [2:0] i_rd_sel, + //Data + input wire i_rs1, + input wire i_op_b, + input wire i_buf, + output wire o_rd); + + wire result_add; + + reg cmp_r; + + wire add_cy; + reg add_cy_r; + + //Sign-extended operands + wire rs1_sx = i_rs1 & i_cmp_sig; + wire op_b_sx = i_op_b & i_cmp_sig; + + wire add_b = i_op_b^i_sub; + + assign {add_cy,result_add} = i_rs1+add_b+add_cy_r; + + wire result_lt = rs1_sx + ~op_b_sx + add_cy; + + wire result_eq = !result_add & (cmp_r | i_cnt0); + + assign o_cmp = i_cmp_eq ? result_eq : result_lt; + + /* + The result_bool expression implements the following operations between + i_rs1 and i_op_b depending on the value of i_bool_op + + 00 xor + 01 0 + 10 or + 11 and + + i_bool_op will be 01 during shift operations, so by outputting zero under + this condition we can safely or result_bool with i_buf + */ + wire result_bool = ((i_rs1 ^ i_op_b) & ~ i_bool_op[0]) | (i_bool_op[1] & i_op_b & i_rs1); + + assign o_rd = i_buf | + (i_rd_sel[0] & result_add) | + (i_rd_sel[1] & cmp_r & i_cnt0) | + (i_rd_sel[2] & result_bool); + + always @(posedge clk) begin + add_cy_r <= i_en ? add_cy : i_sub; + + if (i_en) + cmp_r <= o_cmp; + end + +endmodule +module serv_bufreg #( + parameter [0:0] MDU = 0 +)( + input wire i_clk, + //State + input wire i_cnt0, + input wire i_cnt1, + input wire i_en, + input wire i_init, + input wire i_mdu_op, + output wire [1:0] o_lsb, + //Control + input wire i_rs1_en, + input wire i_imm_en, + input wire i_clr_lsb, + input wire i_sh_signed, + //Data + input wire i_rs1, + input wire i_imm, + output wire o_q, + //External + output wire [31:0] o_dbus_adr, + //Extension + output wire [31:0] o_ext_rs1); + + wire c, q; + reg c_r; + reg [31:2] data; + reg [1:0] lsb; + + wire clr_lsb = i_cnt0 & i_clr_lsb; + + assign {c,q} = {1'b0,(i_rs1 & i_rs1_en)} + {1'b0,(i_imm & i_imm_en & !clr_lsb)} + c_r; + + always @(posedge i_clk) begin + //Make sure carry is cleared before loading new data + c_r <= c & i_en; + + if (i_en) + data <= {i_init ? q : (data[31] & i_sh_signed), data[31:3]}; + + if (i_init ? (i_cnt0 | i_cnt1) : i_en) + lsb <= {i_init ? q : data[2],lsb[1]}; + end + + assign o_q = lsb[0] & i_en; + assign o_dbus_adr = {data, 2'b00}; + assign o_ext_rs1 = {o_dbus_adr[31:2],lsb}; + assign o_lsb = (MDU & i_mdu_op) ? 2'b00 : lsb; + +endmodule +module serv_bufreg2 + ( + input wire i_clk, + //State + input wire i_en, + input wire i_init, + input wire i_cnt_done, + input wire [1:0] i_lsb, + input wire i_byte_valid, + output wire o_sh_done, + output wire o_sh_done_r, + //Control + input wire i_op_b_sel, + input wire i_shift_op, + //Data + input wire i_rs2, + input wire i_imm, + output wire o_op_b, + output wire o_q, + //External + output wire [31:0] o_dat, + input wire i_load, + input wire [31:0] i_dat); + + reg [31:0] dat; + + assign o_op_b = i_op_b_sel ? i_rs2 : i_imm; + + wire dat_en = i_shift_op | (i_en & i_byte_valid); + + /* The dat register has three different use cases for store, load and + shift operations. + store : Data to be written is shifted to the correct position in dat during + init by dat_en and is presented on the data bus as o_wb_dat + load : Data from the bus gets latched into dat during i_wb_ack and is then + shifted out at the appropriate time to end up in the correct + position in rd + shift : Data is shifted in during init. After that, the six LSB are used as + a downcounter (with bit 5 initially set to 0) that triggers + o_sh_done and o_sh_done_r when they wrap around to indicate that + the requested number of shifts have been performed + */ + wire [5:0] dat_shamt = (i_shift_op & !i_init) ? + //Down counter mode + dat[5:0]-1 : + //Shift reg mode with optional clearing of bit 5 + {dat[6] & !(i_shift_op & i_cnt_done),dat[5:1]}; + + assign o_sh_done = dat_shamt[5]; + assign o_sh_done_r = dat[5]; + + assign o_q = + ((i_lsb == 2'd3) & dat[24]) | + ((i_lsb == 2'd2) & dat[16]) | + ((i_lsb == 2'd1) & dat[8]) | + ((i_lsb == 2'd0) & dat[0]); + + assign o_dat = dat; + + always @(posedge i_clk) begin + if (dat_en | i_load) + dat <= i_load ? i_dat : {o_op_b, dat[31:7], dat_shamt}; + end + +endmodule +/* Copyright lowRISC contributors. +Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +Licensed under the Apache License, Version 2.0, see LICENSE for details. +SPDX-License-Identifier: Apache-2.0 + +* Adapted to SERV by @Abdulwadoodd as part of the project under spring '22 LFX Mentorship program */ + +/* Decodes RISC-V compressed instructions into their RV32i equivalent. */ + +module serv_compdec + ( + input wire i_clk, + input wire [31:0] i_instr, + input wire i_ack, + output wire [31:0] o_instr, + output reg o_iscomp); + + localparam OPCODE_LOAD = 7'h03; + localparam OPCODE_OP_IMM = 7'h13; + localparam OPCODE_STORE = 7'h23; + localparam OPCODE_OP = 7'h33; + localparam OPCODE_LUI = 7'h37; + localparam OPCODE_BRANCH = 7'h63; + localparam OPCODE_JALR = 7'h67; + localparam OPCODE_JAL = 7'h6f; + + reg [31:0] comp_instr; + reg illegal_instr; + + assign o_instr = illegal_instr ? i_instr : comp_instr; + + always @(posedge i_clk) begin + if(i_ack) + o_iscomp <= !illegal_instr; + end + + always @ (*) begin + // By default, forward incoming instruction, mark it as legal. + comp_instr = i_instr; + illegal_instr = 1'b0; + + // Check if incoming instruction is compressed. + case (i_instr[1:0]) + // C0 + 2'b00: begin + case (i_instr[15:14]) + 2'b00: begin + // c.addi4spn -> addi rd', x2, imm + comp_instr = {2'b0, i_instr[10:7], i_instr[12:11], i_instr[5], + i_instr[6], 2'b00, 5'h02, 3'b000, 2'b01, i_instr[4:2], {OPCODE_OP_IMM}}; + end + + 2'b01: begin + // c.lw -> lw rd', imm(rs1') + comp_instr = {5'b0, i_instr[5], i_instr[12:10], i_instr[6], + 2'b00, 2'b01, i_instr[9:7], 3'b010, 2'b01, i_instr[4:2], {OPCODE_LOAD}}; + end + + 2'b11: begin + // c.sw -> sw rs2', imm(rs1') + comp_instr = {5'b0, i_instr[5], i_instr[12], 2'b01, i_instr[4:2], + 2'b01, i_instr[9:7], 3'b010, i_instr[11:10], i_instr[6], + 2'b00, {OPCODE_STORE}}; + end + + 2'b10: begin + illegal_instr = 1'b1; + end + + endcase + end + + // C1 + + // Register address checks for RV32E are performed in the regular instruction decoder. + // If this check fails, an illegal instruction exception is triggered and the controller + // writes the actual faulting instruction to mtval. + 2'b01: begin + case (i_instr[15:13]) + 3'b000: begin + // c.addi -> addi rd, rd, nzimm + // c.nop + comp_instr = {{6 {i_instr[12]}}, i_instr[12], i_instr[6:2], + i_instr[11:7], 3'b0, i_instr[11:7], {OPCODE_OP_IMM}}; + end + + 3'b001, 3'b101: begin + // 001: c.jal -> jal x1, imm + // 101: c.j -> jal x0, imm + comp_instr = {i_instr[12], i_instr[8], i_instr[10:9], i_instr[6], + i_instr[7], i_instr[2], i_instr[11], i_instr[5:3], + {9 {i_instr[12]}}, 4'b0, ~i_instr[15], {OPCODE_JAL}}; + end + + 3'b010: begin + // c.li -> addi rd, x0, nzimm + // (c.li hints are translated into an addi hint) + comp_instr = {{6 {i_instr[12]}}, i_instr[12], i_instr[6:2], 5'b0, + 3'b0, i_instr[11:7], {OPCODE_OP_IMM}}; + end + + 3'b011: begin + // c.lui -> lui rd, imm + // (c.lui hints are translated into a lui hint) + comp_instr = {{15 {i_instr[12]}}, i_instr[6:2], i_instr[11:7], {OPCODE_LUI}}; + + if (i_instr[11:7] == 5'h02) begin + // c.addi16sp -> addi x2, x2, nzimm + comp_instr = {{3 {i_instr[12]}}, i_instr[4:3], i_instr[5], i_instr[2], + i_instr[6], 4'b0, 5'h02, 3'b000, 5'h02, {OPCODE_OP_IMM}}; + end + + end + + 3'b100: begin + case (i_instr[11:10]) + 2'b00, + 2'b01: begin + // 00: c.srli -> srli rd, rd, shamt + // 01: c.srai -> srai rd, rd, shamt + // (c.srli/c.srai hints are translated into a srli/srai hint) + comp_instr = {1'b0, i_instr[10], 5'b0, i_instr[6:2], 2'b01, i_instr[9:7], + 3'b101, 2'b01, i_instr[9:7], {OPCODE_OP_IMM}}; + end + + 2'b10: begin + // c.andi -> andi rd, rd, imm + comp_instr = {{6 {i_instr[12]}}, i_instr[12], i_instr[6:2], 2'b01, i_instr[9:7], + 3'b111, 2'b01, i_instr[9:7], {OPCODE_OP_IMM}}; + end + + 2'b11: begin + case (i_instr[6:5]) + 2'b00: begin + // c.sub -> sub rd', rd', rs2' + comp_instr = {2'b01, 5'b0, 2'b01, i_instr[4:2], 2'b01, i_instr[9:7], + 3'b000, 2'b01, i_instr[9:7], {OPCODE_OP}}; + end + + 2'b01: begin + // c.xor -> xor rd', rd', rs2' + comp_instr = {7'b0, 2'b01, i_instr[4:2], 2'b01, i_instr[9:7], 3'b100, + 2'b01, i_instr[9:7], {OPCODE_OP}}; + end + + 2'b10: begin + // c.or -> or rd', rd', rs2' + comp_instr = {7'b0, 2'b01, i_instr[4:2], 2'b01, i_instr[9:7], 3'b110, + 2'b01, i_instr[9:7], {OPCODE_OP}}; + end + + 2'b11: begin + // c.and -> and rd', rd', rs2' + comp_instr = {7'b0, 2'b01, i_instr[4:2], 2'b01, i_instr[9:7], 3'b111, + 2'b01, i_instr[9:7], {OPCODE_OP}}; + end + endcase + end + endcase + end + + 3'b110, 3'b111: begin + // 0: c.beqz -> beq rs1', x0, imm + // 1: c.bnez -> bne rs1', x0, imm + comp_instr = {{4 {i_instr[12]}}, i_instr[6:5], i_instr[2], 5'b0, 2'b01, + i_instr[9:7], 2'b00, i_instr[13], i_instr[11:10], i_instr[4:3], + i_instr[12], {OPCODE_BRANCH}}; + end + endcase + end + + // C2 + + // Register address checks for RV32E are performed in the regular instruction decoder. + // If this check fails, an illegal instruction exception is triggered and the controller + // writes the actual faulting instruction to mtval. + 2'b10: begin + case (i_instr[15:14]) + 2'b00: begin + // c.slli -> slli rd, rd, shamt + // (c.ssli hints are translated into a slli hint) + comp_instr = {7'b0, i_instr[6:2], i_instr[11:7], 3'b001, i_instr[11:7], {OPCODE_OP_IMM}}; + end + + 2'b01: begin + // c.lwsp -> lw rd, imm(x2) + comp_instr = {4'b0, i_instr[3:2], i_instr[12], i_instr[6:4], 2'b00, 5'h02, + 3'b010, i_instr[11:7], OPCODE_LOAD}; + end + + 2'b10: begin + if (i_instr[12] == 1'b0) begin + if (i_instr[6:2] != 5'b0) begin + // c.mv -> add rd/rs1, x0, rs2 + // (c.mv hints are translated into an add hint) + comp_instr = {7'b0, i_instr[6:2], 5'b0, 3'b0, i_instr[11:7], {OPCODE_OP}}; + end else begin + // c.jr -> jalr x0, rd/rs1, 0 + comp_instr = {12'b0, i_instr[11:7], 3'b0, 5'b0, {OPCODE_JALR}}; + end + end else begin + if (i_instr[6:2] != 5'b0) begin + // c.add -> add rd, rd, rs2 + // (c.add hints are translated into an add hint) + comp_instr = {7'b0, i_instr[6:2], i_instr[11:7], 3'b0, i_instr[11:7], {OPCODE_OP}}; + end else begin + if (i_instr[11:7] == 5'b0) begin + // c.ebreak -> ebreak + comp_instr = {32'h00_10_00_73}; + end else begin + // c.jalr -> jalr x1, rs1, 0 + comp_instr = {12'b0, i_instr[11:7], 3'b000, 5'b00001, {OPCODE_JALR}}; + end + end + end + end + + 2'b11: begin + // c.swsp -> sw rs2, imm(x2) + comp_instr = {4'b0, i_instr[8:7], i_instr[12], i_instr[6:2], 5'h02, 3'b010, + i_instr[11:9], 2'b00, {OPCODE_STORE}}; + end + endcase + end + + // Incoming instruction is not compressed. + 2'b11: illegal_instr = 1'b1; + + endcase + end + + endmodule + + +`default_nettype none +module serv_csr + #(parameter RESET_STRATEGY = "MINI") + ( + input wire i_clk, + input wire i_rst, + //State + input wire i_init, + input wire i_en, + input wire i_cnt0to3, + input wire i_cnt3, + input wire i_cnt7, + input wire i_cnt_done, + input wire i_mem_op, + input wire i_mtip, + input wire i_trap, + output reg o_new_irq, + //Control + input wire i_e_op, + input wire i_ebreak, + input wire i_mem_cmd, + input wire i_mstatus_en, + input wire i_mie_en, + input wire i_mcause_en, + input wire [1:0] i_csr_source, + input wire i_mret, + input wire i_csr_d_sel, + //Data + input wire i_rf_csr_out, + output wire o_csr_in, + input wire i_csr_imm, + input wire i_rs1, + output wire o_q); + + localparam [1:0] + CSR_SOURCE_CSR = 2'b00, + CSR_SOURCE_EXT = 2'b01, + CSR_SOURCE_SET = 2'b10, + CSR_SOURCE_CLR = 2'b11; + + reg mstatus_mie; + reg mstatus_mpie; + reg mie_mtie; + + reg mcause31; + reg [3:0] mcause3_0; + wire mcause; + + wire csr_in; + wire csr_out; + + reg timer_irq_r; + + wire d = i_csr_d_sel ? i_csr_imm : i_rs1; + + assign csr_in = (i_csr_source == CSR_SOURCE_EXT) ? d : + (i_csr_source == CSR_SOURCE_SET) ? csr_out | d : + (i_csr_source == CSR_SOURCE_CLR) ? csr_out & ~d : + (i_csr_source == CSR_SOURCE_CSR) ? csr_out : + 1'bx; + + assign csr_out = (i_mstatus_en & mstatus_mie & i_cnt3) | + i_rf_csr_out | + (i_mcause_en & i_en & mcause); + + assign o_q = csr_out; + + wire timer_irq = i_mtip & mstatus_mie & mie_mtie; + + assign mcause = i_cnt0to3 ? mcause3_0[0] : //[3:0] + i_cnt_done ? mcause31 //[31] + : 1'b0; + + assign o_csr_in = csr_in; + + always @(posedge i_clk) begin + if (!i_init & i_cnt_done) begin + timer_irq_r <= timer_irq; + o_new_irq <= timer_irq & !timer_irq_r; + end + + if (i_mie_en & i_cnt7) + mie_mtie <= csr_in; + + /* + The mie bit in mstatus gets updated under three conditions + + When a trap is taken, the bit is cleared + During an mret instruction, the bit is restored from mpie + During a mstatus CSR access instruction it's assigned when + bit 3 gets updated + + These conditions are all mutually exclusibe + */ + if ((i_trap & i_cnt_done) | i_mstatus_en & i_cnt3 | i_mret) + mstatus_mie <= !i_trap & (i_mret ? mstatus_mpie : csr_in); + + /* + Note: To save resources mstatus_mpie (mstatus bit 7) is not + readable or writable from sw + */ + if (i_trap & i_cnt_done) + mstatus_mpie <= mstatus_mie; + + /* + The four lowest bits in mcause hold the exception code + + These bits get updated under three conditions + + During an mcause CSR access function, they are assigned when + bits 0 to 3 gets updated + + During an external interrupt the exception code is set to + 7, since SERV only support timer interrupts + + During an exception, the exception code is assigned to indicate + if it was caused by an ebreak instruction (3), + ecall instruction (11), misaligned load (4), misaligned store (6) + or misaligned jump (0) + + The expressions below are derived from the following truth table + irq => 0111 (timer=7) + e_op => x011 (ebreak=3, ecall=11) + mem => 01x0 (store=6, load=4) + ctrl => 0000 (jump=0) + */ + if (i_mcause_en & i_en & i_cnt0to3 | (i_trap & i_cnt_done)) begin + mcause3_0[3] <= (i_e_op & !i_ebreak) | (!i_trap & csr_in); + mcause3_0[2] <= o_new_irq | i_mem_op | (!i_trap & mcause3_0[3]); + mcause3_0[1] <= o_new_irq | i_e_op | (i_mem_op & i_mem_cmd) | (!i_trap & mcause3_0[2]); + mcause3_0[0] <= o_new_irq | i_e_op | (!i_trap & mcause3_0[1]); + end + if (i_mcause_en & i_cnt_done | i_trap) + mcause31 <= i_trap ? o_new_irq : csr_in; + if (i_rst) + if (RESET_STRATEGY != "NONE") begin + o_new_irq <= 1'b0; + mie_mtie <= 1'b0; + end + end + +endmodule +`default_nettype none +module serv_ctrl + #(parameter RESET_STRATEGY = "MINI", + parameter RESET_PC = 32'd0, + parameter WITH_CSR = 1) + ( + input wire clk, + input wire i_rst, + //State + input wire i_pc_en, + input wire i_cnt12to31, + input wire i_cnt0, + input wire i_cnt1, + input wire i_cnt2, + //Control + input wire i_jump, + input wire i_jal_or_jalr, + input wire i_utype, + input wire i_pc_rel, + input wire i_trap, + input wire i_iscomp, + //Data + input wire i_imm, + input wire i_buf, + input wire i_csr_pc, + output wire o_rd, + output wire o_bad_pc, + //External + output reg [31:0] o_ibus_adr); + + wire pc_plus_4; + wire pc_plus_4_cy; + reg pc_plus_4_cy_r; + wire pc_plus_offset; + wire pc_plus_offset_cy; + reg pc_plus_offset_cy_r; + wire pc_plus_offset_aligned; + wire plus_4; + + wire pc = o_ibus_adr[0]; + + wire new_pc; + + wire offset_a; + wire offset_b; + + /* If i_iscomp=1: increment pc by 2 else increment pc by 4 */ + + assign plus_4 = i_iscomp ? i_cnt1 : i_cnt2; + + assign o_bad_pc = pc_plus_offset_aligned; + + assign {pc_plus_4_cy,pc_plus_4} = pc+plus_4+pc_plus_4_cy_r; + + generate + if (|WITH_CSR) + assign new_pc = i_trap ? (i_csr_pc & !i_cnt0) : i_jump ? pc_plus_offset_aligned : pc_plus_4; + else + assign new_pc = i_jump ? pc_plus_offset_aligned : pc_plus_4; + endgenerate + assign o_rd = (i_utype & pc_plus_offset_aligned) | (pc_plus_4 & i_jal_or_jalr); + + assign offset_a = i_pc_rel & pc; + assign offset_b = i_utype ? (i_imm & i_cnt12to31): i_buf; + assign {pc_plus_offset_cy,pc_plus_offset} = offset_a+offset_b+pc_plus_offset_cy_r; + + assign pc_plus_offset_aligned = pc_plus_offset & !i_cnt0; + + initial if (RESET_STRATEGY == "NONE") o_ibus_adr = RESET_PC; + + always @(posedge clk) begin + pc_plus_4_cy_r <= i_pc_en & pc_plus_4_cy; + pc_plus_offset_cy_r <= i_pc_en & pc_plus_offset_cy; + + if (RESET_STRATEGY == "NONE") begin + if (i_pc_en) + o_ibus_adr <= {new_pc, o_ibus_adr[31:1]}; + end else begin + if (i_pc_en | i_rst) + o_ibus_adr <= i_rst ? RESET_PC : {new_pc, o_ibus_adr[31:1]}; + end + end +endmodule +`default_nettype none +module serv_decode + #(parameter [0:0] PRE_REGISTER = 1, + parameter [0:0] MDU = 0) + ( + input wire clk, + //Input + input wire [31:2] i_wb_rdt, + input wire i_wb_en, + //To state + output reg o_sh_right, + output reg o_bne_or_bge, + output reg o_cond_branch, + output reg o_e_op, + output reg o_ebreak, + output reg o_branch_op, + output reg o_shift_op, + output reg o_slt_or_branch, + output reg o_rd_op, + output reg o_two_stage_op, + output reg o_dbus_en, + //MDU + output reg o_mdu_op, + //Extension + output reg [2:0] o_ext_funct3, + //To bufreg + output reg o_bufreg_rs1_en, + output reg o_bufreg_imm_en, + output reg o_bufreg_clr_lsb, + output reg o_bufreg_sh_signed, + //To ctrl + output reg o_ctrl_jal_or_jalr, + output reg o_ctrl_utype, + output reg o_ctrl_pc_rel, + output reg o_ctrl_mret, + //To alu + output reg o_alu_sub, + output reg [1:0] o_alu_bool_op, + output reg o_alu_cmp_eq, + output reg o_alu_cmp_sig, + output reg [2:0] o_alu_rd_sel, + //To mem IF + output reg o_mem_signed, + output reg o_mem_word, + output reg o_mem_half, + output reg o_mem_cmd, + //To CSR + output reg o_csr_en, + output reg [1:0] o_csr_addr, + output reg o_csr_mstatus_en, + output reg o_csr_mie_en, + output reg o_csr_mcause_en, + output reg [1:0] o_csr_source, + output reg o_csr_d_sel, + output reg o_csr_imm_en, + output reg o_mtval_pc, + //To top + output reg [3:0] o_immdec_ctrl, + output reg [3:0] o_immdec_en, + output reg o_op_b_source, + //To RF IF + output reg o_rd_mem_en, + output reg o_rd_csr_en, + output reg o_rd_alu_en); + + reg [4:0] opcode; + reg [2:0] funct3; + reg op20; + reg op21; + reg op22; + reg op26; + + reg imm25; + reg imm30; + + wire co_mdu_op = MDU & (opcode == 5'b01100) & imm25; + + wire co_two_stage_op = + ~opcode[2] | (funct3[0] & ~funct3[1] & ~opcode[0] & ~opcode[4]) | + (funct3[1] & ~funct3[2] & ~opcode[0] & ~opcode[4]) | co_mdu_op; + wire co_shift_op = (opcode[2] & ~funct3[1]) & !co_mdu_op; + wire co_slt_or_branch = (opcode[4] | (funct3[1] & opcode[2]) | (imm30 & opcode[2] & opcode[3] & ~funct3[2])) & !co_mdu_op; + wire co_branch_op = opcode[4]; + wire co_dbus_en = ~opcode[2] & ~opcode[4]; + wire co_mtval_pc = opcode[4]; + wire co_mem_word = funct3[1]; + wire co_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4] & !co_mdu_op; + wire co_rd_mem_en = (!opcode[2] & !opcode[0]) | co_mdu_op; + wire [2:0] co_ext_funct3 = funct3; + + //jal,branch = imm + //jalr = rs1+imm + //mem = rs1+imm + //shift = rs1 + wire co_bufreg_rs1_en = !opcode[4] | (!opcode[1] & opcode[0]); + wire co_bufreg_imm_en = !opcode[2]; + + //Clear LSB of immediate for BRANCH and JAL ops + //True for BRANCH and JAL + //False for JALR/LOAD/STORE/OP/OPIMM? + wire co_bufreg_clr_lsb = opcode[4] & ((opcode[1:0] == 2'b00) | (opcode[1:0] == 2'b11)); + + //Conditional branch + //True for BRANCH + //False for JAL/JALR + wire co_cond_branch = !opcode[0]; + + wire co_ctrl_utype = !opcode[4] & opcode[2] & opcode[0]; + wire co_ctrl_jal_or_jalr = opcode[4] & opcode[0]; + + //PC-relative operations + //True for jal, b* auipc, ebreak + //False for jalr, lui + wire co_ctrl_pc_rel = (opcode[2:0] == 3'b000) | + (opcode[1:0] == 2'b11) | + (opcode[4] & opcode[2]) & op20| + (opcode[4:3] == 2'b00); + //Write to RD + //True for OP-IMM, AUIPC, OP, LUI, SYSTEM, JALR, JAL, LOAD + //False for STORE, BRANCH, MISC-MEM + wire co_rd_op = (opcode[2] | + (!opcode[2] & opcode[4] & opcode[0]) | + (!opcode[2] & !opcode[3] & !opcode[0])); + + // + //funct3 + // + + wire co_sh_right = funct3[2]; + wire co_bne_or_bge = funct3[0]; + + //Matches system ops except eceall/ebreak/mret + wire csr_op = opcode[4] & opcode[2] & (|funct3); + + + //op20 + wire co_ebreak = op20; + + + //opcode & funct3 & op21 + + wire co_ctrl_mret = opcode[4] & opcode[2] & op21 & !(|funct3); + //Matches system opcodes except CSR accesses (funct3 == 0) + //and mret (!op21) + wire co_e_op = opcode[4] & opcode[2] & !op21 & !(|funct3); + + //opcode & funct3 & imm30 + + wire co_bufreg_sh_signed = imm30; + + /* + True for sub, b*, slt* + False for add* + op opcode f3 i30 + b* 11000 xxx x t + addi 00100 000 x f + slt* 0x100 01x x t + add 01100 000 0 f + sub 01100 000 1 t + */ + wire co_alu_sub = funct3[1] | funct3[0] | (opcode[3] & imm30) | opcode[4]; + + /* + Bits 26, 22, 21 and 20 are enough to uniquely identify the eight supported CSR regs + mtvec, mscratch, mepc and mtval are stored externally (normally in the RF) and are + treated differently from mstatus, mie and mcause which are stored in serv_csr. + + The former get a 2-bit address as seen below while the latter get a + one-hot enable signal each. + + Hex|2 222|Reg |csr + adr|6 210|name |addr + ---|-----|--------|---- + 300|0_000|mstatus | xx + 304|0_100|mie | xx + 305|0_101|mtvec | 01 + 340|1_000|mscratch| 00 + 341|1_001|mepc | 10 + 342|1_010|mcause | xx + 343|1_011|mtval | 11 + + */ + + //true for mtvec,mscratch,mepc and mtval + //false for mstatus, mie, mcause + wire csr_valid = op20 | (op26 & !op21); + + wire co_rd_csr_en = csr_op; + + wire co_csr_en = csr_op & csr_valid; + wire co_csr_mstatus_en = csr_op & !op26 & !op22; + wire co_csr_mie_en = csr_op & !op26 & op22 & !op20; + wire co_csr_mcause_en = csr_op & op21 & !op20; + + wire [1:0] co_csr_source = funct3[1:0]; + wire co_csr_d_sel = funct3[2]; + wire co_csr_imm_en = opcode[4] & opcode[2] & funct3[2]; + wire [1:0] co_csr_addr = {op26 & op20, !op26 | op21}; + + wire co_alu_cmp_eq = funct3[2:1] == 2'b00; + + wire co_alu_cmp_sig = ~((funct3[0] & funct3[1]) | (funct3[1] & funct3[2])); + + wire co_mem_cmd = opcode[3]; + wire co_mem_signed = ~funct3[2]; + wire co_mem_half = funct3[0]; + + wire [1:0] co_alu_bool_op = funct3[1:0]; + + wire [3:0] co_immdec_ctrl; + //True for S (STORE) or B (BRANCH) type instructions + //False for J type instructions + assign co_immdec_ctrl[0] = opcode[3:0] == 4'b1000; + //True for OP-IMM, LOAD, STORE, JALR (I S) + //False for LUI, AUIPC, JAL (U J) + assign co_immdec_ctrl[1] = (opcode[1:0] == 2'b00) | (opcode[2:1] == 2'b00); + assign co_immdec_ctrl[2] = opcode[4] & !opcode[0]; + assign co_immdec_ctrl[3] = opcode[4]; + + wire [3:0] co_immdec_en; + assign co_immdec_en[3] = opcode[4] | opcode[3] | opcode[2] | !opcode[0]; //B I J S U + assign co_immdec_en[2] = (opcode[4] & opcode[2]) | !opcode[3] | opcode[0]; // I J U + assign co_immdec_en[1] = (opcode[2:1] == 2'b01) | (opcode[2] & opcode[0]) | co_csr_imm_en;// J U + assign co_immdec_en[0] = ~co_rd_op; //B S + + wire [2:0] co_alu_rd_sel; + assign co_alu_rd_sel[0] = (funct3 == 3'b000); // Add/sub + assign co_alu_rd_sel[1] = (funct3[2:1] == 2'b01); //SLT* + assign co_alu_rd_sel[2] = funct3[2]; //Bool + + //0 (OP_B_SOURCE_IMM) when OPIMM + //1 (OP_B_SOURCE_RS2) when BRANCH or OP + wire co_op_b_source = opcode[3]; + + generate + if (PRE_REGISTER) begin + + always @(posedge clk) begin + if (i_wb_en) begin + funct3 <= i_wb_rdt[14:12]; + imm30 <= i_wb_rdt[30]; + imm25 <= i_wb_rdt[25]; + opcode <= i_wb_rdt[6:2]; + op20 <= i_wb_rdt[20]; + op21 <= i_wb_rdt[21]; + op22 <= i_wb_rdt[22]; + op26 <= i_wb_rdt[26]; + end + end + + always @(*) begin + o_sh_right = co_sh_right; + o_bne_or_bge = co_bne_or_bge; + o_cond_branch = co_cond_branch; + o_dbus_en = co_dbus_en; + o_mtval_pc = co_mtval_pc; + o_two_stage_op = co_two_stage_op; + o_e_op = co_e_op; + o_ebreak = co_ebreak; + o_branch_op = co_branch_op; + o_shift_op = co_shift_op; + o_slt_or_branch = co_slt_or_branch; + o_rd_op = co_rd_op; + o_mdu_op = co_mdu_op; + o_ext_funct3 = co_ext_funct3; + o_bufreg_rs1_en = co_bufreg_rs1_en; + o_bufreg_imm_en = co_bufreg_imm_en; + o_bufreg_clr_lsb = co_bufreg_clr_lsb; + o_bufreg_sh_signed = co_bufreg_sh_signed; + o_ctrl_jal_or_jalr = co_ctrl_jal_or_jalr; + o_ctrl_utype = co_ctrl_utype; + o_ctrl_pc_rel = co_ctrl_pc_rel; + o_ctrl_mret = co_ctrl_mret; + o_alu_sub = co_alu_sub; + o_alu_bool_op = co_alu_bool_op; + o_alu_cmp_eq = co_alu_cmp_eq; + o_alu_cmp_sig = co_alu_cmp_sig; + o_alu_rd_sel = co_alu_rd_sel; + o_mem_signed = co_mem_signed; + o_mem_word = co_mem_word; + o_mem_half = co_mem_half; + o_mem_cmd = co_mem_cmd; + o_csr_en = co_csr_en; + o_csr_addr = co_csr_addr; + o_csr_mstatus_en = co_csr_mstatus_en; + o_csr_mie_en = co_csr_mie_en; + o_csr_mcause_en = co_csr_mcause_en; + o_csr_source = co_csr_source; + o_csr_d_sel = co_csr_d_sel; + o_csr_imm_en = co_csr_imm_en; + o_immdec_ctrl = co_immdec_ctrl; + o_immdec_en = co_immdec_en; + o_op_b_source = co_op_b_source; + o_rd_csr_en = co_rd_csr_en; + o_rd_alu_en = co_rd_alu_en; + o_rd_mem_en = co_rd_mem_en; + end + + end else begin + + always @(*) begin + funct3 = i_wb_rdt[14:12]; + imm30 = i_wb_rdt[30]; + imm25 = i_wb_rdt[25]; + opcode = i_wb_rdt[6:2]; + op20 = i_wb_rdt[20]; + op21 = i_wb_rdt[21]; + op22 = i_wb_rdt[22]; + op26 = i_wb_rdt[26]; + end + + always @(posedge clk) begin + if (i_wb_en) begin + o_sh_right <= co_sh_right; + o_bne_or_bge <= co_bne_or_bge; + o_cond_branch <= co_cond_branch; + o_e_op <= co_e_op; + o_ebreak <= co_ebreak; + o_two_stage_op <= co_two_stage_op; + o_dbus_en <= co_dbus_en; + o_mtval_pc <= co_mtval_pc; + o_branch_op <= co_branch_op; + o_shift_op <= co_shift_op; + o_slt_or_branch <= co_slt_or_branch; + o_rd_op <= co_rd_op; + o_mdu_op <= co_mdu_op; + o_ext_funct3 <= co_ext_funct3; + o_bufreg_rs1_en <= co_bufreg_rs1_en; + o_bufreg_imm_en <= co_bufreg_imm_en; + o_bufreg_clr_lsb <= co_bufreg_clr_lsb; + o_bufreg_sh_signed <= co_bufreg_sh_signed; + o_ctrl_jal_or_jalr <= co_ctrl_jal_or_jalr; + o_ctrl_utype <= co_ctrl_utype; + o_ctrl_pc_rel <= co_ctrl_pc_rel; + o_ctrl_mret <= co_ctrl_mret; + o_alu_sub <= co_alu_sub; + o_alu_bool_op <= co_alu_bool_op; + o_alu_cmp_eq <= co_alu_cmp_eq; + o_alu_cmp_sig <= co_alu_cmp_sig; + o_alu_rd_sel <= co_alu_rd_sel; + o_mem_signed <= co_mem_signed; + o_mem_word <= co_mem_word; + o_mem_half <= co_mem_half; + o_mem_cmd <= co_mem_cmd; + o_csr_en <= co_csr_en; + o_csr_addr <= co_csr_addr; + o_csr_mstatus_en <= co_csr_mstatus_en; + o_csr_mie_en <= co_csr_mie_en; + o_csr_mcause_en <= co_csr_mcause_en; + o_csr_source <= co_csr_source; + o_csr_d_sel <= co_csr_d_sel; + o_csr_imm_en <= co_csr_imm_en; + o_immdec_ctrl <= co_immdec_ctrl; + o_immdec_en <= co_immdec_en; + o_op_b_source <= co_op_b_source; + o_rd_csr_en <= co_rd_csr_en; + o_rd_alu_en <= co_rd_alu_en; + o_rd_mem_en <= co_rd_mem_en; + end + end + + end + endgenerate + +endmodule +`default_nettype none +module serv_immdec + #(parameter SHARED_RFADDR_IMM_REGS = 1) + ( + input wire i_clk, + //State + input wire i_cnt_en, + input wire i_cnt_done, + //Control + input wire [3:0] i_immdec_en, + input wire i_csr_imm_en, + input wire [3:0] i_ctrl, + output wire [4:0] o_rd_addr, + output wire [4:0] o_rs1_addr, + output wire [4:0] o_rs2_addr, + //Data + output wire o_csr_imm, + output wire o_imm, + //External + input wire i_wb_en, + input wire [31:7] i_wb_rdt); + + reg imm31; + + reg [8:0] imm19_12_20; + reg imm7; + reg [5:0] imm30_25; + reg [4:0] imm24_20; + reg [4:0] imm11_7; + + assign o_csr_imm = imm19_12_20[4]; + + wire signbit = imm31 & !i_csr_imm_en; + + generate + if (SHARED_RFADDR_IMM_REGS) begin + assign o_rs1_addr = imm19_12_20[8:4]; + assign o_rs2_addr = imm24_20; + assign o_rd_addr = imm11_7; + + always @(posedge i_clk) begin + if (i_wb_en) begin + /* CSR immediates are always zero-extended, hence clear the signbit */ + imm31 <= i_wb_rdt[31]; + end + if (i_wb_en | (i_cnt_en & i_immdec_en[1])) + imm19_12_20 <= i_wb_en ? {i_wb_rdt[19:12],i_wb_rdt[20]} : {i_ctrl[3] ? signbit : imm24_20[0], imm19_12_20[8:1]}; + if (i_wb_en | (i_cnt_en)) + imm7 <= i_wb_en ? i_wb_rdt[7] : signbit; + + if (i_wb_en | (i_cnt_en & i_immdec_en[3])) + imm30_25 <= i_wb_en ? i_wb_rdt[30:25] : {i_ctrl[2] ? imm7 : i_ctrl[1] ? signbit : imm19_12_20[0], imm30_25[5:1]}; + + if (i_wb_en | (i_cnt_en & i_immdec_en[2])) + imm24_20 <= i_wb_en ? i_wb_rdt[24:20] : {imm30_25[0], imm24_20[4:1]}; + + if (i_wb_en | (i_cnt_en & i_immdec_en[0])) + imm11_7 <= i_wb_en ? i_wb_rdt[11:7] : {imm30_25[0], imm11_7[4:1]}; + end + end else begin + reg [4:0] rd_addr; + reg [4:0] rs1_addr; + reg [4:0] rs2_addr; + + assign o_rd_addr = rd_addr; + assign o_rs1_addr = rs1_addr; + assign o_rs2_addr = rs2_addr; + always @(posedge i_clk) begin + if (i_wb_en) begin + /* CSR immediates are always zero-extended, hence clear the signbit */ + imm31 <= i_wb_rdt[31]; + imm19_12_20 <= {i_wb_rdt[19:12],i_wb_rdt[20]}; + imm7 <= i_wb_rdt[7]; + imm30_25 <= i_wb_rdt[30:25]; + imm24_20 <= i_wb_rdt[24:20]; + imm11_7 <= i_wb_rdt[11:7]; + + rd_addr <= i_wb_rdt[11:7]; + rs1_addr <= i_wb_rdt[19:15]; + rs2_addr <= i_wb_rdt[24:20]; + end + if (i_cnt_en) begin + imm19_12_20 <= {i_ctrl[3] ? signbit : imm24_20[0], imm19_12_20[8:1]}; + imm7 <= signbit; + imm30_25 <= {i_ctrl[2] ? imm7 : i_ctrl[1] ? signbit : imm19_12_20[0], imm30_25[5:1]}; + imm24_20 <= {imm30_25[0], imm24_20[4:1]}; + imm11_7 <= {imm30_25[0], imm11_7[4:1]}; + end + end + end + endgenerate + + assign o_imm = i_cnt_done ? signbit : i_ctrl[0] ? imm11_7[0] : imm24_20[0]; + +endmodule +`default_nettype none +module serv_mem_if + #(parameter [0:0] WITH_CSR = 1) + ( + input wire i_clk, + //State + input wire [1:0] i_bytecnt, + input wire [1:0] i_lsb, + output wire o_byte_valid, + output wire o_misalign, + //Control + input wire i_signed, + input wire i_word, + input wire i_half, + //MDU + input wire i_mdu_op, + //Data + input wire i_bufreg2_q, + output wire o_rd, + //External interface + output wire [3:0] o_wb_sel); + + reg signbit; + + /* + Before a store operation, the data to be written needs to be shifted into + place. Depending on the address alignment, we need to shift different + amounts. One formula for calculating this is to say that we shift when + i_lsb + i_bytecnt < 4. Unfortunately, the synthesis tools don't seem to be + clever enough so the hideous expression below is used to achieve the same + thing in a more optimal way. + */ + assign o_byte_valid + = (!i_lsb[0] & !i_lsb[1]) | + (!i_bytecnt[0] & !i_bytecnt[1]) | + (!i_bytecnt[1] & !i_lsb[1]) | + (!i_bytecnt[1] & !i_lsb[0]) | + (!i_bytecnt[0] & !i_lsb[1]); + + wire dat_valid = + i_mdu_op | + i_word | + (i_bytecnt == 2'b00) | + (i_half & !i_bytecnt[1]); + + assign o_rd = dat_valid ? i_bufreg2_q : signbit & i_signed; + + assign o_wb_sel[3] = (i_lsb == 2'b11) | i_word | (i_half & i_lsb[1]); + assign o_wb_sel[2] = (i_lsb == 2'b10) | i_word; + assign o_wb_sel[1] = (i_lsb == 2'b01) | i_word | (i_half & !i_lsb[1]); + assign o_wb_sel[0] = (i_lsb == 2'b00); + + always @(posedge i_clk) begin + if (dat_valid) + signbit <= i_bufreg2_q; + end + + /* + mem_misalign is checked after the init stage to decide whether to do a data + bus transaction or go to the trap state. It is only guaranteed to be correct + at this time + */ + assign o_misalign = WITH_CSR & ((i_lsb[0] & (i_word | i_half)) | (i_lsb[1] & i_word)); + +endmodule +`default_nettype none +module serv_rf_if + #(parameter WITH_CSR = 1) + (//RF Interface + input wire i_cnt_en, + output wire [4+WITH_CSR:0] o_wreg0, + output wire [4+WITH_CSR:0] o_wreg1, + output wire o_wen0, + output wire o_wen1, + output wire o_wdata0, + output wire o_wdata1, + output wire [4+WITH_CSR:0] o_rreg0, + output wire [4+WITH_CSR:0] o_rreg1, + input wire i_rdata0, + input wire i_rdata1, + + //Trap interface + input wire i_trap, + input wire i_mret, + input wire i_mepc, + input wire i_mtval_pc, + input wire i_bufreg_q, + input wire i_bad_pc, + output wire o_csr_pc, + //CSR interface + input wire i_csr_en, + input wire [1:0] i_csr_addr, + input wire i_csr, + output wire o_csr, + //RD write port + input wire i_rd_wen, + input wire [4:0] i_rd_waddr, + input wire i_ctrl_rd, + input wire i_alu_rd, + input wire i_rd_alu_en, + input wire i_csr_rd, + input wire i_rd_csr_en, + input wire i_mem_rd, + input wire i_rd_mem_en, + + //RS1 read port + input wire [4:0] i_rs1_raddr, + output wire o_rs1, + //RS2 read port + input wire [4:0] i_rs2_raddr, + output wire o_rs2); + + + /* + ********** Write side *********** + */ + + wire rd_wen = i_rd_wen & (|i_rd_waddr); + + generate + if (|WITH_CSR) begin + wire rd = (i_ctrl_rd ) | + (i_alu_rd & i_rd_alu_en) | + (i_csr_rd & i_rd_csr_en) | + (i_mem_rd & i_rd_mem_en); + + wire mtval = i_mtval_pc ? i_bad_pc : i_bufreg_q; + + assign o_wdata0 = i_trap ? mtval : rd; + assign o_wdata1 = i_trap ? i_mepc : i_csr; + + /* Port 0 handles writes to mtval during traps and rd otherwise + * Port 1 handles writes to mepc during traps and csr accesses otherwise + * + * GPR registers are mapped to address 0-31 (bits 0xxxxx). + * Following that are four CSR registers + * mscratch 100000 + * mtvec 100001 + * mepc 100010 + * mtval 100011 + */ + + assign o_wreg0 = i_trap ? {6'b100011} : {1'b0,i_rd_waddr}; + assign o_wreg1 = i_trap ? {6'b100010} : {4'b1000,i_csr_addr}; + + assign o_wen0 = i_cnt_en & (i_trap | rd_wen); + assign o_wen1 = i_cnt_en & (i_trap | i_csr_en); + + /* + ********** Read side *********** + */ + + //0 : RS1 + //1 : RS2 / CSR + + assign o_rreg0 = {1'b0, i_rs1_raddr}; + + /* + The address of the second read port (o_rreg1) can get assigned from four + different sources + + Normal operations : i_rs2_raddr + CSR access : i_csr_addr + trap : MTVEC + mret : MEPC + + Address 0-31 in the RF are assigned to the GPRs. After that follows the four + CSRs on addresses 32-35 + + 32 MSCRATCH + 33 MTVEC + 34 MEPC + 35 MTVAL + + The expression below is an optimized version of this logic + */ + wire sel_rs2 = !(i_trap | i_mret | i_csr_en); + assign o_rreg1 = {~sel_rs2, + i_rs2_raddr[4:2] & {3{sel_rs2}}, + {1'b0,i_trap} | {i_mret,1'b0} | ({2{i_csr_en}} & i_csr_addr) | ({2{sel_rs2}} & i_rs2_raddr[1:0])}; + + assign o_rs1 = i_rdata0; + assign o_rs2 = i_rdata1; + assign o_csr = i_rdata1 & i_csr_en; + assign o_csr_pc = i_rdata1; + + end else begin + wire rd = (i_ctrl_rd ) | + (i_alu_rd & i_rd_alu_en) | + (i_mem_rd & i_rd_mem_en); + + assign o_wdata0 = rd; + assign o_wdata1 = 1'b0; + + assign o_wreg0 = i_rd_waddr; + assign o_wreg1 = 5'd0; + + assign o_wen0 = i_cnt_en & rd_wen; + assign o_wen1 = 1'b0; + + /* + ********** Read side *********** + */ + + assign o_rreg0 = i_rs1_raddr; + assign o_rreg1 = i_rs2_raddr; + + assign o_rs1 = i_rdata0; + assign o_rs2 = i_rdata1; + assign o_csr = 1'b0; + assign o_csr_pc = 1'b0; + end // else: !if(WITH_CSR) + endgenerate +endmodule +module serv_rf_ram + #(parameter width=0, + parameter csr_regs=4, + parameter depth=32*(32+csr_regs)/width) + (input wire i_clk, + input wire [$clog2(depth)-1:0] i_waddr, + input wire [width-1:0] i_wdata, + input wire i_wen, + input wire [$clog2(depth)-1:0] i_raddr, + input wire i_ren, + output wire [width-1:0] o_rdata); + + reg [width-1:0] memory [0:depth-1]; + reg [width-1:0] rdata ; + + always @(posedge i_clk) begin + if (i_wen) + memory[i_waddr] <= i_wdata; + rdata <= i_ren ? memory[i_raddr] : {width{1'bx}}; + end + + /* Reads from reg x0 needs to return 0 + Check that the part of the read address corresponding to the register + is zero and gate the output + width LSB of reg index $clog2(width) + 2 4 1 + 4 3 2 + 8 2 3 + 16 1 4 + 32 0 5 + */ + reg regzero; + + always @(posedge i_clk) + regzero <= !(|i_raddr[$clog2(depth)-1:5-$clog2(width)]); + + assign o_rdata = rdata & ~{width{regzero}}; + +`ifdef SERV_CLEAR_RAM + integer i; + initial + for (i=0;i2) + always @(posedge i_clk) begin + rdata1 <= {1'b0,rdata1[width-2:1]}; //Optimize? + if (rtrig1) + rdata1[width-2:0] <= i_rdata[width-1:1]; + end + else + always @(posedge i_clk) if (rtrig1) rdata1 <= i_rdata[1]; + endgenerate + + always @(posedge i_clk) begin + if (&rcnt | i_rreq) + rgate <= i_rreq; + + rtrig1 <= rtrig0; + rcnt <= rcnt+5'd1; + if (i_rreq | i_wreq) + rcnt <= {3'd0,i_wreq,1'b0}; + + rreq_r <= i_rreq; + rgnt <= rreq_r; + + rdata0 <= {1'b0,rdata0[width-1:1]}; + if (rtrig0) + rdata0 <= i_rdata; + + if (i_rst) begin + if (reset_strategy != "NONE") begin + rgate <= 1'b0; + rgnt <= 1'b0; + rreq_r <= 1'b0; + rcnt <= 5'd0; + end + end + end + + + +endmodule +`default_nettype none + +module serv_rf_top + #(parameter RESET_PC = 32'd0, + /* COMPRESSED=1: Enable the compressed decoder and allowed misaligned jump of pc + COMPRESSED=0: Disable the compressed decoder and does not allow the misaligned jump of pc + */ + parameter [0:0] COMPRESSED = 0, + /* + ALIGN = 1: Fetch the aligned instruction by making two bus transactions if the misaligned address + is given to the instruction bus. + */ + parameter [0:0] ALIGN = COMPRESSED, + /* Multiplication and Division Unit + This parameter enables the interface for connecting SERV and MDU + */ + parameter [0:0] MDU = 0, + /* Register signals before or after the decoder + 0 : Register after the decoder. Faster but uses more resources + 1 : (default) Register before the decoder. Slower but uses less resources + */ + parameter PRE_REGISTER = 1, + /* Amount of reset applied to design + "NONE" : No reset at all. Relies on a POR to set correct initialization + values and that core isn't reset during runtime + "MINI" : Standard setting. Resets the minimal amount of FFs needed to + restart execution from the instruction at RESET_PC + */ + parameter RESET_STRATEGY = "MINI", + parameter WITH_CSR = 1, + parameter RF_WIDTH = 4, + parameter RF_L2D = $clog2((32+(WITH_CSR*4))*32/RF_WIDTH)) + ( + input wire clk, + input wire i_rst, + input wire i_timer_irq, +`ifdef RISCV_FORMAL + output wire rvfi_valid, + output wire [63:0] rvfi_order, + output wire [31:0] rvfi_insn, + output wire rvfi_trap, + output wire rvfi_halt, + output wire rvfi_intr, + output wire [1:0] rvfi_mode, + output wire [1:0] rvfi_ixl, + output wire [4:0] rvfi_rs1_addr, + output wire [4:0] rvfi_rs2_addr, + output wire [31:0] rvfi_rs1_rdata, + output wire [31:0] rvfi_rs2_rdata, + output wire [4:0] rvfi_rd_addr, + output wire [31:0] rvfi_rd_wdata, + output wire [31:0] rvfi_pc_rdata, + output wire [31:0] rvfi_pc_wdata, + output wire [31:0] rvfi_mem_addr, + output wire [3:0] rvfi_mem_rmask, + output wire [3:0] rvfi_mem_wmask, + output wire [31:0] rvfi_mem_rdata, + output wire [31:0] rvfi_mem_wdata, +`endif + output wire [31:0] o_ibus_adr, + output wire o_ibus_cyc, + input wire [31:0] i_ibus_rdt, + input wire i_ibus_ack, + output wire [31:0] o_dbus_adr, + output wire [31:0] o_dbus_dat, + output wire [3:0] o_dbus_sel, + output wire o_dbus_we , + output wire o_dbus_cyc, + input wire [31:0] i_dbus_rdt, + input wire i_dbus_ack, + + // Extension + output wire [31:0] o_ext_rs1, + output wire [31:0] o_ext_rs2, + output wire [ 2:0] o_ext_funct3, + input wire [31:0] i_ext_rd, + input wire i_ext_ready, + // MDU + output wire o_mdu_valid); + + localparam CSR_REGS = WITH_CSR*4; + + wire rf_wreq; + wire rf_rreq; + wire [4+WITH_CSR:0] wreg0; + wire [4+WITH_CSR:0] wreg1; + wire wen0; + wire wen1; + wire wdata0; + wire wdata1; + wire [4+WITH_CSR:0] rreg0; + wire [4+WITH_CSR:0] rreg1; + wire rf_ready; + wire rdata0; + wire rdata1; + + wire [RF_L2D-1:0] waddr; + wire [RF_WIDTH-1:0] wdata; + wire wen; + wire [RF_L2D-1:0] raddr; + wire ren; + wire [RF_WIDTH-1:0] rdata; + + serv_rf_ram_if + #(.width (RF_WIDTH), + .reset_strategy (RESET_STRATEGY), + .csr_regs (CSR_REGS)) + rf_ram_if + (.i_clk (clk), + .i_rst (i_rst), + .i_wreq (rf_wreq), + .i_rreq (rf_rreq), + .o_ready (rf_ready), + .i_wreg0 (wreg0), + .i_wreg1 (wreg1), + .i_wen0 (wen0), + .i_wen1 (wen1), + .i_wdata0 (wdata0), + .i_wdata1 (wdata1), + .i_rreg0 (rreg0), + .i_rreg1 (rreg1), + .o_rdata0 (rdata0), + .o_rdata1 (rdata1), + .o_waddr (waddr), + .o_wdata (wdata), + .o_wen (wen), + .o_raddr (raddr), + .o_ren (ren), + .i_rdata (rdata)); + + serv_rf_ram + #(.width (RF_WIDTH), + .csr_regs (CSR_REGS)) + rf_ram + (.i_clk (clk), + .i_waddr (waddr), + .i_wdata (wdata), + .i_wen (wen), + .i_raddr (raddr), + .i_ren (ren), + .o_rdata (rdata)); + + serv_top + #(.RESET_PC (RESET_PC), + .PRE_REGISTER (PRE_REGISTER), + .RESET_STRATEGY (RESET_STRATEGY), + .WITH_CSR (WITH_CSR), + .MDU(MDU), + .COMPRESSED(COMPRESSED), + .ALIGN(ALIGN)) + cpu + ( + .clk (clk), + .i_rst (i_rst), + .i_timer_irq (i_timer_irq), +`ifdef RISCV_FORMAL + .rvfi_valid (rvfi_valid ), + .rvfi_order (rvfi_order ), + .rvfi_insn (rvfi_insn ), + .rvfi_trap (rvfi_trap ), + .rvfi_halt (rvfi_halt ), + .rvfi_intr (rvfi_intr ), + .rvfi_mode (rvfi_mode ), + .rvfi_ixl (rvfi_ixl ), + .rvfi_rs1_addr (rvfi_rs1_addr ), + .rvfi_rs2_addr (rvfi_rs2_addr ), + .rvfi_rs1_rdata (rvfi_rs1_rdata), + .rvfi_rs2_rdata (rvfi_rs2_rdata), + .rvfi_rd_addr (rvfi_rd_addr ), + .rvfi_rd_wdata (rvfi_rd_wdata ), + .rvfi_pc_rdata (rvfi_pc_rdata ), + .rvfi_pc_wdata (rvfi_pc_wdata ), + .rvfi_mem_addr (rvfi_mem_addr ), + .rvfi_mem_rmask (rvfi_mem_rmask), + .rvfi_mem_wmask (rvfi_mem_wmask), + .rvfi_mem_rdata (rvfi_mem_rdata), + .rvfi_mem_wdata (rvfi_mem_wdata), +`endif + .o_rf_rreq (rf_rreq), + .o_rf_wreq (rf_wreq), + .i_rf_ready (rf_ready), + .o_wreg0 (wreg0), + .o_wreg1 (wreg1), + .o_wen0 (wen0), + .o_wen1 (wen1), + .o_wdata0 (wdata0), + .o_wdata1 (wdata1), + .o_rreg0 (rreg0), + .o_rreg1 (rreg1), + .i_rdata0 (rdata0), + .i_rdata1 (rdata1), + + .o_ibus_adr (o_ibus_adr), + .o_ibus_cyc (o_ibus_cyc), + .i_ibus_rdt (i_ibus_rdt), + .i_ibus_ack (i_ibus_ack), + + .o_dbus_adr (o_dbus_adr), + .o_dbus_dat (o_dbus_dat), + .o_dbus_sel (o_dbus_sel), + .o_dbus_we (o_dbus_we), + .o_dbus_cyc (o_dbus_cyc), + .i_dbus_rdt (i_dbus_rdt), + .i_dbus_ack (i_dbus_ack), + + //Extension + .o_ext_funct3 (o_ext_funct3), + .i_ext_ready (i_ext_ready), + .i_ext_rd (i_ext_rd), + .o_ext_rs1 (o_ext_rs1), + .o_ext_rs2 (o_ext_rs2), + //MDU + .o_mdu_valid (o_mdu_valid)); + +endmodule +`default_nettype wire +module serv_state + #(parameter RESET_STRATEGY = "MINI", + parameter [0:0] WITH_CSR = 1, + parameter [0:0] ALIGN =0, + parameter [0:0] MDU = 0) + ( + input wire i_clk, + input wire i_rst, + //State + input wire i_new_irq, + input wire i_alu_cmp, + output wire o_init, + output wire o_cnt_en, + output wire o_cnt0to3, + output wire o_cnt12to31, + output wire o_cnt0, + output wire o_cnt1, + output wire o_cnt2, + output wire o_cnt3, + output wire o_cnt7, + output reg o_cnt_done, + output wire o_bufreg_en, + output wire o_ctrl_pc_en, + output reg o_ctrl_jump, + output wire o_ctrl_trap, + input wire i_ctrl_misalign, + input wire i_sh_done, + input wire i_sh_done_r, + output wire [1:0] o_mem_bytecnt, + input wire i_mem_misalign, + //Control + input wire i_bne_or_bge, + input wire i_cond_branch, + input wire i_dbus_en, + input wire i_two_stage_op, + input wire i_branch_op, + input wire i_shift_op, + input wire i_sh_right, + input wire i_slt_or_branch, + input wire i_e_op, + input wire i_rd_op, + //MDU + input wire i_mdu_op, + output wire o_mdu_valid, + //Extension + input wire i_mdu_ready, + //External + output wire o_dbus_cyc, + input wire i_dbus_ack, + output wire o_ibus_cyc, + input wire i_ibus_ack, + //RF Interface + output wire o_rf_rreq, + output wire o_rf_wreq, + input wire i_rf_ready, + output wire o_rf_rd_en); + + reg stage_two_req; + reg init_done; + wire misalign_trap_sync; + + reg [4:2] o_cnt; + reg [3:0] o_cnt_r; + + reg ibus_cyc; + //Update PC in RUN or TRAP states + assign o_ctrl_pc_en = o_cnt_en & !o_init; + + assign o_cnt_en = |o_cnt_r; + + assign o_mem_bytecnt = o_cnt[4:3]; + + assign o_cnt0to3 = (o_cnt[4:2] == 3'd0); + assign o_cnt12to31 = (o_cnt[4] | (o_cnt[3:2] == 2'b11)); + assign o_cnt0 = (o_cnt[4:2] == 3'd0) & o_cnt_r[0]; + assign o_cnt1 = (o_cnt[4:2] == 3'd0) & o_cnt_r[1]; + assign o_cnt2 = (o_cnt[4:2] == 3'd0) & o_cnt_r[2]; + assign o_cnt3 = (o_cnt[4:2] == 3'd0) & o_cnt_r[3]; + assign o_cnt7 = (o_cnt[4:2] == 3'd1) & o_cnt_r[3]; + + //Take branch for jump or branch instructions (opcode == 1x0xx) if + //a) It's an unconditional branch (opcode[0] == 1) + //b) It's a conditional branch (opcode[0] == 0) of type beq,blt,bltu (funct3[0] == 0) and ALU compare is true + //c) It's a conditional branch (opcode[0] == 0) of type bne,bge,bgeu (funct3[0] == 1) and ALU compare is false + //Only valid during the last cycle of INIT, when the branch condition has + //been calculated. + wire take_branch = i_branch_op & (!i_cond_branch | (i_alu_cmp^i_bne_or_bge)); + + //valid signal for mdu + assign o_mdu_valid = MDU & !o_cnt_en & init_done & i_mdu_op; + + //Prepare RF for writes when everything is ready to enter stage two + // and the first stage didn't cause a misalign exception + assign o_rf_wreq = !misalign_trap_sync & !o_cnt_en & init_done & + ((i_shift_op & (i_sh_done | !i_sh_right)) | + i_dbus_ack | (MDU & i_mdu_ready) | + i_slt_or_branch); + + assign o_dbus_cyc = !o_cnt_en & init_done & i_dbus_en & !i_mem_misalign; + + //Prepare RF for reads when a new instruction is fetched + // or when stage one caused an exception (rreq implies a write request too) + assign o_rf_rreq = i_ibus_ack | (stage_two_req & misalign_trap_sync); + + assign o_rf_rd_en = i_rd_op & !o_init; + + /* + bufreg is used during mem. branch and shift operations + + mem : bufreg is used for dbus address. Shift in data during phase 1. + Shift out during phase 2 if there was an misalignment exception. + + branch : Shift in during phase 1. Shift out during phase 2 + + shift : Shift in during phase 1. Continue shifting between phases (except + for the first cycle after init). Shift out during phase 2 + */ + assign o_bufreg_en = (o_cnt_en & (o_init | ((o_ctrl_trap | i_branch_op) & i_two_stage_op))) | (i_shift_op & !stage_two_req & (i_sh_right | i_sh_done_r) & init_done); + + assign o_ibus_cyc = ibus_cyc & !i_rst; + + assign o_init = i_two_stage_op & !i_new_irq & !init_done; + + always @(posedge i_clk) begin + //ibus_cyc changes on three conditions. + //1. i_rst is asserted. Together with the async gating above, o_ibus_cyc + // will be asserted as soon as the reset is released. This is how the + // first instruction is fetced + //2. o_cnt_done and o_ctrl_pc_en are asserted. This means that SERV just + // finished updating the PC, is done with the current instruction and + // o_ibus_cyc gets asserted to fetch a new instruction + //3. When i_ibus_ack, a new instruction is fetched and o_ibus_cyc gets + // deasserted to finish the transaction + if (i_ibus_ack | o_cnt_done | i_rst) + ibus_cyc <= o_ctrl_pc_en | i_rst; + + if (o_cnt_done) begin + init_done <= o_init & !init_done; + o_ctrl_jump <= o_init & take_branch; + end + o_cnt_done <= (o_cnt[4:2] == 3'b111) & o_cnt_r[2]; + + //Need a strobe for the first cycle in the IDLE state after INIT + stage_two_req <= o_cnt_done & o_init; + + /* + Because SERV is 32-bit bit-serial we need a counter than can count 0-31 + to keep track of which bit we are currently processing. o_cnt and o_cnt_r + are used together to create such a counter. + The top three bits (o_cnt) are implemented as a normal counter, but + instead of the two LSB, o_cnt_r is a 4-bit shift register which loops 0-3 + When o_cnt_r[3] is 1, o_cnt will be increased. + + The counting starts when the core is idle and the i_rf_ready signal + comes in from the RF module by shifting in the i_rf_ready bit as LSB of + the shift register. Counting is stopped by using o_cnt_done to block the + bit that was supposed to be shifted into bit 0 of o_cnt_r. + + There are two benefit of doing the counter this way + 1. We only need to check four bits instead of five when we want to check + if the counter is at a certain value. For 4-LUT architectures this means + we only need one LUT instead of two for each comparison. + 2. We don't need a separate enable signal to turn on and off the counter + between stages, which saves an extra FF and a unique control signal. We + just need to check if o_cnt_r is not zero to see if the counter is + currently running + */ + o_cnt <= o_cnt + {2'd0,o_cnt_r[3]}; + o_cnt_r <= {o_cnt_r[2:0],(o_cnt_r[3] & !o_cnt_done) | (i_rf_ready & !o_cnt_en)}; + if (i_rst) begin + if (RESET_STRATEGY != "NONE") begin + o_cnt <= 3'd0; + init_done <= 1'b0; + o_ctrl_jump <= 1'b0; + o_cnt_done <= 1'b0; + o_cnt_r <= 4'b0000; + stage_two_req <= 1'b0; + end + end + end + + assign o_ctrl_trap = WITH_CSR & (i_e_op | i_new_irq | misalign_trap_sync); + + generate + if (WITH_CSR) begin + reg misalign_trap_sync_r; + + //trap_pending is only guaranteed to have correct value during the + // last cycle of the init stage + wire trap_pending = WITH_CSR & ((take_branch & i_ctrl_misalign & !ALIGN) | + (i_dbus_en & i_mem_misalign)); + + always @(posedge i_clk) begin + if (o_cnt_done) + misalign_trap_sync_r <= trap_pending & o_init; + if (i_rst) + if (RESET_STRATEGY != "NONE") + misalign_trap_sync_r <= 1'b0; + end + assign misalign_trap_sync = misalign_trap_sync_r; + end else + assign misalign_trap_sync = 1'b0; + endgenerate +endmodule +`default_nettype none + +module serv_top + #(parameter WITH_CSR = 1, + parameter PRE_REGISTER = 1, + parameter RESET_STRATEGY = "MINI", + parameter RESET_PC = 32'd0, + parameter [0:0] MDU = 1'b0, + parameter [0:0] COMPRESSED=0, + parameter [0:0] ALIGN = COMPRESSED) + ( + input wire clk, + input wire i_rst, + input wire i_timer_irq, +`ifdef RISCV_FORMAL + output reg rvfi_valid = 1'b0, + output reg [63:0] rvfi_order = 64'd0, + output reg [31:0] rvfi_insn = 32'd0, + output reg rvfi_trap = 1'b0, + output reg rvfi_halt = 1'b0, + output reg rvfi_intr = 1'b0, + output reg [1:0] rvfi_mode = 2'b11, + output reg [1:0] rvfi_ixl = 2'b01, + output reg [4:0] rvfi_rs1_addr, + output reg [4:0] rvfi_rs2_addr, + output reg [31:0] rvfi_rs1_rdata, + output reg [31:0] rvfi_rs2_rdata, + output reg [4:0] rvfi_rd_addr, + output reg [31:0] rvfi_rd_wdata, + output reg [31:0] rvfi_pc_rdata, + output reg [31:0] rvfi_pc_wdata, + output reg [31:0] rvfi_mem_addr, + output reg [3:0] rvfi_mem_rmask, + output reg [3:0] rvfi_mem_wmask, + output reg [31:0] rvfi_mem_rdata, + output reg [31:0] rvfi_mem_wdata, +`endif + //RF Interface + output wire o_rf_rreq, + output wire o_rf_wreq, + input wire i_rf_ready, + output wire [4+WITH_CSR:0] o_wreg0, + output wire [4+WITH_CSR:0] o_wreg1, + output wire o_wen0, + output wire o_wen1, + output wire o_wdata0, + output wire o_wdata1, + output wire [4+WITH_CSR:0] o_rreg0, + output wire [4+WITH_CSR:0] o_rreg1, + input wire i_rdata0, + input wire i_rdata1, + + output wire [31:0] o_ibus_adr, + output wire o_ibus_cyc, + input wire [31:0] i_ibus_rdt, + input wire i_ibus_ack, + output wire [31:0] o_dbus_adr, + output wire [31:0] o_dbus_dat, + output wire [3:0] o_dbus_sel, + output wire o_dbus_we , + output wire o_dbus_cyc, + input wire [31:0] i_dbus_rdt, + input wire i_dbus_ack, + //Extension + output wire [ 2:0] o_ext_funct3, + input wire i_ext_ready, + input wire [31:0] i_ext_rd, + output wire [31:0] o_ext_rs1, + output wire [31:0] o_ext_rs2, + //MDU + output wire o_mdu_valid); + + wire [4:0] rd_addr; + wire [4:0] rs1_addr; + wire [4:0] rs2_addr; + + wire [3:0] immdec_ctrl; + wire [3:0] immdec_en; + + wire sh_right; + wire bne_or_bge; + wire cond_branch; + wire two_stage_op; + wire e_op; + wire ebreak; + wire branch_op; + wire shift_op; + wire slt_or_branch; + wire rd_op; + wire mdu_op; + + wire rd_alu_en; + wire rd_csr_en; + wire rd_mem_en; + wire ctrl_rd; + wire alu_rd; + wire mem_rd; + wire csr_rd; + wire mtval_pc; + + wire ctrl_pc_en; + wire jump; + wire jal_or_jalr; + wire utype; + wire mret; + wire imm; + wire trap; + wire pc_rel; + wire iscomp; + + wire init; + wire cnt_en; + wire cnt0to3; + wire cnt12to31; + wire cnt0; + wire cnt1; + wire cnt2; + wire cnt3; + wire cnt7; + + wire cnt_done; + + wire bufreg_en; + wire bufreg_sh_signed; + wire bufreg_rs1_en; + wire bufreg_imm_en; + wire bufreg_clr_lsb; + wire bufreg_q; + wire bufreg2_q; + wire [31:0] dbus_rdt; + wire dbus_ack; + + wire alu_sub; + wire [1:0] alu_bool_op; + wire alu_cmp_eq; + wire alu_cmp_sig; + wire alu_cmp; + wire [2:0] alu_rd_sel; + + wire rs1; + wire rs2; + wire rd_en; + + wire op_b; + wire op_b_sel; + + wire mem_signed; + wire mem_word; + wire mem_half; + wire [1:0] mem_bytecnt; + wire sh_done; + wire sh_done_r; + wire byte_valid; + + wire mem_misalign; + + wire bad_pc; + + wire csr_mstatus_en; + wire csr_mie_en; + wire csr_mcause_en; + wire [1:0] csr_source; + wire csr_imm; + wire csr_d_sel; + wire csr_en; + wire [1:0] csr_addr; + wire csr_pc; + wire csr_imm_en; + wire csr_in; + wire rf_csr_out; + wire dbus_en; + + wire new_irq; + + wire [1:0] lsb; + + wire [31:0] i_wb_rdt; + + wire [31:0] wb_ibus_adr; + wire wb_ibus_cyc; + wire [31:0] wb_ibus_rdt; + wire wb_ibus_ack; + + generate + if (ALIGN) begin + serv_aligner align + ( + .clk(clk), + .rst(i_rst), + // serv_rf_top + .i_ibus_adr(wb_ibus_adr), + .i_ibus_cyc(wb_ibus_cyc), + .o_ibus_rdt(wb_ibus_rdt), + .o_ibus_ack(wb_ibus_ack), + // servant_arbiter + .o_wb_ibus_adr(o_ibus_adr), + .o_wb_ibus_cyc(o_ibus_cyc), + .i_wb_ibus_rdt(i_ibus_rdt), + .i_wb_ibus_ack(i_ibus_ack)); + end else begin + assign o_ibus_adr = wb_ibus_adr; + assign o_ibus_cyc = wb_ibus_cyc; + assign wb_ibus_rdt = i_ibus_rdt; + assign wb_ibus_ack = i_ibus_ack; + end + endgenerate + + generate + if (COMPRESSED) begin + serv_compdec compdec + ( + .i_clk(clk), + .i_instr(wb_ibus_rdt), + .i_ack(wb_ibus_ack), + .o_instr(i_wb_rdt), + .o_iscomp(iscomp)); + end else begin + assign i_wb_rdt = wb_ibus_rdt; + assign iscomp = 1'b0; + end + endgenerate + + serv_state + #(.RESET_STRATEGY (RESET_STRATEGY), + .WITH_CSR (WITH_CSR[0:0]), + .MDU(MDU), + .ALIGN(ALIGN)) + state + ( + .i_clk (clk), + .i_rst (i_rst), + //State + .i_new_irq (new_irq), + .i_alu_cmp (alu_cmp), + .o_init (init), + .o_cnt_en (cnt_en), + .o_cnt0to3 (cnt0to3), + .o_cnt12to31 (cnt12to31), + .o_cnt0 (cnt0), + .o_cnt1 (cnt1), + .o_cnt2 (cnt2), + .o_cnt3 (cnt3), + .o_cnt7 (cnt7), + .o_cnt_done (cnt_done), + .o_bufreg_en (bufreg_en), + .o_ctrl_pc_en (ctrl_pc_en), + .o_ctrl_jump (jump), + .o_ctrl_trap (trap), + .i_ctrl_misalign(lsb[1]), + .i_sh_done (sh_done), + .i_sh_done_r (sh_done_r), + .o_mem_bytecnt (mem_bytecnt), + .i_mem_misalign (mem_misalign), + //Control + .i_bne_or_bge (bne_or_bge), + .i_cond_branch (cond_branch), + .i_dbus_en (dbus_en), + .i_two_stage_op (two_stage_op), + .i_branch_op (branch_op), + .i_shift_op (shift_op), + .i_sh_right (sh_right), + .i_slt_or_branch (slt_or_branch), + .i_e_op (e_op), + .i_rd_op (rd_op), + //MDU + .i_mdu_op (mdu_op), + .o_mdu_valid (o_mdu_valid), + //Extension + .i_mdu_ready (i_ext_ready), + //External + .o_dbus_cyc (o_dbus_cyc), + .i_dbus_ack (i_dbus_ack), + .o_ibus_cyc (wb_ibus_cyc), + .i_ibus_ack (wb_ibus_ack), + //RF Interface + .o_rf_rreq (o_rf_rreq), + .o_rf_wreq (o_rf_wreq), + .i_rf_ready (i_rf_ready), + .o_rf_rd_en (rd_en)); + + serv_decode + #(.PRE_REGISTER (PRE_REGISTER), + .MDU(MDU)) + decode + ( + .clk (clk), + //Input + .i_wb_rdt (i_wb_rdt[31:2]), + .i_wb_en (wb_ibus_ack), + //To state + .o_bne_or_bge (bne_or_bge), + .o_cond_branch (cond_branch), + .o_dbus_en (dbus_en), + .o_e_op (e_op), + .o_ebreak (ebreak), + .o_branch_op (branch_op), + .o_shift_op (shift_op), + .o_slt_or_branch (slt_or_branch), + .o_rd_op (rd_op), + .o_sh_right (sh_right), + .o_mdu_op (mdu_op), + .o_two_stage_op (two_stage_op), + //Extension + .o_ext_funct3 (o_ext_funct3), + + //To bufreg + .o_bufreg_rs1_en (bufreg_rs1_en), + .o_bufreg_imm_en (bufreg_imm_en), + .o_bufreg_clr_lsb (bufreg_clr_lsb), + .o_bufreg_sh_signed (bufreg_sh_signed), + //To bufreg2 + .o_op_b_source (op_b_sel), + //To ctrl + .o_ctrl_jal_or_jalr (jal_or_jalr), + .o_ctrl_utype (utype), + .o_ctrl_pc_rel (pc_rel), + .o_ctrl_mret (mret), + //To alu + .o_alu_sub (alu_sub), + .o_alu_bool_op (alu_bool_op), + .o_alu_cmp_eq (alu_cmp_eq), + .o_alu_cmp_sig (alu_cmp_sig), + .o_alu_rd_sel (alu_rd_sel), + //To mem IF + .o_mem_cmd (o_dbus_we), + .o_mem_signed (mem_signed), + .o_mem_word (mem_word), + .o_mem_half (mem_half), + //To CSR + .o_csr_en (csr_en), + .o_csr_addr (csr_addr), + .o_csr_mstatus_en (csr_mstatus_en), + .o_csr_mie_en (csr_mie_en), + .o_csr_mcause_en (csr_mcause_en), + .o_csr_source (csr_source), + .o_csr_d_sel (csr_d_sel), + .o_csr_imm_en (csr_imm_en), + .o_mtval_pc (mtval_pc ), + //To top + .o_immdec_ctrl (immdec_ctrl), + .o_immdec_en (immdec_en), + //To RF IF + .o_rd_mem_en (rd_mem_en), + .o_rd_csr_en (rd_csr_en), + .o_rd_alu_en (rd_alu_en)); + + serv_immdec immdec + ( + .i_clk (clk), + //State + .i_cnt_en (cnt_en), + .i_cnt_done (cnt_done), + //Control + .i_immdec_en (immdec_en), + .i_csr_imm_en (csr_imm_en), + .i_ctrl (immdec_ctrl), + .o_rd_addr (rd_addr), + .o_rs1_addr (rs1_addr), + .o_rs2_addr (rs2_addr), + //Data + .o_csr_imm (csr_imm), + .o_imm (imm), + //External + .i_wb_en (wb_ibus_ack), + .i_wb_rdt (i_wb_rdt[31:7])); + + serv_bufreg + #(.MDU(MDU)) + bufreg + ( + .i_clk (clk), + //State + .i_cnt0 (cnt0), + .i_cnt1 (cnt1), + .i_en (bufreg_en), + .i_init (init), + .i_mdu_op (mdu_op), + .o_lsb (lsb), + //Control + .i_sh_signed (bufreg_sh_signed), + .i_rs1_en (bufreg_rs1_en), + .i_imm_en (bufreg_imm_en), + .i_clr_lsb (bufreg_clr_lsb), + //Data + .i_rs1 (rs1), + .i_imm (imm), + .o_q (bufreg_q), + //External + .o_dbus_adr (o_dbus_adr), + .o_ext_rs1 (o_ext_rs1)); + + serv_bufreg2 bufreg2 + ( + .i_clk (clk), + //State + .i_en (cnt_en), + .i_init (init), + .i_cnt_done (cnt_done), + .i_lsb (lsb), + .i_byte_valid (byte_valid), + .o_sh_done (sh_done), + .o_sh_done_r (sh_done_r), + //Control + .i_op_b_sel (op_b_sel), + .i_shift_op (shift_op), + //Data + .i_rs2 (rs2), + .i_imm (imm), + .o_op_b (op_b), + .o_q (bufreg2_q), + //External + .o_dat (o_dbus_dat), + .i_load (dbus_ack), + .i_dat (dbus_rdt)); + + serv_ctrl + #(.RESET_PC (RESET_PC), + .RESET_STRATEGY (RESET_STRATEGY), + .WITH_CSR (WITH_CSR)) + ctrl + ( + .clk (clk), + .i_rst (i_rst), + //State + .i_pc_en (ctrl_pc_en), + .i_cnt12to31 (cnt12to31), + .i_cnt0 (cnt0), + .i_cnt1 (cnt1), + .i_cnt2 (cnt2), + //Control + .i_jump (jump), + .i_jal_or_jalr (jal_or_jalr), + .i_utype (utype), + .i_pc_rel (pc_rel), + .i_trap (trap | mret), + .i_iscomp (iscomp), + //Data + .i_imm (imm), + .i_buf (bufreg_q), + .i_csr_pc (csr_pc), + .o_rd (ctrl_rd), + .o_bad_pc (bad_pc), + //External + .o_ibus_adr (wb_ibus_adr)); + + serv_alu alu + ( + .clk (clk), + //State + .i_en (cnt_en), + .i_cnt0 (cnt0), + .o_cmp (alu_cmp), + //Control + .i_sub (alu_sub), + .i_bool_op (alu_bool_op), + .i_cmp_eq (alu_cmp_eq), + .i_cmp_sig (alu_cmp_sig), + .i_rd_sel (alu_rd_sel), + //Data + .i_rs1 (rs1), + .i_op_b (op_b), + .i_buf (bufreg_q), + .o_rd (alu_rd)); + + serv_rf_if + #(.WITH_CSR (WITH_CSR)) + rf_if + (//RF interface + .i_cnt_en (cnt_en), + .o_wreg0 (o_wreg0), + .o_wreg1 (o_wreg1), + .o_wen0 (o_wen0), + .o_wen1 (o_wen1), + .o_wdata0 (o_wdata0), + .o_wdata1 (o_wdata1), + .o_rreg0 (o_rreg0), + .o_rreg1 (o_rreg1), + .i_rdata0 (i_rdata0), + .i_rdata1 (i_rdata1), + + //Trap interface + .i_trap (trap), + .i_mret (mret), + .i_mepc (wb_ibus_adr[0]), + .i_mtval_pc (mtval_pc), + .i_bufreg_q (bufreg_q), + .i_bad_pc (bad_pc), + .o_csr_pc (csr_pc), + //CSR write port + .i_csr_en (csr_en), + .i_csr_addr (csr_addr), + .i_csr (csr_in), + //RD write port + .i_rd_wen (rd_en), + .i_rd_waddr (rd_addr), + .i_ctrl_rd (ctrl_rd), + .i_alu_rd (alu_rd), + .i_rd_alu_en (rd_alu_en), + .i_csr_rd (csr_rd), + .i_rd_csr_en (rd_csr_en), + .i_mem_rd (mem_rd), + .i_rd_mem_en (rd_mem_en), + + //RS1 read port + .i_rs1_raddr (rs1_addr), + .o_rs1 (rs1), + //RS2 read port + .i_rs2_raddr (rs2_addr), + .o_rs2 (rs2), + + //CSR read port + .o_csr (rf_csr_out)); + + serv_mem_if + #(.WITH_CSR (WITH_CSR[0:0])) + mem_if + ( + .i_clk (clk), + //State + .i_bytecnt (mem_bytecnt), + .i_lsb (lsb), + .o_byte_valid (byte_valid), + .o_misalign (mem_misalign), + //Control + .i_mdu_op (mdu_op), + .i_signed (mem_signed), + .i_word (mem_word), + .i_half (mem_half), + //Data + .i_bufreg2_q (bufreg2_q), + .o_rd (mem_rd), + //External interface + .o_wb_sel (o_dbus_sel)); + + generate + if (|WITH_CSR) begin + serv_csr + #(.RESET_STRATEGY (RESET_STRATEGY)) + csr + ( + .i_clk (clk), + .i_rst (i_rst), + //State + .i_init (init), + .i_en (cnt_en), + .i_cnt0to3 (cnt0to3), + .i_cnt3 (cnt3), + .i_cnt7 (cnt7), + .i_cnt_done (cnt_done), + .i_mem_op (!mtval_pc), + .i_mtip (i_timer_irq), + .i_trap (trap), + .o_new_irq (new_irq), + //Control + .i_e_op (e_op), + .i_ebreak (ebreak), + .i_mem_cmd (o_dbus_we), + .i_mstatus_en (csr_mstatus_en), + .i_mie_en (csr_mie_en ), + .i_mcause_en (csr_mcause_en ), + .i_csr_source (csr_source), + .i_mret (mret), + .i_csr_d_sel (csr_d_sel), + //Data + .i_rf_csr_out (rf_csr_out), + .o_csr_in (csr_in), + .i_csr_imm (csr_imm), + .i_rs1 (rs1), + .o_q (csr_rd)); + end else begin + assign csr_in = 1'b0; + assign csr_rd = 1'b0; + assign new_irq = 1'b0; + end + endgenerate + + +`ifdef RISCV_FORMAL + reg [31:0] pc = RESET_PC; + + wire rs_en = two_stage_op ? init : ctrl_pc_en; + + always @(posedge clk) begin + /* End of instruction */ + rvfi_valid <= cnt_done & ctrl_pc_en & !i_rst; + rvfi_order <= rvfi_order + {63'd0,rvfi_valid}; + + /* Get instruction word when it's fetched from ibus */ + if (wb_ibus_cyc & wb_ibus_ack) + rvfi_insn <= i_wb_rdt; + + /* Store data written to rd */ + if (o_wen0) + rvfi_rd_wdata <= {o_wdata0,rvfi_rd_wdata[31:1]}; + + if (cnt_done & ctrl_pc_en) begin + rvfi_pc_rdata <= pc; + if (!(rd_en & (|rd_addr))) begin + rvfi_rd_addr <= 5'd0; + rvfi_rd_wdata <= 32'd0; + end + end + rvfi_trap <= trap; + if (rvfi_valid) begin + rvfi_trap <= 1'b0; + pc <= rvfi_pc_wdata; + end + + /* Not used */ + rvfi_halt <= 1'b0; + rvfi_intr <= 1'b0; + rvfi_mode <= 2'd3; + rvfi_ixl = 2'd1; + + /* RS1 not valid during J, U instructions (immdec_en[1]) */ + /* RS2 not valid during I, J, U instructions (immdec_en[2]) */ + if (i_rf_ready) begin + rvfi_rs1_addr <= !immdec_en[1] ? rs1_addr : 5'd0; + rvfi_rs2_addr <= !immdec_en[2] /*rs2_valid*/ ? rs2_addr : 5'd0; + rvfi_rd_addr <= rd_addr; + end + if (rs_en) begin + rvfi_rs1_rdata <= {!immdec_en[1] & rs1,rvfi_rs1_rdata[31:1]}; + rvfi_rs2_rdata <= {!immdec_en[2] & rs2,rvfi_rs2_rdata[31:1]}; + end + + if (i_dbus_ack) begin + rvfi_mem_addr <= o_dbus_adr; + rvfi_mem_rmask <= o_dbus_we ? 4'b0000 : o_dbus_sel; + rvfi_mem_wmask <= o_dbus_we ? o_dbus_sel : 4'b0000; + rvfi_mem_rdata <= i_dbus_rdt; + rvfi_mem_wdata <= o_dbus_dat; + end + if (wb_ibus_ack) begin + rvfi_mem_rmask <= 4'b0000; + rvfi_mem_wmask <= 4'b0000; + end + end + /* verilator lint_off COMBDLY */ + always @(wb_ibus_adr) + rvfi_pc_wdata <= wb_ibus_adr; + /* verilator lint_on COMBDLY */ + + +`endif + +generate + if (MDU) begin + assign dbus_rdt = i_ext_ready ? i_ext_rd:i_dbus_rdt; + assign dbus_ack = i_dbus_ack | i_ext_ready; + end else begin + assign dbus_rdt = i_dbus_rdt; + assign dbus_ack = i_dbus_ack; + end + assign o_ext_rs2 = o_dbus_dat; +endgenerate + +endmodule +`default_nettype wire +`default_nettype none + +`ifdef SIM + `include `CONFIG_PATH +`else + `include "./config.txt" +`endif + +module accelerator_if #( + parameter WEIGHT_DEPTH_12 = 8192, + parameter WEIGHT_DEPTH_34 = 8192, + parameter CHANNELS = 16, + parameter MAX_NEURONS = 128, + parameter MAX_SYNAPSES = 128 +) +( + input wire i_wb_clk, + input wire i_wb_rst, + + //from servant_mux, when i_wb_adr[31:30] == 2'b01 + input wire [31:0] i_wb_adr, + input wire [31:0] i_wb_dat, + input wire i_wb_we, + input wire i_wb_cyc, + output reg [31:0] o_wb_rdt, + output o_wb_ack, + + // snn + input wire i_snn_valid, + output output_buffer_ren, + output [7:0] output_buffer_addr, + input [31:0] output_buffer_out, + output wire [31:0] o_snn_adr_w1, + output wire [31:0] o_snn_adr_w2, + output wire [31:0] o_snn_adr_w3, + output wire [31:0] o_snn_adr_w4, + output wire [ 4:0] o_snn_we, + output wire [15:0] o_snn_dat, + output reg [clogb2(MAX_SYNAPSES-1)-1:0] snn_input_channels, + output reg [clogb2(MAX_NEURONS-1)-1:0] neuron_1, neuron_2, neuron_3, neuron_4, + /*neuron_5, neuron_6, neuron_7, neuron_8,*/ + output reg [2:0] layers, + + // spi + input wire [ 7:0] i_spi_dat, + output wire [23:0] o_spi_adr, + output wire [31:0] o_spi_siz, + + // ctrl + input wire i_ctrl_clr, + input wire i_ctrl_load1, + input wire i_ctrl_load2, + input wire i_ctrl_set0, + input wire i_ctrl_snn_we, + output wire o_ctrl_start, + + // uart + input wire i_uart_ready, + output reg [ 7:0] o_uart_data, + output reg o_uart_send, + output reg o_uart_wren, + output reg o_uart_hp, + + //spike mem 1 & 2 + input wire [7:0] i_spike_mem_dat, + output wire [7:0] o_spike_mem_adr, + output wire [1:0] o_spike_mem_rd_en, + output wire [1:0] o_spike_mem_wr_en, + output wire [3:0] o_spike_mem_dat, + + // sample mem + input wire [15:0] i_sample_mem_dat, + output wire [7:0] o_sample_mem_adr, + output wire o_sample_mem_rd_en, + output wire o_sample_mem_wr_en, + output wire [15:0] o_sample_mem_dat, + + // encoding bypass + output reg o_encoding_bypass, + + // gate clocks + output reg gate_spi, gate_snn, gate_enc, gate_serv, + output wire gate_general, + input wire timer_irq, + + output enable_next_debug + ); + + assign enable_next_debug = enable_next ; + + reg [ 7:0] data1, data2; + reg [23:0] spi_address; + reg [31:0] snn_address; + reg [31:0] spi_read_size; + reg [ 4:0] snn_write_enable; + reg spi_start; + reg enable_next; + reg uart_send_next; + + wire [31:0] snn_adr; + + reg gate_serv_armed; + reg gate_general_int; +/* + initial gate_spi = 0; + initial gate_snn = 0; + initial gate_enc = 0; + initial gate_serv = 0; + + initial gate_serv_armed = 0; + initial gate_general_int = 0; + initial snn_valid_rst = 0; + initial o_uart_hp = 0; + initial o_uart_data = 0; +*/ + assign gate_general = ~(gate_serv & gate_general_int); + + // bram read requires an extra clock cycle (sample mem) or two (spike mem) + // => ack is delayed by 2 c.c if spike mems are accessed, and by 1 c.c. otherwise + reg o_wb_ack_int, o_wb_ack_d, o_wb_ack_dd; + reg [7:0] i_wb_adr_d; + always @(posedge i_wb_clk) begin + o_wb_ack_int <= 1'b0; + o_wb_ack_d <= o_wb_ack_int; + o_wb_ack_dd <= o_wb_ack_d; + i_wb_adr_d <= i_wb_adr[27:20]; + spi_start <= enable_next; + + + if (i_wb_cyc & !o_wb_ack & !o_wb_ack_d & !o_wb_ack_dd) + o_wb_ack_int <= 1'b1; + + if (i_wb_rst) begin + o_wb_ack_int <= 1'b0; + o_wb_ack_d <= 1'b0; + o_wb_ack_dd <= 1'b0; + i_wb_adr_d <= 0; + + + //aggiunti dopo + + spi_start <= 0; + + gate_spi <= 0; + gate_snn <= 0; + gate_enc <= 0; + //gate_serv <= 0; + //gate_serv_armed <= 0; //forse da reinserire da qualche altra parte + //gate_general_int <= 0; + snn_valid_rst <= 0; + o_uart_hp <= 0; + o_uart_data <= 0; + end + end + + wire rst_asinc_gate_serv; + assign rst_asinc_gate_serv = timer_irq || i_wb_rst; + + always @(posedge i_wb_clk, posedge rst_asinc_gate_serv) + if(rst_asinc_gate_serv) + gate_serv <= 1'b0; + else if(gate_serv_armed) + gate_serv <= 1'b1; + + assign o_wb_ack = (i_wb_adr_d == 8'h03 | i_wb_adr_d == 8'h04 | i_wb_adr_d == 8'h05 | i_wb_adr_d == 8'h01) ? o_wb_ack_d : o_wb_ack_int ; + + assign o_snn_adr_w1 = snn_adr; + assign o_snn_adr_w2 = snn_adr; + assign o_snn_adr_w3 = snn_adr; + assign o_snn_adr_w4 = snn_adr; + reg snn_valid, snn_valid_rst; + + + always @(posedge i_wb_clk) begin + if(i_wb_rst) + snn_valid <= 0; + else if(i_snn_valid) + snn_valid <= i_snn_valid; + else if(snn_valid_rst) + snn_valid <= 0; + end + + assign o_snn_dat = {data1, data2}; + assign o_spi_adr = spi_address; + assign o_spi_siz = {spi_read_size, 3'b000}; // convert from bytes to bits + assign o_ctrl_start = spi_start; + assign o_snn_we = snn_write_enable; + + + always @(posedge i_wb_clk) + if(i_wb_rst) + o_uart_wren <= 0; + else + o_uart_wren <= (i_wb_adr[27:16] == 12'h021) && (i_wb_cyc & i_wb_we & o_wb_ack); // && o_uart_hp + + `ifdef ACCESSIBILITY + `ifdef SIM initial $display("ACCESSIBILITY IS DEFINED"); `endif + + assign o_spike_mem_adr = i_wb_adr[8:2]; + assign o_spike_mem_rd_en[0] = (i_wb_adr[27:20] == 8'h03) && (i_wb_cyc); // spike mem 1 + assign o_spike_mem_rd_en[1] = (i_wb_adr[27:20] == 8'h04) && (i_wb_cyc); // spike mem 2 + assign o_spike_mem_wr_en[0] = (i_wb_adr[27:20] == 8'h03) && (i_wb_cyc && i_wb_we); // spike mem 1 + assign o_spike_mem_wr_en[1] = (i_wb_adr[27:20] == 8'h04) && (i_wb_cyc && i_wb_we); // spike mem 2 + assign o_spike_mem_dat = i_wb_dat[3:0]; + + assign o_sample_mem_adr = i_wb_adr[8:2]; + assign o_sample_mem_rd_en = (i_wb_adr[27:20] == 8'h05) && (i_wb_cyc); // sample mem + assign o_sample_mem_wr_en = (i_wb_adr[27:20] == 8'h05) && (i_wb_cyc && i_wb_we); + assign o_sample_mem_dat = i_wb_dat[15:0]; + + assign output_buffer_addr = i_wb_adr[9:2]; + assign output_buffer_ren = (i_wb_adr[27:16] == 12'h010) && (i_wb_cyc); // output buffer mem + `else + assign o_spike_mem_rd_en = 0; + assign o_spike_mem_wr_en = 0; + assign o_sample_mem_rd_en = 0; + assign o_sample_mem_wr_en = 0; + `endif + + always @(posedge i_wb_clk) begin + + gate_serv_armed = 0; // auto reset after 1 c.c. + case (i_wb_adr[27:20]) + //////// SPI /////// + 8'h00: begin + case (i_wb_adr[19:16]) + 4'h0: begin o_wb_rdt <= {8'h0, spi_address}; + if (i_wb_we & i_wb_cyc) begin + spi_address <= i_wb_dat; + end + end + 4'h1: begin // snn address + o_wb_rdt <= snn_address; + if (i_wb_we & i_wb_cyc) begin + snn_address <= i_wb_dat; + end + end + 4'h2: begin // spi read size + o_wb_rdt <= spi_read_size; + if (i_wb_we & i_wb_cyc) begin + spi_read_size <= i_wb_dat; + end + end + 4'h3: begin + o_wb_rdt <= {31'h0, spi_start}; // spi start + end + endcase + end + //////// OUTPUT BUFFER /////// + 8'h01: begin + case (i_wb_adr[19:16]) + + 4'h0: begin // v + o_wb_rdt <= output_buffer_out; + end + /* + 4'h1: begin // f1 + o_wb_rdt <= {16'h0, i_snn_f1}; + end + 4'h2: begin // f2 + o_wb_rdt <= {16'h0, i_snn_f2}; + end + 4'h3: begin // f3 + o_wb_rdt <= {16'h0, i_snn_f3}; + end + 4'h4: begin // f4 + o_wb_rdt <= {16'h0, i_snn_f4}; + end + */ + 4'hf: begin // valid inference + o_wb_rdt <= {16'h0, snn_valid}; + end + 4'he: begin // valid inference reset + o_wb_rdt <= {31'b0,snn_valid_rst}; + if (i_wb_cyc & o_wb_ack) begin + snn_valid_rst <= i_wb_dat[0]; + end + end + endcase + end + /////////////////////////////////////////////////////////////////////// + `ifndef UART_HP //////// UART /////// + /////////////////////////////////////////////////////////////////////// + 8'h02: begin + case (i_wb_adr[19:16]) + 4'h0: begin // o_uart_data + o_wb_rdt <= {24'h0, o_uart_data}; + if (i_wb_cyc & i_wb_we) begin + o_uart_data <= i_wb_dat; + end + end + 4'h1: begin + o_wb_rdt <= {31'h0, o_uart_send}; // i_uart_send + end + 4'h2: begin + o_wb_rdt <= {31'h0, i_uart_ready}; // i_uart_ready + end + 4'h3: begin // o_uart_hp high performance + o_wb_rdt <= {31'h0, o_uart_hp}; + if (i_wb_cyc & i_wb_we) begin + o_uart_hp <= i_wb_dat[0]; + end + end + endcase + end + + `endif + + /////////////////////////////////////////////////////////////////////// + /////////////////////////////////////////////////////////////////////// + + /////////////////////////////////////////////////////////////////////// + `ifdef ACCESSIBILITY + /////////////////////////////////////////////////////////////////////// + + 8'h03: begin // spike_mem_1 + o_wb_rdt <= {28'b0,i_spike_mem_dat[3:0]}; + end + 8'h04: begin + o_wb_rdt <= {28'b0,i_spike_mem_dat[7:4]}; // spike_mem_2 + end + 8'h05: begin + o_wb_rdt <= {16'b0,i_sample_mem_dat}; // sample_mem + end + + //////// ENCODING SETTINGS /////// + 8'h06: begin + case (i_wb_adr[19:16]) + 4'h0: begin + if (i_wb_cyc & i_wb_we) // encoding bypass + o_encoding_bypass <= i_wb_dat[0]; + end + endcase + end + + `endif + + /////////////////////////////////////////////////////////////////////// + /////////////////////////////////////////////////////////////////////// + + /////////////////////////////////////////////////////////////////////// + `ifdef CONFIGURABILITY + /////////////////////////////////////////////////////////////////////// + + //////// SNN SETTINGS /////// + 8'h07: begin + case (i_wb_adr[19:16]) + 4'h0: begin + if (i_wb_cyc & i_wb_we) // snn_input_channels + snn_input_channels <= i_wb_dat[clogb2(MAX_SYNAPSES-1)-1:0]; + end + 4'h1: begin + if (i_wb_cyc & i_wb_we) // #neuron L1 + neuron_1 <= i_wb_dat[clogb2(MAX_NEURONS-1)-1:0]; + end + 4'h2: begin + if (i_wb_cyc & i_wb_we) // #neuron L2 + neuron_2 <= i_wb_dat[clogb2(MAX_NEURONS-1)-1:0]; + end + 4'h3: begin + if (i_wb_cyc & i_wb_we) // #neuron L3 + neuron_3 <= i_wb_dat[clogb2(MAX_NEURONS-1)-1:0]; + end + 4'h4: begin + if (i_wb_cyc & i_wb_we) // #neuron L4 + neuron_4 <= i_wb_dat[clogb2(MAX_NEURONS-1)-1:0]; + end + + 4'h9: begin + if (i_wb_cyc & i_wb_we) // #layer + layers <= i_wb_dat[2:0]; + end + endcase + end + + `endif + + /////////////////////////////////////////////////////////////////////// + /////////////////////////////////////////////////////////////////////// + + /////////////////////////////////////////////////////////////////////// + `ifdef LOW_POWER + /////////////////////////////////////////////////////////////////////// + + //////// GATE CLOCK /////// + 8'h08: begin + o_wb_rdt <= {27'b0,gate_general_int,gate_serv_armed,gate_enc,gate_snn,gate_spi}; + if (i_wb_cyc & i_wb_we) begin + gate_spi <= i_wb_dat[0]; + gate_snn <= i_wb_dat[1]; + gate_enc <= i_wb_dat[2]; + gate_serv_armed = i_wb_dat[3]; + gate_general_int <= i_wb_dat[4]; + end + end + + `endif + + /////////////////////////////////////////////////////////////////////// + /////////////////////////////////////////////////////////////////////// + + default: begin + o_wb_rdt <= 32'h0; + end + + endcase + + if (i_ctrl_load1) begin // load data1 + data1 <= i_spi_dat; + end + + if (i_ctrl_load2) // load data2 + data2 <= i_spi_dat; + + + + o_uart_send <= uart_send_next; + + end + + always @(*) begin + if (i_ctrl_set0) begin // reset spi_start + enable_next = 0; + end + else if (i_wb_adr[27:16] == 12'h003 && i_wb_we && i_wb_cyc) begin + enable_next = i_wb_dat[0]; + end + else begin + enable_next = spi_start; + end + + if (i_wb_adr[27:16] == 12'h021 && i_wb_we && i_wb_cyc) begin + uart_send_next = i_wb_dat; + end + else begin + uart_send_next = 0; + end + end + + // combinatorial logic for write enables and addresses for snn + always @(*) begin + if (i_ctrl_snn_we) begin + case (snn_address) + 1: begin + snn_write_enable = 5'b00001; + end + 2: begin + snn_write_enable = 5'b00010; + end + 3: begin + snn_write_enable = 5'b00100; + end + 4: begin + snn_write_enable = 5'b01000; + end + 5: begin + snn_write_enable = 5'b10000; + end + default: begin + snn_write_enable = 5'b00000; + end + endcase + end + else begin + snn_write_enable = 5'b00000; + end + end + + snn_addr_counter #( + .DEPTH(max3(WEIGHT_DEPTH_12, WEIGHT_DEPTH_34, CHANNELS)) + ) + snn_addr_counter + ( + .clk (i_wb_clk), + .rst (i_wb_rst), + .clr (i_ctrl_clr), + .inc (i_ctrl_snn_we), + .addr (snn_adr) + ); + + // The following function calculates the address width based on specified RAM depth + function integer clogb2; + input integer depth; + for (clogb2=0; depth>0; clogb2=clogb2+1) + depth = depth >> 1; + endfunction + + function integer max3; + input integer a,b,c; + if (a>b) + if (a>c) + max3 = a; + else + max3 = c; + else if (b>c) + max3 = b; + else + max3 = c; + endfunction + +endmodule +`default_nettype none +module accelerator_top #( + parameter WEIGHT_DEPTH_12 = 8192, + parameter WEIGHT_DEPTH_34 = 8192, + parameter CHANNELS = 16, + parameter MAX_NEURONS = 128, + parameter MAX_SYNAPSES = 128, + parameter pClockFrequency = 24000000, + parameter DOUBLE_CLOCK = 0, + parameter UART_QUEUE = 16 +) +( + // cpu + input wire wb_clk, + input wire spi_clk, + input wire wb_rst, + input wire [31:0] i_cpu_adr, + input wire [31:0] i_cpu_dat, + input wire i_cpu_we, + input wire i_cpu_cyc, + output wire [31:0] o_cpu_rdt, + output wire o_cpu_ack, + + // flash + output wire o_flash_sck, + output wire o_flash_mosi, + output wire o_flash_ss, + input wire i_flash_miso, + + // snn + input wire i_snn_valid, + output output_buffer_ren, + output [7:0] output_buffer_addr, + input [31:0] output_buffer_out, + output wire [31:0] o_snn_adr_w1, + output wire [31:0] o_snn_adr_w2, + output wire [31:0] o_snn_adr_w3, + output wire [31:0] o_snn_adr_w4, + output wire [ 4:0] o_snn_we, + output wire [15:0] o_snn_dat, + output wire [clogb2(MAX_SYNAPSES-1)-1:0] snn_input_channels, + output wire [clogb2(MAX_NEURONS-1)-1:0] neuron_1, neuron_2, neuron_3, neuron_4, + output wire [2:0] layers, + + // uart + output wire o_txd, + + //spike mem 1 & 2 + input wire [7:0] i_spike_mem_dat, + output wire [7:0] o_spike_mem_adr, + output wire [1:0] o_spike_mem_rd_en, + output wire [1:0] o_spike_mem_wr_en, + output wire [3:0] o_spike_mem_dat, + + // sample mem + input wire [15:0] i_sample_mem_dat, + output wire [7:0] o_sample_mem_adr, + output wire o_sample_mem_rd_en, + output wire o_sample_mem_wr_en, + output wire [15:0] o_sample_mem_dat, + + output wire o_encoding_bypass, + + // gate clocks + output wire gate_spi, gate_snn, gate_enc, gate_serv, + input wire timer_irq, + output wire gate_general + ); + + wire [23:0] spi_if_adr; + wire [31:0] spi_if_size; + wire [ 7:0] spi_if_dat; + wire ctrl_if_start; + wire ctrl_if_clr; + wire ctrl_if_load1; + wire ctrl_if_load2; + wire ctrl_if_set0; + wire ctrl_if_snn_we; + wire ctrl_spi_valid; + wire ctrl_spi_end; + wire ctrl_spi_enable; + wire ctrl_spi_read_ack; + wire uart_if_ready; + wire [ 7:0] uart_if_data; + wire uart_if_send; + wire uart_wren; + wire o_uart_hp; + +`ifdef PS_ACC_TOP + + + //initial begin $deposit(ctrl_if_load1, 1'b1); end + //initial begin $deposit(ctrl_if_load2, 1'b1); end + + accelerator_if_ps aif_ps( + .i_wb_clk (wb_clk), + .i_wb_rst (wb_rst), + + .i_wb_adr (i_cpu_adr), + .i_wb_dat (i_cpu_dat), + .i_wb_we (i_cpu_we), + .i_wb_cyc (i_cpu_cyc), + + .o_wb_rdt (o_cpu_rdt), + .o_wb_ack (o_cpu_ack), + + .i_snn_valid (i_snn_valid), + .output_buffer_ren(output_buffer_ren), + .output_buffer_addr(output_buffer_addr), + .output_buffer_out(output_buffer_out), + .o_snn_adr_w1 (o_snn_adr_w1), + .o_snn_adr_w2 (o_snn_adr_w2), + .o_snn_adr_w3 (o_snn_adr_w3), + .o_snn_adr_w4 (o_snn_adr_w4), + .o_snn_we (o_snn_we), + .o_snn_dat (o_snn_dat), + .snn_input_channels(snn_input_channels), + .neuron_1(neuron_1), .neuron_2(neuron_2), .neuron_3(neuron_3), .neuron_4(neuron_4), + .layers(layers), + + .i_spi_dat (spi_if_dat), + .o_spi_adr (spi_if_adr), + .o_spi_siz (spi_if_size), + + .i_ctrl_clr (ctrl_if_clr), + .i_ctrl_load1 (ctrl_if_load1), + .i_ctrl_load2 (ctrl_if_load2), + .i_ctrl_set0 (ctrl_if_set0), + .i_ctrl_snn_we (ctrl_if_snn_we), + .o_ctrl_start (ctrl_if_start), + + .i_uart_ready (uart_if_ready), + .o_uart_data (uart_if_data), + .o_uart_send (uart_if_send), + .o_uart_wren (uart_wren), + .o_uart_hp (o_uart_hp), + + //spike mem 1 & 2 + .i_spike_mem_dat(i_spike_mem_dat), + .o_spike_mem_adr(o_spike_mem_adr), + .o_spike_mem_rd_en(o_spike_mem_rd_en), + .o_spike_mem_wr_en(o_spike_mem_wr_en), + .o_spike_mem_dat(o_spike_mem_dat), + // sample mem + .i_sample_mem_dat(i_sample_mem_dat), + .o_sample_mem_adr(o_sample_mem_adr), + .o_sample_mem_rd_en(o_sample_mem_rd_en), + .o_sample_mem_wr_en(o_sample_mem_wr_en), + .o_sample_mem_dat(o_sample_mem_dat), + + .o_encoding_bypass(o_encoding_bypass), + + .gate_spi(gate_spi), .gate_snn(gate_snn), .gate_enc(gate_enc), .gate_serv(gate_serv), + .timer_irq(timer_irq), .gate_general(gate_general) + ); + +`else + + accelerator_if #( + .WEIGHT_DEPTH_12(WEIGHT_DEPTH_12), + .WEIGHT_DEPTH_34(WEIGHT_DEPTH_34), + .CHANNELS (CHANNELS), + .MAX_NEURONS (MAX_NEURONS), + .MAX_SYNAPSES (MAX_SYNAPSES) + ) + aif( + .i_wb_clk (wb_clk), + .i_wb_rst (wb_rst), + + .i_wb_adr (i_cpu_adr), + .i_wb_dat (i_cpu_dat), + .i_wb_we (i_cpu_we), + .i_wb_cyc (i_cpu_cyc), + .o_wb_rdt (o_cpu_rdt), + .o_wb_ack (o_cpu_ack), + + .i_snn_valid (i_snn_valid), + .output_buffer_ren(output_buffer_ren), + .output_buffer_addr(output_buffer_addr), + .output_buffer_out(output_buffer_out), + .o_snn_adr_w1 (o_snn_adr_w1), + .o_snn_adr_w2 (o_snn_adr_w2), + .o_snn_adr_w3 (o_snn_adr_w3), + .o_snn_adr_w4 (o_snn_adr_w4), + .o_snn_we (o_snn_we), + .o_snn_dat (o_snn_dat), + .snn_input_channels(snn_input_channels), + .neuron_1(neuron_1), .neuron_2(neuron_2), .neuron_3(neuron_3), .neuron_4(neuron_4), + .layers(layers), + + .i_spi_dat (spi_if_dat), + .o_spi_adr (spi_if_adr), + .o_spi_siz (spi_if_size), + + .i_ctrl_clr (ctrl_if_clr), + .i_ctrl_load1 (ctrl_if_load1), + .i_ctrl_load2 (ctrl_if_load2), + .i_ctrl_set0 (ctrl_if_set0), + .i_ctrl_snn_we (ctrl_if_snn_we), + .o_ctrl_start (ctrl_if_start), + + .i_uart_ready (uart_if_ready), + .o_uart_data (uart_if_data), + .o_uart_send (uart_if_send), + .o_uart_wren (uart_wren), + .o_uart_hp (o_uart_hp), + + //spike mem 1 & 2 + .i_spike_mem_dat(i_spike_mem_dat), + .o_spike_mem_adr(o_spike_mem_adr), + .o_spike_mem_rd_en(o_spike_mem_rd_en), + .o_spike_mem_wr_en(o_spike_mem_wr_en), + .o_spike_mem_dat(o_spike_mem_dat), + // sample mem + .i_sample_mem_dat(i_sample_mem_dat), + .o_sample_mem_adr(o_sample_mem_adr), + .o_sample_mem_rd_en(o_sample_mem_rd_en), + .o_sample_mem_wr_en(o_sample_mem_wr_en), + .o_sample_mem_dat(o_sample_mem_dat), + + .o_encoding_bypass(o_encoding_bypass), + + .gate_spi(gate_spi), .gate_snn(gate_snn), .gate_enc(gate_enc), .gate_serv(gate_serv), + .timer_irq(timer_irq), .gate_general(gate_general) + ); + + +`endif + + +`ifdef PS_ACC_TOP + +//initial begin $deposit(ctrl_if_start, 1'b0); end + + + spi_acc_control_ps sac_ps( + .wb_clk(spi_clk), + .wb_rst(wb_rst), + .i_if_start (ctrl_if_start), + .i_spi_valid (ctrl_spi_valid), + .i_spi_end (ctrl_spi_end), + .o_spi_en (ctrl_spi_enable), + .o_spi_read_ack (ctrl_spi_read_ack), + .o_if_snn_we (ctrl_if_snn_we), + .o_if_clr (ctrl_if_clr), + .o_if_load1 (ctrl_if_load1), + .o_if_load2 (ctrl_if_load2), + .o_if_set0 (ctrl_if_set0) + ); + +`else + + + spi_acc_control #(.DOUBLE_CLOCK(DOUBLE_CLOCK)) sac( + .wb_clk(spi_clk), + .wb_rst(wb_rst), + .i_if_start (ctrl_if_start), + .o_if_clr (ctrl_if_clr), + .o_if_load1 (ctrl_if_load1), + .o_if_load2 (ctrl_if_load2), + .o_if_set0 (ctrl_if_set0), + .i_spi_valid (ctrl_spi_valid), + .i_spi_end (ctrl_spi_end), + .o_spi_en (ctrl_spi_enable), + .o_spi_read_ack (ctrl_spi_read_ack), + .o_if_snn_we (ctrl_if_snn_we) + ); + + +`endif + +`ifdef PS_ACC_TOP + + spi_master_ps spi_ps( + .clk (spi_clk), + .reset (wb_rst), + .SPI_SCK (o_flash_sck), + .SPI_SS (o_flash_ss), + .SPI_MOSI (o_flash_mosi), + .SPI_MISO (i_flash_miso), + .en (ctrl_spi_enable), + .addr (spi_if_adr), + .valid (ctrl_spi_valid), + .end_transaction (ctrl_spi_end), + .rd_ack (ctrl_spi_read_ack), + .rd_data (spi_if_dat), + .words_to_read (spi_if_size), + .read_req (1'b1), + .wr_data (8'b0) + ); + +`else + + spi_master spi( + .clk (spi_clk), + .reset (wb_rst), + .SPI_SCK (o_flash_sck), + .SPI_SS (o_flash_ss), + .SPI_MOSI (o_flash_mosi), + .SPI_MISO (i_flash_miso), + .en (ctrl_spi_enable), + .addr (spi_if_adr), + .valid (ctrl_spi_valid), + .end_transaction (ctrl_spi_end), + .rd_ack (ctrl_spi_read_ack), + .rd_data (spi_if_dat), + .words_to_read (spi_if_size), + .read_req (1'b1), + .wr_data (8'b0) + ); + + +`endif + +//////// UART /////// + + wire uart_tx_go, uart_tx_go_hp; + wire [7:0] uart_byte, uart_byte_hp; + wire [clogb2(UART_QUEUE-1)-1:0] sel; + wire hp_tx_start; + + assign hp_tx_start = uart_wren & o_uart_hp; + +`ifdef PS_ACC_TOP + + fsm_uart_tx_ps + fsm_uart_tx_ps + ( + .clk(wb_clk), + .rst(wb_rst), + .i_start(hp_tx_start), + .i_continue(uart_if_ready), + .o_sel(sel), + .o_valid(uart_tx_go_hp) + ); + +`else + + fsm_uart_tx #( .N(UART_QUEUE)) + fsm_uart_tx_i + ( + .clk(wb_clk), + .rst(wb_rst), + .i_start(hp_tx_start), + .i_continue(uart_if_ready), + .o_sel(sel), + .o_valid(uart_tx_go_hp) + ); +`endif + + assign uart_byte_hp = (sel == 0)? output_buffer_out[7:0] : + (sel == 1)? output_buffer_out[15:8]: + (sel == 2)? output_buffer_out[23:16] : + output_buffer_out[31:24]; + + assign uart_byte = o_uart_hp ? uart_byte_hp : uart_if_data; + assign uart_tx_go = o_uart_hp ? uart_tx_go_hp : uart_wren; + +`ifdef PS_ACC_TOP +wire uart_if_ready_debug, o_txd_debug; + + SerialTransmitter_ps + uart_transmitter_ps( + .iClock (wb_clk), + .iData (uart_byte), + .iSend (uart_tx_go), + .oReady (uart_if_ready), + .oTxd (o_txd), + .iReset (wb_rst) + ); + + +`else + + SerialTransmitter #(.pClockFrequency(pClockFrequency), .pBaudRate(4000000)) + uart_transmitter( + .iClock (wb_clk), + .iData (uart_byte), + .iSend (uart_tx_go), + .oReady (uart_if_ready), + .oTxd (o_txd), + .iReset (wb_rst) + ); + +`endif + + + + + + + // The following function calculates the address width based on specified RAM depth + function integer clogb2; + input integer depth; + for (clogb2=0; depth>0; clogb2=clogb2+1) + depth = depth >> 1; + endfunction + +endmodule + + + + + + + + + + + + + + + + + + + +module fsm_uart_tx #( parameter N = 16) ( + + input rst,clk, + input i_start, i_continue, + output [clogb2(N-1)-1:0] o_sel, + output o_valid +); + +reg [clogb2(N-1):0] cnt; + +always @(posedge clk) + if (rst) begin + cnt <= 0; + end + else if (cnt == N) begin + cnt <= 0; + end + else if (cnt != 0 && i_continue) begin + cnt <= cnt + 1'b1; + end + else if (cnt == 0 && i_start) begin + cnt <= 1; + end + +reg continue_r; +always @(posedge clk) + if (rst) + continue_r <= 0; + else if (cnt != 0) + continue_r <= i_continue; + +assign o_sel = cnt; +assign o_valid = (i_start && i_continue) || (i_continue && cnt != 0); + +////////////////////////////////////////////////// +// __ _ _ // +// / _|_ _ _ __ ___| |_(_) ___ _ __ ___ // +// | |_| | | | '_ \ / __| __| |/ _ \| '_ \/ __| // +// | _| |_| | | | | (__| |_| | (_) | | | \__ \ // +// |_| \__,_|_| |_|\___|\__|_|\___/|_| |_|___/ // +// // +////////////////////////////////////////////////// + +function integer clogb2; + input integer depth; + for (clogb2=0; depth>0; clogb2=clogb2+1) + depth = depth >> 1; +endfunction + +endmodule +/* This is a Glitch free clock Mux. The design is based on the description provided +at: https://vlsitutorials.com/glitch-free-clock-mux/ + +TBD: Need to contrain the locations of the various cells properly so they're close to each other to avoid glitches. +*/ + +module gfcm ( + input reset, // Async reset! + input clk1, + input clk2, + input sel, + output outclk +); + // Select double register + reg [1:0] sync1, sync2; + + wire i_and1, i_and2; + wire o_and1, o_and2; + + assign i_and1 = ~sel & ~sync2[1]; + assign i_and2 = sel & ~sync1[1]; + + always @ (posedge clk1 or posedge reset) + if (reset == 1'b1) + sync1 <= 0; + else + sync1 <= {sync1[0], i_and1}; + + always @ (posedge clk2 or posedge reset) + if (reset == 1'b1) + sync2 <= 0; + else + sync2 <= {sync2[0], i_and2}; + + assign o_and1 = clk1 & sync1[1]; + assign o_and2 = clk2 & sync2[1]; + + assign outclk = o_and1 | o_and2; +endmodule +`default_nettype none +// 011 gpio +// 010 accelerator + +module gpio_accelerator_mux + (input wire i_wb_clk, + input wire [31:0] i_wb_adr, + input wire [31:0] i_wb_dat, + input wire i_wb_we, + input wire i_wb_cyc, + output wire [31:0] o_wb_rdt, + + //output wire [31:0] o_wb_gpio_adr, + output wire o_wb_gpio_dat, + output wire o_wb_gpio_we, + output wire o_wb_gpio_cyc, + input wire i_wb_gpio_rdt, + + output wire [31:0] o_wb_acc_adr, + output wire [31:0] o_wb_acc_dat, + output wire o_wb_acc_we, + output wire o_wb_acc_cyc, + input wire [31:0] i_wb_acc_rdt); + + wire s = i_wb_adr[29]; + + assign o_wb_rdt = s ? {31'b0, i_wb_gpio_rdt} : i_wb_acc_rdt; + + //assign o_wb_gpio_adr = i_wb_adr; + assign o_wb_gpio_dat = i_wb_dat[0]; + assign o_wb_gpio_we = i_wb_we; + + assign o_wb_acc_adr = i_wb_adr; + assign o_wb_acc_dat = i_wb_dat; + assign o_wb_acc_we = i_wb_we; + + assign o_wb_gpio_cyc = i_wb_cyc & s; + assign o_wb_acc_cyc = i_wb_cyc & ~s; + +endmodule`default_nettype none +module servant( + input wire wb_clk, + input wire timer_clk, + input wire wb_rst, + output wire [3:0] led, + input wire [2:0] buttons, + output wire timer_irq, + + output wire [31:0] o_wb_acc_adr, + output wire [31:0] o_wb_acc_dat, + output wire o_wb_acc_we, + output wire o_wb_acc_cyc, + input wire [31:0] i_wb_acc_rdt, + input wire i_wb_acc_ack, + + input wire enb_debug +); + + parameter memfile = "zephyr_hello.hex"; + parameter memsize = 8192; + parameter reset_strategy = "MINI"; + parameter sim = 0; + parameter with_csr = 1; + parameter [0:0] compress = 0; + parameter [0:0] align = compress; + + wire [31:0] wb_ibus_adr; + wire wb_ibus_cyc; + wire [31:0] wb_ibus_rdt; + wire wb_ibus_ack; + + wire [31:0] wb_dbus_adr; + wire [31:0] wb_dbus_dat; + wire [3:0] wb_dbus_sel; + wire wb_dbus_we; + wire wb_dbus_cyc; + wire [31:0] wb_dbus_rdt; + wire wb_dbus_ack; + + wire [31:0] wb_dmem_adr; + wire [31:0] wb_dmem_dat; + wire [ 3:0] wb_dmem_sel; + wire wb_dmem_we; + wire wb_dmem_cyc; + wire [31:0] wb_dmem_rdt; + wire wb_dmem_ack; + + wire [31:0] wb_mem_adr; + wire [31:0] wb_mem_dat; + wire [ 3:0] wb_mem_sel; + wire wb_mem_we; + wire wb_mem_cyc; + wire [31:0] wb_mem_rdt; + wire wb_mem_ack; + + wire [31:0] wb_gamux_adr; + wire [31:0] wb_gamux_dat; + wire wb_gamux_we; + wire wb_gamux_cyc; + wire [31:0] wb_gamux_rdt; + + wire [31:0] wb_gpio_adr; + wire [31:0] wb_gpio_dat; + wire wb_gpio_we; + wire wb_gpio_cyc; + wire [31:0] wb_gpio_rdt; + + wire [31:0] wb_timer_adr; + wire [31:0] wb_timer_dat; + wire wb_timer_we; + wire wb_timer_cyc; + wire [31:0] wb_timer_rdt; + + wire [31:0] mdu_rs1; + wire [31:0] mdu_rs2; + wire [ 2:0] mdu_op; + wire mdu_valid; + wire [31:0] mdu_rd; + wire mdu_ready; + + servant_arbiter arbiter( + .i_wb_cpu_dbus_adr (wb_dmem_adr), + .i_wb_cpu_dbus_dat (wb_dmem_dat), + .i_wb_cpu_dbus_sel (wb_dmem_sel), + .i_wb_cpu_dbus_we (wb_dmem_we ), + .i_wb_cpu_dbus_cyc (wb_dmem_cyc), + .o_wb_cpu_dbus_rdt (wb_dmem_rdt), + .o_wb_cpu_dbus_ack (wb_dmem_ack), + + .i_wb_cpu_ibus_adr (wb_ibus_adr), + .i_wb_cpu_ibus_cyc (wb_ibus_cyc), + .o_wb_cpu_ibus_rdt (wb_ibus_rdt), + .o_wb_cpu_ibus_ack (wb_ibus_ack), + + .o_wb_cpu_adr (wb_mem_adr), + .o_wb_cpu_dat (wb_mem_dat), + .o_wb_cpu_sel (wb_mem_sel), + .o_wb_cpu_we (wb_mem_we ), + .o_wb_cpu_cyc (wb_mem_cyc), + .i_wb_cpu_rdt (wb_mem_rdt), + .i_wb_cpu_ack (wb_mem_ack) + ); + + servant_mux #(sim) servant_mux + ( + .i_clk (wb_clk), + .i_rst (wb_rst & (reset_strategy != "NONE")), + .i_wb_cpu_adr (wb_dbus_adr), + .i_wb_cpu_dat (wb_dbus_dat), + .i_wb_cpu_sel (wb_dbus_sel), + .i_wb_cpu_we (wb_dbus_we), + .i_wb_cpu_cyc (wb_dbus_cyc), + .o_wb_cpu_rdt (wb_dbus_rdt), + .o_wb_cpu_ack (wb_dbus_ack), + + .o_wb_mem_adr (wb_dmem_adr), + .o_wb_mem_dat (wb_dmem_dat), + .o_wb_mem_sel (wb_dmem_sel), + .o_wb_mem_we (wb_dmem_we), + .o_wb_mem_cyc (wb_dmem_cyc), + .i_wb_mem_rdt (wb_dmem_rdt), + + .o_wb_gpio_adr (wb_gpio_adr), + .o_wb_gpio_dat (wb_gpio_dat), + .o_wb_gpio_we (wb_gpio_we), + .o_wb_gpio_cyc (wb_gpio_cyc), + .i_wb_gpio_rdt (wb_gpio_rdt), + + .o_wb_acc_adr (o_wb_acc_adr), + .o_wb_acc_dat (o_wb_acc_dat), + .o_wb_acc_we (o_wb_acc_we), + .o_wb_acc_cyc (o_wb_acc_cyc), + .i_wb_acc_rdt (i_wb_acc_rdt), + .i_wb_acc_ack (i_wb_acc_ack), + + .o_wb_timer_adr (wb_timer_adr), + .o_wb_timer_dat (wb_timer_dat), + .o_wb_timer_we (wb_timer_we), + .o_wb_timer_cyc (wb_timer_cyc), + .i_wb_timer_rdt (wb_timer_rdt)); + + servant_ram + #(.memfile (memfile), + .depth (memsize), + .RESET_STRATEGY (reset_strategy)) + ram + (// Wishbone interface + .i_wb_clk (wb_clk), + .i_wb_rst (wb_rst), + .i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]), + .i_wb_cyc (wb_mem_cyc), + .i_wb_we (wb_mem_we) , + .i_wb_sel (wb_mem_sel), + .i_wb_dat (wb_mem_dat), + .o_wb_rdt (wb_mem_rdt), + .o_wb_ack (wb_mem_ack), + + .enb_debug(enb_debug) + ); + + //`ifdef IEEG + servant_timer + #(.RESET_STRATEGY (reset_strategy), + .WIDTH (32)) + timer + (.i_clk (wb_clk), // always on clk + .i_rst (wb_rst), + .o_irq (), + .i_wb_cyc (wb_timer_cyc), + .i_wb_we (wb_timer_we) , + .i_wb_dat (wb_timer_dat), + .o_wb_rdt ()); + + // EMG + +wire timer_irq_debug; +wire wb_timer_rdt_debug; + +`ifdef PS_SLOW_TIMER + servant_slow_timer_ps + + timer_slow_ps + ( .i_clk (wb_clk), // serv stops gating stops with the interrupt + .slow_clk (timer_clk), + .i_rst (wb_rst), + .o_irq (timer_irq_debug), + .i_wb_cyc (wb_timer_cyc), + .i_wb_we (wb_timer_we) , + .i_wb_dat (wb_timer_dat), + .o_wb_rdt (wb_timer_rdt_debug)); +`else + + servant_slow_timer_new + #(.RESET_STRATEGY (reset_strategy), + .WIDTH (32)) + timer_slow_new + (.i_clk (wb_clk), // serv stops gating stops with the interrupt + .slow_clk (timer_clk), + .i_rst (wb_rst), + .o_irq (timer_irq), + .i_wb_cyc (wb_timer_cyc), + .i_wb_we (wb_timer_we) , + .i_wb_dat (wb_timer_dat), + .o_wb_rdt (wb_timer_rdt)); +`endif + + servant_gpio gpio + (.i_wb_clk (wb_clk), + .i_wb_adr (wb_gpio_adr), + .i_wb_dat (wb_gpio_dat), + .i_wb_we (wb_gpio_we), + .i_wb_cyc (wb_gpio_cyc), + .o_wb_rdt (wb_gpio_rdt), + .led (led), + .buttons(buttons)); + + serv_rf_top + #(.RESET_PC (32'h0000_0000), + .RESET_STRATEGY (reset_strategy), + `ifdef MDU + .MDU(1), + `endif + .WITH_CSR (with_csr), + .COMPRESSED(compress), + .ALIGN(align)) + cpu + ( + .clk (wb_clk), + .i_rst (wb_rst), + .i_timer_irq (timer_irq), +`ifdef RISCV_FORMAL + .rvfi_valid (), + .rvfi_order (), + .rvfi_insn (), + .rvfi_trap (), + .rvfi_halt (), + .rvfi_intr (), + .rvfi_mode (), + .rvfi_ixl (), + .rvfi_rs1_addr (), + .rvfi_rs2_addr (), + .rvfi_rs1_rdata (), + .rvfi_rs2_rdata (), + .rvfi_rd_addr (), + .rvfi_rd_wdata (), + .rvfi_pc_rdata (), + .rvfi_pc_wdata (), + .rvfi_mem_addr (), + .rvfi_mem_rmask (), + .rvfi_mem_wmask (), + .rvfi_mem_rdata (), + .rvfi_mem_wdata (), +`endif + + .o_ibus_adr (wb_ibus_adr), + .o_ibus_cyc (wb_ibus_cyc), + .i_ibus_rdt (wb_ibus_rdt), + .i_ibus_ack (wb_ibus_ack), + + .o_dbus_adr (wb_dbus_adr), + .o_dbus_dat (wb_dbus_dat), + .o_dbus_sel (wb_dbus_sel), + .o_dbus_we (wb_dbus_we), + .o_dbus_cyc (wb_dbus_cyc), + .i_dbus_rdt (wb_dbus_rdt), + .i_dbus_ack (wb_dbus_ack), + + //Extension + .o_ext_rs1 (mdu_rs1), + .o_ext_rs2 (mdu_rs2), + .o_ext_funct3 (mdu_op), + .i_ext_rd (mdu_rd), + .i_ext_ready (mdu_ready), + //MDU + .o_mdu_valid (mdu_valid)); + +`ifdef MDU + mdu_top mdu_serv + ( + .i_clk(wb_clk), + .i_rst(wb_rst), + .i_mdu_rs1(mdu_rs1), + .i_mdu_rs2(mdu_rs2), + .i_mdu_op(mdu_op), + .i_mdu_valid(mdu_valid), + .o_mdu_ready(mdu_ready), + .o_mdu_rd(mdu_rd)); +`else + assign mdu_ready = 1'b0; + assign mdu_rd = 32'b0; +`endif + +endmodule +/* + Basic serial transmitter (UART) + Copyright (c) 2020 Stanislav Jurny (github.com/STjurny) license MIT + + Serial data format is 8 data bits, without parity, one stop bit (8N1) without hardware flow control. + Set parameters pClockFrequency and pBaudRate to requirements of your design (pBaudRate can be + max 1/3 of pClockFrequency). For high baud rates check values of parametrization report pInaccuracyPerFrame and + pInaccuracyThreshhold to ensure that ClockFrequency / BaudRate ratio generates acceptable inaccuracy of frame length. + Generally pInaccuracyPerFrame have to be less than pInaccuracyThreshhold. For ideal ratio is pInaccuracyPerFrame = 0. + + For send a byte set iData to required value and set iSend to 1 for at least one clock cycle. The module + takes over data into its own buffer and starts transmitting. The iData value has to be valid only for first tick + after iSend was asserted. The signal oReady indicates readiness to take over next byte for send. The signal is + set to 0 after take over byte to send and during transmitting the start and data bits. After last data bit sent + the oReady signal is immediatelly set to 1 so a next byte to send can be pass already during transmitting + stop bit of previous byte. Because of that there is not any delay before transmitting the next byte. + + Module supports automatic power on reset (after load bitstream to the FPGA), explicit reset over iReset signal or both + of them. Mode of reset is determined by preprocessor symbols GlobalReset and PowerOnReset. Edit the Global.inc file + to select reset modes. +*/ + +`define GlobalReset + + +module SerialTransmitter #( + parameter pClockFrequency = 24000000, + //^ System clock frequency. + + parameter pBaudRate = 4000000 + //^ Serial output baud rate (..., 9600, 115200, 2000000, ...) + //^ Can be value from arbitrary low to max 1/3 of pClockFrequency. +)( + input wire iClock, + //^ System clock with frequency specified in the parameter pClockFrequency. + + input wire [7:0] iData, + //^ Data to send (have to be valid first clock after set iSend to 1). + + input wire iSend, + //^ Set to 1 for at least one clock cycle for start the sending. + + output wire oReady, + //^ Signalizes readiness to take over next byte to send. + + output wire oTxd + //^ Serial data output with baudrate specified in the parameter pBaudRate. + + + ,input wire iReset + //^ Reset module to initial state (reset is synchronized with posedge, set to 1 for one clock is enough). + //^ Module can begin transmit data in next clock tick after the iReset was set to 0. + +); + + +localparam + pTicksPerBit = pClockFrequency / pBaudRate, + pBitTimerMsb = $clog2(pTicksPerBit) - 1, + pLastTickOfBit = pTicksPerBit - 1; + +localparam + pTicksPerFrame = pClockFrequency * 10 / pBaudRate, + pInaccuracyPerFrame = pTicksPerFrame - pTicksPerBit * 10, + pInaccuracyThreshhold = pTicksPerBit / 2; + +`ifdef SIM + + initial // parametrization report + begin + $display("%m|1|--"); + + `ifdef GlobalReset + $display("%m|1|GlobalReset = yes"); + `else + $display("%m|1|GlobalReset = no"); + `endif + + `ifdef PowerOnReset + $display("%m|1|PowerOnReset = yes"); + `else + $display("%m|1|PowerOnReset = no"); + `endif + + $display("%m|1|pClockFrequency = '%d", pClockFrequency); + $display("%m|1|pBaudRate = '%d", pBaudRate); + $display("%m|1|--"); + $display("%m|1|pTicksPerBit = '%d", pTicksPerBit); + $display("%m|1|pTicksPerFrame = '%d", pTicksPerFrame); + $display("%m|1|--"); + $display("%m|1|pInaccuracyPerFrame = '%d", pInaccuracyPerFrame); + $display("%m|1|pInaccuracyThreshhold = '%d", pInaccuracyThreshhold); + $display("%m|1|--"); + $display("%m|1|pLastTickOfBit = '%d", pLastTickOfBit); + $display("%m|1|cBitTimer range = '%d:0", pBitTimerMsb); + + if (pTicksPerBit < 3) + begin + $display("%m|0|Error: Parameter pBaudrate can be max 1/3 of clock frequency."); + $stop; + end + end + +`endif + +localparam // $State:2,st + stIdle = 0, + stStartBit = 1, + stDataBit = 2, + stStopBit = 3; + + +reg [pBitTimerMsb:0] cBitTimer; +reg cBitSent; + +reg [1:0] cState; +reg [7:0] cBuffer; +reg [2:0] cBitIndex; + +reg cReady; +assign oReady = cReady; + +reg cnTxd; +assign oTxd = ~cnTxd; // negation because iCEcude2 can initialize registers after power on reset only to zero + + +`ifdef PowerOnReset +initial + begin + cBitTimer = 0; + cBitSent = 0; + + cState = stIdle; + cReady = 0; + cBitIndex = 0; + + cnTxd = 0; + end +`endif + + +always @(posedge iClock) // serial bit output timer + `ifdef GlobalReset + if (iReset) + begin + cBitTimer <= 0; + cBitSent <= 0; + end + else + `endif + begin + if (cState == stIdle || cBitSent) + cBitTimer <= 0; + else + cBitTimer <= cBitTimer + 1; + + // comparison is potentially complex so we do it separately one clock earlier + cBitSent <= cBitTimer == (pLastTickOfBit[pBitTimerMsb:0] - 1); + end + + +always @(posedge iClock) // transmitter FSM + `ifdef GlobalReset + if (iReset) + begin + cState <= stIdle; + cReady <= 0; + cBitIndex <= 0; + end + else + `endif + case (cState) + stIdle: + if (iSend) + begin + cBuffer <= iData; + cReady <= 0; + cState <= stStartBit; + end + else + cReady <= 1; + + stStartBit: + if (cBitSent) + cState <= stDataBit; + + stDataBit: + if (cBitSent) + begin + cBuffer <= cBuffer >> 1; + cBitIndex <= cBitIndex + 1; + + if (cBitIndex == 7) + begin + cReady <= 1; + cState <= stStopBit; + end; + end + + stStopBit: + begin: stopBit + reg nReady; + nReady = cReady; + + if (cReady && iSend) // next byte to send can be passed before sending of stop bit is completed + begin // so there isn't any delay before beginning of sending next byte + cBuffer <= iData; + nReady = 0; + end + + if (cBitSent) + if (~nReady) + cState <= stStartBit; + else + cState <= stIdle; + + cReady <= nReady; + end + endcase + + +always @(posedge iClock) // registered serial output prevents glitches + `ifdef GlobalReset + if (iReset) + cnTxd <= 0; + else + `endif + cnTxd <= ~( + cState == stIdle || + cState == stStopBit || + cState == stDataBit && cBuffer[0] // cBuffer LSB is a currently sending bit + ); + + +endmodule + + + + + + + + + + + + + + + + + + +/* Arbitrates between dbus and ibus accesses. + * Relies on the fact that not both masters are active at the same time + */ +module servant_arbiter + ( + input wire [31:0] i_wb_cpu_dbus_adr, + input wire [31:0] i_wb_cpu_dbus_dat, + input wire [3:0] i_wb_cpu_dbus_sel, + input wire i_wb_cpu_dbus_we, + input wire i_wb_cpu_dbus_cyc, + output wire [31:0] o_wb_cpu_dbus_rdt, + output wire o_wb_cpu_dbus_ack, + + input wire [31:0] i_wb_cpu_ibus_adr, + input wire i_wb_cpu_ibus_cyc, + output wire [31:0] o_wb_cpu_ibus_rdt, + output wire o_wb_cpu_ibus_ack, + + output wire [31:0] o_wb_cpu_adr, + output wire [31:0] o_wb_cpu_dat, + output wire [3:0] o_wb_cpu_sel, + output wire o_wb_cpu_we, + output wire o_wb_cpu_cyc, + input wire [31:0] i_wb_cpu_rdt, + input wire i_wb_cpu_ack); + + assign o_wb_cpu_dbus_rdt = i_wb_cpu_rdt; + assign o_wb_cpu_dbus_ack = i_wb_cpu_ack & !i_wb_cpu_ibus_cyc; + + assign o_wb_cpu_ibus_rdt = i_wb_cpu_rdt; + assign o_wb_cpu_ibus_ack = i_wb_cpu_ack & i_wb_cpu_ibus_cyc; + + assign o_wb_cpu_adr = i_wb_cpu_ibus_cyc ? i_wb_cpu_ibus_adr : i_wb_cpu_dbus_adr; + assign o_wb_cpu_dat = i_wb_cpu_dbus_dat; + assign o_wb_cpu_sel = i_wb_cpu_dbus_sel; + assign o_wb_cpu_we = i_wb_cpu_dbus_we & !i_wb_cpu_ibus_cyc; + assign o_wb_cpu_cyc = i_wb_cpu_ibus_cyc | i_wb_cpu_dbus_cyc; + +endmodule +`default_nettype none +module servant_clock_gen + ( + input wire i_clk, + input wire i_rst, + output wire o_clk, + output wire o_half_clk, + output wire o_slow_clk, + output wire o_rst, + output wire o_rst_gfcm, + input wire bypass, + input wire low_power_mode + ); + + parameter SIM = 0; + parameter DOUBLE_CLOCK = 0; + parameter DIVR = 4'b0000; + parameter DIVF = 7'b0110100; + parameter DIVQ = 7'b0110100; + parameter HFOSC = "0'b01"; + + localparam RESET_LENGTH = 12; + reg [RESET_LENGTH-1:0] rst_reg = 0; + always @(posedge o_half_clk) + rst_reg <= {rst_reg[RESET_LENGTH-2:0],1'b1}; + assign o_rst = ~rst_reg[RESET_LENGTH-1]; + assign o_rst_gfcm = ~rst_reg[2]; + + generate + if(SIM) begin + + if(DOUBLE_CLOCK) + begin + assign o_half_clk = i_clk | ~low_power_mode; + + reg spi_clk_reg = 0; + always #15.5 spi_clk_reg <= !spi_clk_reg | ~low_power_mode; + assign o_clk = spi_clk_reg | ~low_power_mode; + end + else // single clock + begin + assign o_half_clk = i_clk | ~low_power_mode; + assign o_clk = i_clk | ~low_power_mode; + end + + reg slow_clk_reg = 0; + always #50000 slow_clk_reg <= !slow_clk_reg; + assign o_slow_clk = slow_clk_reg; + + end + else begin // not sim + + if(DOUBLE_CLOCK) + begin + SB_PLL40_2F_PAD + pll + ( + .PACKAGEPIN (i_clk), + .PLLOUTCOREA(o_clk), + .PLLOUTCOREB(o_half_clk), + .RESETB(1'b1), + .BYPASS(bypass), + .LATCHINPUTVALUE(low_power_mode) + ); + + //\\ Fin=12, Fout=45; + defparam pll.DIVR = DIVR; + defparam pll.DIVF = DIVF; + defparam pll.DIVQ = DIVQ; + defparam pll.FILTER_RANGE = 3'b001; + defparam pll.FEEDBACK_PATH = "SIMPLE"; + defparam pll.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; + defparam pll.FDA_FEEDBACK = 4'b0000; + defparam pll.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; + defparam pll.FDA_RELATIVE = 4'b0000; + defparam pll.SHIFTREG_DIV_MODE = 2'b00; + defparam pll.PLLOUT_SELECT_PORTA = "GENCLK"; + defparam pll.PLLOUT_SELECT_PORTB = "GENCLK_HALF"; + //defparam pll.PLLOUT_SELECT = "GENCLK"; + defparam pll.ENABLE_ICEGATE_PORTA = 1'b1; + defparam pll.ENABLE_ICEGATE_PORTB = 1'b1; + //defparam pll.ENABLE_ICEGATE = 1'b0; + end + else + begin // single clock + /* + SB_PLL40_PAD + pll + ( + .PACKAGEPIN (i_clk), + .PLLOUTCORE(o_clk), + .RESETB(1'b1), + .BYPASS(bypass), + .LATCHINPUTVALUE(low_power_mode) + ); + + assign o_half_clk = o_clk; + + //\\ Fin=12, Fout=45; + defparam pll.DIVR = DIVR; + defparam pll.DIVF = DIVF; + defparam pll.DIVQ = DIVQ; + defparam pll.FILTER_RANGE = 3'b001; + defparam pll.FEEDBACK_PATH = "SIMPLE"; + defparam pll.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; + defparam pll.FDA_FEEDBACK = 4'b0000; + defparam pll.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; + defparam pll.FDA_RELATIVE = 4'b0000; + defparam pll.SHIFTREG_DIV_MODE = 2'b00; + defparam pll.PLLOUT_SELECT = "GENCLK"; + defparam pll.ENABLE_ICEGATE = 1'b1; + */ + + SB_HFOSC + hfosc + ( + .CLKHFEN(low_power_mode), // andrebbe a zero per 100 us ma se a 6 MHz funziona lo stesso + .CLKHFPU(1'b1), + .CLKHF(o_clk) + ); + + // synthesis ROUTE_THROUGH_FABRIC= 1 + //the value can be either 0 or 1 + + // Parameter CLKHF_DIV = "0b00" (default), "0b01", "0b10", "0b11" + // 0b00 = 48 MHz, 0b01 = 24 MHz, 0b10 = 12 MHz, 0b11 = 6 MHz + defparam hfosc.CLKHF_DIV = HFOSC; + + assign o_half_clk = o_clk; + + end + + SB_LFOSC u_lf_osc(.CLKLFPU(1'b1), .CLKLFEN(1'b1), .CLKLF(o_slow_clk)); + + end + endgenerate + +endmodule +module servant_gpio + (input wire i_wb_clk, + input wire [31:0] i_wb_adr, + input wire [31:0] i_wb_dat, + input wire i_wb_we, + input wire i_wb_cyc, + output reg [31:0] o_wb_rdt, + output wire [3:0] led, + input [2:0] buttons + ); + +/* always @(posedge i_wb_clk) begin + o_wb_rdt <= {buttons,27'b0,o_gpio}; + if (i_wb_cyc & i_wb_we) + o_gpio <= i_wb_dat[1:0]; + end*/ + +reg [3:0] o_gpio_reg; + +always @(posedge i_wb_clk) begin + o_wb_rdt <= {buttons,25'b0,o_gpio_reg}; + if (i_wb_cyc & i_wb_we) + o_gpio_reg <= i_wb_dat[3:0]; + end + +assign led = o_gpio_reg; + +/* +always @(posedge i_wb_clk) begin + o_wb_rdt <= {buttons,o_gpio[28:0]}; + if (i_wb_cyc & i_wb_we) + o_gpio <= i_wb_dat; + end +*/ +endmodule +/* + mem = 00 + gamux = 01 + timer = 10 + testcon = 11 + */ +module servant_mux + ( + input wire i_clk, + input wire i_rst, + input wire [31:0] i_wb_cpu_adr, + input wire [31:0] i_wb_cpu_dat, + input wire [3:0] i_wb_cpu_sel, + input wire i_wb_cpu_we, + input wire i_wb_cpu_cyc, + output wire [31:0] o_wb_cpu_rdt, + output reg o_wb_cpu_ack, + + output wire [31:0] o_wb_mem_adr, + output wire [31:0] o_wb_mem_dat, + output wire [3:0] o_wb_mem_sel, + output wire o_wb_mem_we, + output wire o_wb_mem_cyc, + input wire [31:0] i_wb_mem_rdt, + + output wire [31:0] o_wb_gpio_adr, + output wire [31:0] o_wb_gpio_dat, + output wire o_wb_gpio_we, + output wire o_wb_gpio_cyc, + input wire [31:0] i_wb_gpio_rdt, + + output wire [31:0] o_wb_timer_adr, + output wire [31:0] o_wb_timer_dat, + output wire o_wb_timer_we, + output wire o_wb_timer_cyc, + input wire [31:0] i_wb_timer_rdt, + + output wire [31:0] o_wb_acc_adr, + output wire [31:0] o_wb_acc_dat, + output wire o_wb_acc_we, + output wire o_wb_acc_cyc, + input wire [31:0] i_wb_acc_rdt, + input wire i_wb_acc_ack + ); + + parameter sim = 0; + + wire [1:0] s = i_wb_cpu_adr[31:30]; + + assign o_wb_cpu_rdt = (s == 2'b11) ? i_wb_gpio_rdt : + (s == 2'b10) ? i_wb_timer_rdt : + (s == 2'b01) ? i_wb_acc_rdt : + i_wb_mem_rdt; + + always @(posedge i_clk) begin + o_wb_cpu_ack <= 1'b0; + if (i_wb_cpu_cyc & !o_wb_cpu_ack & (s != 2'b01)) + o_wb_cpu_ack <= 1'b1; + if (i_wb_cpu_cyc & !o_wb_cpu_ack & (s == 2'b01)) // bram read requires 1 extra clock-cycle + o_wb_cpu_ack <= i_wb_acc_ack; + if (i_rst) + o_wb_cpu_ack <= 1'b0; + end + + assign o_wb_mem_adr = i_wb_cpu_adr; + assign o_wb_mem_dat = i_wb_cpu_dat; + assign o_wb_mem_sel = i_wb_cpu_sel; + assign o_wb_mem_we = i_wb_cpu_we; + assign o_wb_mem_cyc = i_wb_cpu_cyc & (s == 2'b00); + + assign o_wb_acc_adr = i_wb_cpu_adr; + assign o_wb_acc_dat = i_wb_cpu_dat; + assign o_wb_acc_we = i_wb_cpu_we; + assign o_wb_acc_cyc = i_wb_cpu_cyc & (s == 2'b01); + + assign o_wb_timer_adr = i_wb_cpu_adr; + assign o_wb_timer_dat = i_wb_cpu_dat; + assign o_wb_timer_we = i_wb_cpu_we; + assign o_wb_timer_cyc = i_wb_cpu_cyc & (s == 2'b10); + + assign o_wb_gpio_adr = i_wb_cpu_adr; + assign o_wb_gpio_dat = i_wb_cpu_dat; + assign o_wb_gpio_we = i_wb_cpu_we; + assign o_wb_gpio_cyc = i_wb_cpu_cyc & (s == 2'b11); + + generate + if (sim) begin + wire sig_en = (i_wb_cpu_adr[31:28] == 4'h8) & i_wb_cpu_cyc & o_wb_cpu_ack; + wire halt_en = (i_wb_cpu_adr[31:28] == 4'h9) & i_wb_cpu_cyc & o_wb_cpu_ack; + + reg [1023:0] signature_file; + integer f = 0; + + initial + /* verilator lint_off WIDTH */ + if ($value$plusargs("signature=%s", signature_file)) begin + $display("Writing signature to %0s", signature_file); + f = $fopen(signature_file, "w"); + end + /* verilator lint_on WIDTH */ + + always @(posedge i_clk) + if (sig_en & (f != 0)) + $fwrite(f, "%c", i_wb_cpu_dat[7:0]); + else if(halt_en) begin + $display("Test complete"); + $finish; + end + end + endgenerate +endmodule +`default_nettype none +module servant_ram +#(//Memory parameters + parameter depth = 256, + parameter aw = $clog2(depth), + parameter RESET_STRATEGY = "", + parameter memfile = "") +( + input wire i_wb_clk, + input wire i_wb_rst, + input wire [aw-1:2] i_wb_adr, + input wire [31:0] i_wb_dat, + input wire [3:0] i_wb_sel, + input wire i_wb_we, + input wire i_wb_cyc, + output [31:0] o_wb_rdt, + output reg o_wb_ack, + + input wire enb_debug +); + + wire [3:0] we = {4{i_wb_we & i_wb_cyc}} & i_wb_sel; + + reg [31:0] mem [0:depth/4-1] /* verilator public */; + + wire [aw-3:0] addr = i_wb_adr[aw-1:2]; + + always @(posedge i_wb_clk) + if (i_wb_rst & (RESET_STRATEGY != "NONE")) + o_wb_ack <= 1'b0; + else + o_wb_ack <= i_wb_cyc & !o_wb_ack; + + + ihp_ram #(.memfile(memfile)) sevant_ram + ( + .clk(i_wb_clk), + .we(we), + .addr(addr), + .dina(i_wb_dat), + .dout(o_wb_rdt), + .enb_debug(enb_debug) + ); +/* + always @(posedge i_wb_clk) begin + if (we[0]) mem[addr][7:0] <= i_wb_dat[7:0]; + if (we[1]) mem[addr][15:8] <= i_wb_dat[15:8]; + if (we[2]) mem[addr][23:16] <= i_wb_dat[23:16]; + if (we[3]) mem[addr][31:24] <= i_wb_dat[31:24]; + o_wb_rdt <= mem[addr]; + end + + + + initial + if(|memfile) begin +`ifndef ISE + $display("Preloading %m from %s", memfile); +`endif + $readmemh(memfile, mem); + end + +*/ + +endmodule +`default_nettype none +module servant_slow_timer_new + #( + parameter WIDTH = 16, + parameter RESET_STRATEGY = "", + parameter DIVIDER = 0 + ) + + ( + input wire i_clk, slow_clk, + input wire i_rst, + output reg o_irq, + input wire [31:0] i_wb_dat, + input wire i_wb_we, + input wire i_wb_cyc, + output reg [31:0] o_wb_rdt + ); + + localparam HIGH = WIDTH-1-DIVIDER; + + reg [WIDTH-1:0] mtime; + reg [HIGH:0] mtimecmp; + + wire [HIGH:0] mtimeslice = mtime[WIDTH-1:DIVIDER]; + + always @(mtimeslice) begin + o_wb_rdt = 32'd0; + o_wb_rdt[HIGH:0] = mtimeslice; + end + + always @(posedge i_clk) begin + if (RESET_STRATEGY != "NONE") + if (i_rst) begin + mtimecmp <= 0; + end + if (i_wb_cyc & i_wb_we) begin + mtimecmp <= i_wb_dat[HIGH:0]; + end + + end + + wire wr_en; + assign wr_en = i_wb_cyc & i_wb_we; + + always @(posedge slow_clk, posedge wr_en, posedge i_rst) begin + if (RESET_STRATEGY != "NONE") + if (wr_en) + mtime <= 0; + else if (i_rst) + mtime <= 0; + else if(mtimeslice <= mtimecmp) + mtime <= mtime + 'd1; + else + mtime <= 0; + end + + + always @(posedge slow_clk) + o_irq <= (mtimeslice >= mtimecmp); + +endmodule + + + + + + + + + + + + +`default_nettype none +module servant_timer + #(parameter WIDTH = 16, + parameter RESET_STRATEGY = "", + parameter DIVIDER = 0) + (input wire i_clk, + input wire i_rst, + output reg o_irq, + input wire [31:0] i_wb_dat, + input wire i_wb_we, + input wire i_wb_cyc, + output reg [31:0] o_wb_rdt); + + localparam HIGH = WIDTH-1-DIVIDER; + + reg [WIDTH-1:0] mtime; + reg [HIGH:0] mtimecmp; + + wire [HIGH:0] mtimeslice = mtime[WIDTH-1:DIVIDER]; + + always @(mtimeslice) begin + o_wb_rdt = 32'd0; + o_wb_rdt[HIGH:0] = mtimeslice; + end + + always @(posedge i_clk) begin + if (RESET_STRATEGY != "NONE") + if (i_rst) begin + mtime <= 0; + mtimecmp <= 0; + end + if (i_wb_cyc & i_wb_we) begin + mtimecmp <= i_wb_dat[HIGH:0]; + mtime <= 0; + end + else begin + mtime <= mtime + 'd1; + end + o_irq <= (mtimeslice >= mtimecmp); + end +endmodule +`default_nettype none + +`ifdef SIM + `include `CONFIG_PATH +`else + `include "./config.txt" +`endif + +module service_ihp #( + parameter SIM = 1, + parameter ENCODING_BYPASS = 0, + parameter CHANNELS = `INPUT_CHANNELS, + parameter ORDER = 2, + parameter WINDOW = 8192, + parameter REF_PERIOD = 1024, + parameter DW = `DW, + + parameter WIDTH = 16, + + parameter MAX_NEURONS = 128, + parameter MAX_SYNAPSES = 128, + + parameter INPUT_SPIKE_1 = `INPUT_SPIKE_1, + parameter NEURON_1 = `NEURON_1, + parameter WEIGHTS_FILE_1 = "weights_1.txt", + parameter [13:0] current_decay_1 = `CURRENT_DECAY_1, + parameter [13:0] voltage_decay_1 = `VOLTAGE_DECAY_1, + parameter [WIDTH-1:0] threshold_1 = `THRESHOLD_1, + + parameter INPUT_SPIKE_2 = NEURON_1, + parameter NEURON_2 = `NEURON_2, + parameter WEIGHTS_FILE_2 = "weights_2.txt", + parameter [13:0] current_decay_2 = `CURRENT_DECAY_2, + parameter [13:0] voltage_decay_2 = `VOLTAGE_DECAY_2, + parameter [WIDTH-1:0] threshold_2 = `THRESHOLD_2, + + parameter INPUT_SPIKE_3 = NEURON_2, + parameter NEURON_3 = `NEURON_3, + parameter WEIGHTS_FILE_3 = "weights_3.txt", + parameter [13:0] current_decay_3 = `CURRENT_DECAY_3, + parameter [13:0] voltage_decay_3 = `VOLTAGE_DECAY_3, + parameter [WIDTH-1:0] threshold_3 = `THRESHOLD_3, + + parameter INPUT_SPIKE_4 = NEURON_3, + parameter NEURON_4 = `NEURON_4, + parameter WEIGHTS_FILE_4 = "weights_4.txt", + parameter [13:0] current_decay_4 = `CURRENT_DECAY_4, + parameter [13:0] voltage_decay_4 = `VOLTAGE_DECAY_4, + parameter [WIDTH-1:0] threshold_4 = `THRESHOLD_4, + + parameter DOUBLE_CLOCK = 0, // if DOUBLE_CLOCK = 0 clk is generated from HFOSC, allowed freq are 48,24,12,6 + parameter pClockFrequency = 24_000_000/(DOUBLE_CLOCK+1), + parameter DIVR = 4'b0000, + parameter DIVF = 7'b1010100, + parameter DIVQ = 3'b110, + parameter HFOSC = "0b01", // "0b00" = 48 MHz, "0b01" = 24 MHz, "0b10" = 12 MHz, "0b11" = 6 MHz + + parameter memfile = "firmware/exe.hex", + parameter memsize = 4096, + parameter PLL = "NONE" +) +( + output wire [3:0] led, + input wire [2:0] buttons, + output wire o_flash_ss, + output wire o_flash_sck, + output wire o_flash_mosi, + input wire i_flash_miso, + output wire o_txd, + + //input di servant_clk_gen + input wire wb_clk, + input wire wb_rst, + + output wire gate_general, gate_snn, gate_serv, + input wire timer_clk, + + output output_buffer_wr_en_debug, + output signed [WIDTH-1:0] p1, p2, + input enb_debug + +); + + localparam WEIGHT_DEPTH_12 = 8192; + localparam WEIGHT_DEPTH_34 = 8192; + + +////////////////////////////////////////////////////////////////////////////////////// +// ____ _____ ______ ___ _ _ _____ // +// / ___|| ____| _ \ \ / / \ | \ | |_ _| // +// \___ \| _| | |_) \ \ / / _ \ | \| | | | // +// ___) | |___| _ < \ V / ___ \| |\ | | | // +// |____/|_____|_| \_\ \_/_/ \_\_| \_| |_| // +// ____ _____ ______ __ ____ ___ ____ ______ __ ____ ____ // +// / ___|| ____| _ \ \ / / | _ \|_ _/ ___| / ___\ \ / / / ___| ___ / ___| // +// \___ \| _| | |_) \ \ / / | |_) || |\___ \| | \ \ / / \___ \ / _ \| | // +// ___) | |___| _ < \ V / | _ < | | ___) | |___ \ V / ___) | (_) | |___ // +// |____/|_____|_| \_\ \_/ |_| \_\___|____/ \____| \_/ |____/ \___/ \____| // +// // +////////////////////////////////////////////////////////////////////////////////////// + + wire [31:0] wb_acc_adr; + wire [31:0] wb_acc_dat; + wire wb_acc_we; + wire wb_acc_cyc; + wire [31:0] wb_acc_rdt; + wire wb_acc_ack; + + wire acc_snn_valid; + wire output_buffer_ren; + wire [7:0] output_buffer_addr; + wire [31:0] output_buffer_out; + wire [31:0] acc_snn_adr_w1; + wire [31:0] acc_snn_adr_w2; + wire [31:0] acc_snn_adr_w3; + wire [31:0] acc_snn_adr_w4; + wire [ 4:0] acc_snn_we; + wire [15:0] acc_snn_dat; + wire [clogb2(MAX_SYNAPSES-1)-1:0] snn_input_channels; + wire [clogb2(MAX_NEURONS-1)-1:0] neuron_1, neuron_2, neuron_3, neuron_4; + wire [2:0] layers; + wire [ 7:0] uart_byte; + wire [ 3:0] sel; + wire uart_tx_go; + wire uart_tx_done; + wire [7:0] o_spike_mem_dat; + wire [7:0] i_spike_mem_adr; + wire [1:0] i_spike_mem_rd_en; + wire [1:0] i_spike_mem_wr_en; + wire [3:0] i_spike_mem_dat; + wire [15:0] o_sample_mem_dat; + wire [7:0] i_sample_mem_adr; + wire i_sample_mem_rd_en; + wire i_sample_mem_wr_en; + wire [15:0] i_sample_mem_dat; + wire encoding_bypass; + // wire gate_spi, gate_snn, gate_enc, gate_serv, gate_general; + wire gate_spi, gate_enc; + wire timer_irq; + + + servant #( + .memfile (memfile) + ) + + servant( + .wb_clk (wb_clk), + .timer_clk(timer_clk), + .wb_rst (wb_rst), + + .led (led), + .buttons(buttons), + .timer_irq(timer_irq), + + .o_wb_acc_adr (wb_acc_adr), + .o_wb_acc_dat (wb_acc_dat), + .o_wb_acc_we (wb_acc_we), + .o_wb_acc_cyc (wb_acc_cyc), + .i_wb_acc_rdt (wb_acc_rdt), + .i_wb_acc_ack (wb_acc_ack), + + .enb_debug(enb_debug) + ); + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ____ _ _ ____ ___ _ _ _____ _____ ____ ____ ___ _ _ _ _ _____ ____ _____ // +// | __ )| | | / ___| |_ _| \ | |_ _| ____| _ \ / ___/ _ \| \ | | \ | | ____/ ___|_ _| // +// | _ \| | | \___ \ | || \| | | | | _| | |_) | | | | | | \| | \| | _|| | | | // +// | |_) | |_| |___) | | || |\ | | | | |___| _ <| |__| |_| | |\ | |\ | |__| |___ | | // +// |____/ \___/|____/ |___|_| \_| |_| |_____|_| \_\\____\___/|_| \_|_| \_|_____\____| |_| // +// __ _ _ _ __ // +// / _| | __ _ ___| |__ (_)_ __ / _| ___ _ __ ___ _ __ ___ ___ // +// | |_| |/ _` / __| '_ \ | | '_ \| |_ / _ \ '__/ _ \ '_ \ / __/ _ \ // +// | _| | (_| \__ \ | | | _ | | | | | _| __/ | | __/ | | | (_| __/ _ // +// |_| |_|\__,_|___/_| |_| ( ) |_|_| |_|_| \___|_| \___|_| |_|\___\___| ( ) // +// |/ _ _ _ |/ // +// ___ __ _ _ __ ___ _ __ | | ___ ___ _ __ (_) | _____ _ __ ___ ___ _ __ ___ ___ // +// / __|/ _` | '_ ` _ \| '_ \| |/ _ \ / __| '_ \| | |/ / _ \ | '_ ` _ \ / _ \ '_ ` _ \/ __| // +// \__ \ (_| | | | | | | |_) | | __/ _ \__ \ |_) | | < __/ | | | | | | __/ | | | | \__ \ // +// |___/\__,_|_| |_| |_| .__/|_|\___| ( ) |___/ .__/|_|_|\_\___| |_| |_| |_|\___|_| |_| |_|___/ // +// |_| |/ |_| // +// // +//////////////////////////////////////////////////////////////////////////////////////////////////// + + accelerator_top + acc_top( + + .wb_clk(wb_clk), + .spi_clk(wb_clk), + .wb_rst(wb_rst), + + .i_cpu_adr(wb_acc_adr), + .i_cpu_dat(wb_acc_dat), + .i_cpu_we(wb_acc_we), + .i_cpu_cyc(wb_acc_cyc), + .o_cpu_rdt(wb_acc_rdt), + .o_cpu_ack(wb_acc_ack), + + .o_flash_sck(o_flash_sck), + .o_flash_mosi(o_flash_mosi), + .o_flash_ss(o_flash_ss), + .i_flash_miso(i_flash_miso), + + .i_snn_valid(acc_snn_valid), + .output_buffer_ren(output_buffer_ren), + .output_buffer_addr(output_buffer_addr), + .output_buffer_out(output_buffer_out), + .o_snn_adr_w1(acc_snn_adr_w1), + .o_snn_adr_w2(acc_snn_adr_w2), + .o_snn_adr_w3(acc_snn_adr_w3), + .o_snn_adr_w4(acc_snn_adr_w4), + .o_snn_we(acc_snn_we), + .o_snn_dat(acc_snn_dat), + .snn_input_channels(snn_input_channels), + .neuron_1(neuron_1), .neuron_2(neuron_2), .neuron_3(neuron_3), .neuron_4(neuron_4), + .layers(layers), + .o_txd(o_txd), + .i_spike_mem_dat(o_spike_mem_dat), + .o_spike_mem_adr(i_spike_mem_adr), + .o_spike_mem_rd_en(i_spike_mem_rd_en), + .o_spike_mem_wr_en(i_spike_mem_wr_en), + .o_spike_mem_dat(i_spike_mem_dat), + .i_sample_mem_dat(o_sample_mem_dat), + .o_sample_mem_adr(i_sample_mem_adr), + .o_sample_mem_rd_en(i_sample_mem_rd_en), + .o_sample_mem_wr_en(i_sample_mem_wr_en), + .o_sample_mem_dat(i_sample_mem_dat), + .o_encoding_bypass(encoding_bypass), + .gate_spi(gate_spi), .gate_snn(gate_snn), .gate_enc(gate_enc), .gate_serv(gate_serv), + .timer_irq(timer_irq), .gate_general(gate_general) + ); + + + + +/////////////////////////////////////////////////////////////////////////////////////// +// ____ _ _ // +// / ___| _ _ _ __ | |_ _____ _| |_ _ _ // +// \___ \| | | | '_ \| __|_ / | | | | | | | (_) // +// ___) | |_| | | | | |_ / /| |_| | | |_| | _ // +// |____/ \__, |_| |_|\__/___|\__,_|_|\__,_| (_) // +// __ __|___/ _ _ _ _ _ // +// | \/ | ___ ___ __ _ _ _(_) |_ ___ | (_) | _____ // +// | |\/| |/ _ \/ __|/ _` | | | | | __/ _ \ _____ | | | |/ / _ \ // +// | | | | (_) \__ \ (_| | |_| | | || (_) | |_____| | | | < __/ // +// |_| |_|\___/|___/\__, |\__,_|_|\__\___/ |_|_|_|\_\___| // +// |_| // +// _____ _ _ _ ____ ___ __ __ ____ // +// | ____(_) __ _| |__ | |_ __ ____ _ _ _ / ___|_ _| \/ | _ \ // +// | _| | |/ _` | '_ \| __| _____ \ \ /\ / / _` | | | | \___ \| || |\/| | | | | // +// | |___| | (_| | | | | |_ |_____| \ V V / (_| | |_| | ___) | || | | | |_| | // +// |_____|_|\__, |_| |_|\__| \_/\_/ \__,_|\__, | |____/___|_| |_|____/ // +// |___/ |___/ // +// ____ _ _ _ _ // +// / ___|| \ | | \ | | _ __ _ __ ___ ___ ___ ___ ___ ___ _ __ // +// \___ \| \| | \| | | '_ \| '__/ _ \ / __/ _ \/ __/ __|/ _ \| '__| // +// ___) | |\ | |\ | | |_) | | | (_) | (_| __/\__ \__ \ (_) | | // +// |____/|_| \_|_| \_| | .__/|_| \___/ \___\___||___/___/\___/|_| // +// |_| // +// // +/////////////////////////////////////////////////////////////////////////////////////// + + Syntzulu + + mosquito + ( + .clk_enc (wb_clk), + .clk_snn (wb_clk), + .rst (wb_rst), + + .en (acc_snn_we[4]), + .data_in (acc_snn_dat), + .detect (1'b1), + + .encoding_bypass(1'b0), + + .valid (acc_snn_valid), + + .weight_mem_L1_wren ({8{acc_snn_we[0]}}), + .weight_mem_L1_wr_addr (acc_snn_adr_w1), + .weight_mem_L1_data_in (acc_snn_dat), + .weight_mem_L1_ena (acc_snn_we[0]), + + .weight_mem_L2_wren ({8{acc_snn_we[1]}}), + .weight_mem_L2_wr_addr (acc_snn_adr_w2), + .weight_mem_L2_data_in (acc_snn_dat), + .weight_mem_L2_ena (acc_snn_we[1]), + + .weight_mem_L3_wren ({8{acc_snn_we[2]}}), + .weight_mem_L3_wr_addr (acc_snn_adr_w3), + .weight_mem_L3_data_in (acc_snn_dat), + .weight_mem_L3_ena (acc_snn_we[2]), + + .weight_mem_L4_wren ({8{acc_snn_we[3]}}), + .weight_mem_L4_wr_addr (acc_snn_adr_w4), + .weight_mem_L4_data_in (acc_snn_dat), + .weight_mem_L4_ena (acc_snn_we[3]), + + // ACCESSIBILITY + .o_spike_mem_dat(o_spike_mem_dat), + .i_spike_mem_adr(i_spike_mem_adr), + .i_spike_mem_rd_en(i_spike_mem_rd_en), + .i_spike_mem_wr_en(i_spike_mem_wr_en), + .i_spike_mem_dat(i_spike_mem_dat), + .o_sample_mem_dat(o_sample_mem_dat), + .i_sample_mem_adr(i_sample_mem_adr), + .i_sample_mem_rd_en(i_sample_mem_rd_en), + .i_sample_mem_wr_en(i_sample_mem_wr_en), + .i_sample_mem_dat(i_sample_mem_dat), + + // CONFIGURABILITY + .snn_input_channels(snn_input_channels), + .neuron_1(neuron_1), .neuron_2(neuron_2), .neuron_3(neuron_3), .neuron_4(neuron_4), + .layers(layers), + + // OUTPUT BUFFER ACCESS + + .output_buffer_ren(output_buffer_ren), + .output_buffer_addr(output_buffer_addr), + .output_buffer_out(output_buffer_out), + + .output_buffer_wr_en_debug(output_buffer_wr_en_debug), + .p1(p1), + .p2(p2), + + .enb_debug(enb_debug) + ); + + + // The following function calculates the address width based on specified RAM depth + function integer clogb2; + input integer depth; + for (clogb2=0; depth>0; clogb2=clogb2+1) + depth = depth >> 1; + endfunction + +endmodule +`default_nettype none + +`define OPENROAD_CLKGATE + +`ifdef SIM + `include `CONFIG_PATH +`else + `include "./config.txt" +`endif + +module service_ihp_chip +( + //output wire [3:0] led, + input wire [2:0] buttons, + + output wire o_flash_ss, + output wire o_flash_sck, + output wire o_flash_mosi, + input wire i_flash_miso, + + //input di servant_clk_gen + input wire wb_clk, + input wire wb_rst, + + //output wire gate_general, + // output wire gate_snn, gate_serv, + input wire timer_clk, + + //output wire output_buffer_wr_en_debug, + //output wire signed [15:0] p1, p2, + input wire enb_debug + + //output wire o_txd + +); + + wire [2:0] buttons_i; + wire [3:0] led_i; + wire signed [15:0] p1_i, p2_i; + + wire wb_clk_i, wb_rst_i, enb_debug_i, timer_clk_i, i_flash_miso_i; + wire o_flash_ss_i, o_flash_sck_i, o_flash_mosi_i; + wire gate_general_i, gate_snn_i, gate_serv_i; + wire output_buffer_wr_en_debug_i; + + wire o_txd_i; + + // sg13g2_IOPadIn pad_wb_clk (.pad(wb_clk), .p2c(wb_clk_i)); + // sg13g2_IOPadIn pad_wb_rst (.pad(wb_rst), .p2c(wb_rst_i)); + // sg13g2_IOPadIn pad_enb_debug (.pad(enb_debug), .p2c(enb_debug_i)); + // sg13g2_IOPadIn pad_timer_clk (.pad(timer_clk), .p2c(timer_clk_i)); + + // sg13g2_IOPadIn pad_i_flash_miso (.pad(i_flash_miso), .p2c(i_flash_miso_i)); + // sg13g2_IOPadOut16mA pad_o_flash_ss (.pad(o_flash_ss), .c2p(o_flash_ss_i)); + // sg13g2_IOPadOut16mA pad_o_flash_sck (.pad(o_flash_sck), .c2p(o_flash_sck_i)); + // sg13g2_IOPadOut16mA pad_o_flash_mosi (.pad(o_flash_mosi), .c2p(o_flash_mosi_i)); + + // sg13g2_IOPadIn pad_buttons_0 (.pad(buttons[0]), .p2c(buttons_i[0])); + // sg13g2_IOPadIn pad_buttons_1 (.pad(buttons[1]), .p2c(buttons_i[1])); + // sg13g2_IOPadIn pad_buttons_2 (.pad(buttons[2]), .p2c(buttons_i[2])); + + assign wb_clk_i = wb_clk; + assign wb_rst_i = wb_rst; + assign enb_debug_i = enb_debug; + assign timer_clk_i = timer_clk; + assign i_flash_miso_i = i_flash_miso; + assign o_flash_ss = o_flash_ss_i; + assign o_flash_sck = o_flash_sck_i; + assign o_flash_mosi = o_flash_mosi_i; + assign buttons_i[0] = buttons[0]; + assign buttons_i[1] = buttons[1]; + assign buttons_i[2] = buttons[2]; + + //sg13g2_IOPadOut16mA pad_o_txd (.pad(o_txd), .c2p(o_txd_i)); + + + //sg13g2_IOPadOut16mA pad_gate_general (.pad(gate_general), .c2p(gate_general_i)); + +/* + sg13g2_IOPadOut16mA pad_gate_snn (.pad(gate_snn), .c2p(gate_snn_i)); + sg13g2_IOPadOut16mA pad_gate_serv (.pad(gate_serv), .c2p(gate_serv_i)); + + + sg13g2_IOPadOut16mA pad_led_0 (.pad(led[0]), .c2p(led_i[0])); + sg13g2_IOPadOut16mA pad_led_1 (.pad(led[1]), .c2p(led_i[1])); + sg13g2_IOPadOut16mA pad_led_2 (.pad(led[2]), .c2p(led_i[2])); + sg13g2_IOPadOut16mA pad_led_3 (.pad(led[3]), .c2p(led_i[3])); + + + sg13g2_IOPadOut16mA pad_output_buffer_wr_en_debug (.pad(output_buffer_wr_en_debug), .c2p(output_buffer_wr_en_debug_i)); + sg13g2_IOPadOut16mA pad_p1_0 (.pad(p1[0]), .c2p(p1_i[0])); + sg13g2_IOPadOut16mA pad_p1_1 (.pad(p1[1]), .c2p(p1_i[1])); + sg13g2_IOPadOut16mA pad_p1_2 (.pad(p1[2]), .c2p(p1_i[2])); + sg13g2_IOPadOut16mA pad_p1_3 (.pad(p1[3]), .c2p(p1_i[3])); + sg13g2_IOPadOut16mA pad_p1_4 (.pad(p1[4]), .c2p(p1_i[4])); + sg13g2_IOPadOut16mA pad_p1_5 (.pad(p1[5]), .c2p(p1_i[5])); + sg13g2_IOPadOut16mA pad_p1_6 (.pad(p1[6]), .c2p(p1_i[6])); + sg13g2_IOPadOut16mA pad_p1_7 (.pad(p1[7]), .c2p(p1_i[7])); + sg13g2_IOPadOut16mA pad_p1_8 (.pad(p1[8]), .c2p(p1_i[8])); + sg13g2_IOPadOut16mA pad_p1_9 (.pad(p1[9]), .c2p(p1_i[9])); + sg13g2_IOPadOut16mA pad_p1_10 (.pad(p1[10]), .c2p(p1_i[10])); + sg13g2_IOPadOut16mA pad_p1_11 (.pad(p1[11]), .c2p(p1_i[11])); + sg13g2_IOPadOut16mA pad_p1_12 (.pad(p1[12]), .c2p(p1_i[12])); + sg13g2_IOPadOut16mA pad_p1_13 (.pad(p1[13]), .c2p(p1_i[13])); + sg13g2_IOPadOut16mA pad_p1_14 (.pad(p1[14]), .c2p(p1_i[14])); + sg13g2_IOPadOut16mA pad_p1_15 (.pad(p1[15]), .c2p(p1_i[15])); + + sg13g2_IOPadOut16mA pad_p2_0 (.pad(p2[0]), .c2p(p2_i[0])); + sg13g2_IOPadOut16mA pad_p2_1 (.pad(p2[1]), .c2p(p2_i[1])); + sg13g2_IOPadOut16mA pad_p2_2 (.pad(p2[2]), .c2p(p2_i[2])); + sg13g2_IOPadOut16mA pad_p2_3 (.pad(p2[3]), .c2p(p2_i[3])); + sg13g2_IOPadOut16mA pad_p2_4 (.pad(p2[4]), .c2p(p2_i[4])); + sg13g2_IOPadOut16mA pad_p2_5 (.pad(p2[5]), .c2p(p2_i[5])); + sg13g2_IOPadOut16mA pad_p2_6 (.pad(p2[6]), .c2p(p2_i[6])); + sg13g2_IOPadOut16mA pad_p2_7 (.pad(p2[7]), .c2p(p2_i[7])); + sg13g2_IOPadOut16mA pad_p2_8 (.pad(p2[8]), .c2p(p2_i[8])); + sg13g2_IOPadOut16mA pad_p2_9 (.pad(p2[9]), .c2p(p2_i[9])); + sg13g2_IOPadOut16mA pad_p2_10 (.pad(p2[10]), .c2p(p2_i[10])); + sg13g2_IOPadOut16mA pad_p2_11 (.pad(p2[11]), .c2p(p2_i[11])); + sg13g2_IOPadOut16mA pad_p2_12 (.pad(p2[12]), .c2p(p2_i[12])); + sg13g2_IOPadOut16mA pad_p2_13 (.pad(p2[13]), .c2p(p2_i[13])); + sg13g2_IOPadOut16mA pad_p2_14 (.pad(p2[14]), .c2p(p2_i[14])); + sg13g2_IOPadOut16mA pad_p2_15 (.pad(p2[15]), .c2p(p2_i[15])); +*/ + + wire gate_general, wb_clk_i_gated; + + OPENROAD_CLKGATE gating_cell (wb_clk_i, gate_general, wb_clk_i_gated); + + + service_ihp service_ihp( + + .buttons(buttons_i), + + .o_flash_ss(o_flash_ss_i), + .o_flash_sck(o_flash_sck_i), + .o_flash_mosi(o_flash_mosi_i), + .i_flash_miso(i_flash_miso_i), + //.o_txd(o_txd_i), + + .wb_clk (wb_clk_i_gated ), + .wb_rst (wb_rst_i ), + .timer_clk (timer_clk_i), + + .gate_general(gate_general), + //.gate_snn (gate_snn_i), + //.gate_serv (gate_serv_i), + + .enb_debug(enb_debug_i) + + + //.output_buffer_wr_en_debug(output_buffer_wr_en_debug_i), + //.p1(p1_i), .p2(p2_i) + + ); + + + // The following function calculates the address width based on specified RAM depth + function integer clogb2; + input integer depth; + for (clogb2=0; depth>0; clogb2=clogb2+1) + depth = depth >> 1; + endfunction + +endmodule +`default_nettype none + +`ifdef SIM + `include `CONFIG_PATH +`else + `include "./config.txt" +`endif + +module service_ihp_top #( + parameter SIM = 1, + parameter ENCODING_BYPASS = 0, + parameter CHANNELS = `INPUT_CHANNELS, + parameter ORDER = 2, + parameter WINDOW = 8192, + parameter REF_PERIOD = 1024, + parameter DW = `DW, + + parameter WIDTH = 16, + + parameter MAX_NEURONS = 128, + parameter MAX_SYNAPSES = 128, + + parameter INPUT_SPIKE_1 = `INPUT_SPIKE_1, + parameter NEURON_1 = `NEURON_1, + parameter WEIGHTS_FILE_1 = "weights_1.txt", + parameter [13:0] current_decay_1 = `CURRENT_DECAY_1, + parameter [13:0] voltage_decay_1 = `VOLTAGE_DECAY_1, + parameter [WIDTH-1:0] threshold_1 = `THRESHOLD_1, + + parameter INPUT_SPIKE_2 = NEURON_1, + parameter NEURON_2 = `NEURON_2, + parameter WEIGHTS_FILE_2 = "weights_2.txt", + parameter [13:0] current_decay_2 = `CURRENT_DECAY_2, + parameter [13:0] voltage_decay_2 = `VOLTAGE_DECAY_2, + parameter [WIDTH-1:0] threshold_2 = `THRESHOLD_2, + + parameter INPUT_SPIKE_3 = NEURON_2, + parameter NEURON_3 = `NEURON_3, + parameter WEIGHTS_FILE_3 = "weights_3.txt", + parameter [13:0] current_decay_3 = `CURRENT_DECAY_3, + parameter [13:0] voltage_decay_3 = `VOLTAGE_DECAY_3, + parameter [WIDTH-1:0] threshold_3 = `THRESHOLD_3, + + parameter INPUT_SPIKE_4 = NEURON_3, + parameter NEURON_4 = `NEURON_4, + parameter WEIGHTS_FILE_4 = "weights_4.txt", + parameter [13:0] current_decay_4 = `CURRENT_DECAY_4, + parameter [13:0] voltage_decay_4 = `VOLTAGE_DECAY_4, + parameter [WIDTH-1:0] threshold_4 = `THRESHOLD_4, + + parameter DOUBLE_CLOCK = 0, // if DOUBLE_CLOCK = 0 clk is generated from HFOSC, allowed freq are 48,24,12,6 + parameter pClockFrequency = 24_000_000/(DOUBLE_CLOCK+1), + parameter DIVR = 4'b0000, + parameter DIVF = 7'b1010100, + parameter DIVQ = 3'b110, + parameter HFOSC = "0b01", // "0b00" = 48 MHz, "0b01" = 24 MHz, "0b10" = 12 MHz, "0b11" = 6 MHz + + parameter memfile = "firmware/exe.hex", + parameter memsize = 4096, + parameter PLL = "ICE40_PAD" +) +( + input wire i_clk, i_rst, + output wire [3:0] led, + input wire [2:0] buttons, + output wire o_flash_ss, + output wire o_flash_sck, + output wire o_flash_mosi, + input wire i_flash_miso, + output wire o_txd +); + + localparam WEIGHT_DEPTH_12 = 8192; + localparam WEIGHT_DEPTH_34 = 8192; + +////////////////////////////////////////////////////////////////////////////////// +// ____ _ _ ____ _ _ __ ____ _____ _ _ // +// | _ \| | | | _ / ___| | | |/ /___ / ___| ____| \ | | // +// | |_) | | | | (_) | | | | | ' // __| _____ | | _| _| | \| | // +// | __/| |___| |___ _ | |___| |___| . \\__ \ |_____| | |_| | |___| |\ | // +// |_| |_____|_____| (_) \____|_____|_|\_\___/ \____|_____|_| \_| // +// // +////////////////////////////////////////////////////////////////////////////////// + + wire wb_clk; + wire wb_rst; + wire spi_clk; + wire rst_gfcm; + wire slow_clk; + wire gate_general; + + + servant_clock_gen #(.SIM(SIM), .DOUBLE_CLOCK(DOUBLE_CLOCK), .DIVR(DIVR), .DIVF(DIVF), .DIVQ(DIVQ), .HFOSC(HFOSC)) + clock_gen( + .i_clk (i_clk), + .i_rst (i_rst), + .o_clk (spi_clk), + .o_half_clk (wb_clk), + .o_slow_clk (slow_clk), // 10 kHz + .o_rst (wb_rst), + .o_rst_gfcm (rst_gfcm), + .bypass (1'b0), + .low_power_mode(1'b1) //mettere gate_general se si vuole il gating -- mettere 1'b1 se non si vuole il gating + ); + + wire timer_clk; + wire gate_snn; + wire gate_serv; + wire rst; + + wire spi_clk_g; + wire wb_clk_snn; + wire wb_clk_enc; + wire wb_clk_serv; + + assign rst = wb_rst; + + + `ifdef LOW_POWER + assign spi_clk_g = spi_clk; + assign wb_clk_snn = wb_clk; + assign wb_clk_enc = wb_clk; + assign wb_clk_serv = wb_clk; + + `else + assign spi_clk_g = spi_clk; + assign wb_clk_snn = wb_clk; + assign wb_clk_enc = wb_clk; + assign wb_clk_serv = wb_clk; + `endif + + assign timer_clk = slow_clk; + + + service_ihp_chip + + service_ihp_chip( + + //.led(led), + .buttons(buttons), + + .o_flash_ss(o_flash_ss), + .o_flash_sck(o_flash_sck), + .o_flash_mosi(o_flash_mosi), + .i_flash_miso(i_flash_miso), + + .wb_clk (i_clk ), + .wb_rst (wb_rst ), + .timer_clk (timer_clk), + .enb_debug(1'b1) + + //.o_txd(o_txd) + + //.gate_general(gate_general) + //.gate_snn (gate_snn), + //.gate_serv (gate_serv), + + + ); + + + + // The following function calculates the address width based on specified RAM depth + function integer clogb2; + input integer depth; + for (clogb2=0; depth>0; clogb2=clogb2+1) + depth = depth >> 1; + endfunction + +endmodule +`default_nettype none +module snn_addr_counter +#( + parameter DEPTH = 8192 +) +( + input wire clk, + input wire rst, + input wire clr, + input wire inc, + output reg [clogb2(DEPTH)-1:0] addr +); + + always @(posedge clk) begin + if (rst | clr) begin + addr <= 0; + end + else if (inc) begin + addr <= addr + 1; + end + end + + function integer clogb2; + input integer depth; + for (clogb2=0; depth>0; clogb2=clogb2+1) + depth = depth >> 1; + endfunction + +endmodule`default_nettype none + +module spi_acc_control #(parameter DOUBLE_CLOCK = 0) ( + input wire wb_clk, + input wire wb_rst, + + input wire i_if_start, + output wire o_if_load1, + output wire o_if_load2, + output wire o_if_snn_we, + output wire o_if_set0, + output wire o_if_clr, + + input wire i_spi_valid, + input wire i_spi_end, + output wire o_spi_en, + output wire o_spi_read_ack + ); + + reg [4:0] out; + reg if_load1_ff, if_load2_ff, if_snn_we_ff, if_set0_ff, if_clr_ff; + wire if_load1, if_load2, if_snn_we, if_set0, if_clr; + + assign {o_spi_en, if_load1, if_load2, if_snn_we, if_set0} = out; + assign if_clr = o_spi_en; + assign o_spi_read_ack = if_snn_we; + + assign o_if_load1 = DOUBLE_CLOCK? (if_load1 | if_load1_ff) : if_load1; + assign o_if_load2 = DOUBLE_CLOCK? (if_load2 | if_load2_ff) : if_load2; + assign o_if_snn_we = DOUBLE_CLOCK? (if_snn_we | if_snn_we_ff) : if_snn_we; + assign o_if_set0 = DOUBLE_CLOCK? (if_set0 | if_set0_ff) : if_set0; + assign o_if_clr = DOUBLE_CLOCK? (if_clr | if_clr_ff) : if_clr; + + parameter [2:0] + IDLE = 0, + ENABLE = 1, + WAIT_DATA1 = 2, + WAIT_DATA2 = 3, + WRITE_DATA = 4, + END_SET0 = 5, + DUMMY = 6; + + reg [2:0] state, state_next; + + // state transition + always @(posedge wb_clk) begin + if (wb_rst) begin + state <= IDLE; + if_load1_ff <= 0; + if_load2_ff <= 0; + if_snn_we_ff <= 0; + if_set0_ff <= 0; + if_clr_ff <= 0; + end + else begin + state <= state_next; + if_load1_ff <= if_load1; + if_load2_ff <= if_load2; + if_snn_we_ff <= if_snn_we; + if_set0_ff <= if_set0; + if_clr_ff <= if_clr; + end + end + + // next state and output logic + always @(*) begin + case (state) + IDLE: begin + out = 5'b0xx00; + if (i_if_start) begin + state_next = ENABLE; + end + else begin + state_next = IDLE; + end + end + ENABLE: begin + out = 5'b1xx00; + state_next = WAIT_DATA1; + end + WAIT_DATA1: begin + out = 5'b01x00; + if (i_spi_valid) begin + state_next = WAIT_DATA2; + end + else begin + state_next = WAIT_DATA1; + end + end + WAIT_DATA2: begin + out = 5'b00100; + if (i_spi_valid) begin + state_next = DUMMY; + end + else begin + state_next = WAIT_DATA2; + end + end + DUMMY: begin + out = 5'b00000; + state_next = WRITE_DATA; + end + WRITE_DATA: begin + out = 5'b00010; + if (i_spi_end) begin + state_next = END_SET0; + end + else begin + state_next = WAIT_DATA1; + end + end + END_SET0: begin + out = 5'b0xx01; + state_next = IDLE; + end + default: begin + out = 5'b0xx0x; + state_next = IDLE; + end + endcase + end + +endmodule +//spi master module for flash reading (N25Q032A) +module spi_master( + input wire clk, + input wire reset, + output reg SPI_SCK, + output SPI_SS, + output reg SPI_MOSI, + input wire SPI_MISO, + input en, + input [23:0] addr, + output reg valid, + output reg end_transaction, + input wire rd_ack, + output reg [7:0] rd_data, + input wire [17:0] words_to_read, + input read_req, + input [7:0] wr_data + ); + + //states + parameter [2:0] IDLE = 0, SEND_CMD = 1, SEND_ADDR= 2, READ_FLASH= 3, WAIT_ACK = 4, SEND_WREN_CMD = 5, WRITE_FLASH = 6; + + reg [2:0] counter_clk; + reg [17:0] counter_send; //64 max + reg [2:0] state; + reg [23:0] read_addr_reg; + reg [7:0] wr_data_reg; + reg [7:0] read_cmd; + reg [7:0] write_cmd; + reg [7:0] write_en_cmd; + reg [7:0] cmd; + reg spi_ss_reg; + reg read_req_r; + reg [17:0] words_to_read_reg; + reg [17:0] words_to_read_reg_sub0, words_to_read_reg_sub1; + + assign SPI_SS = spi_ss_reg; + + /*initial begin + SPI_SCK = 0; + valid = 0; + + counter_clk = 0; + counter_send = 0; + state = IDLE; + read_addr_reg = 0; + end_transaction <= 0; + + //bunch of commands to read status registers as well as the flash from the datasheet + read_cmd = 8'h03; //read + write_en_cmd = 8'h06; // page program + write_cmd = 8'h02; // page program + + SPI_MOSI = 0; + spi_ss_reg = 1; //active low + rd_data = 0; + + words_to_read_reg <= 0; + end*/ + + always @(posedge clk) + begin + if(reset == 1) begin + state <= IDLE; + end else begin + case (state) + IDLE : begin //wait for an address to be written + spi_ss_reg <= 1; //un select slave + + // signals from initial + SPI_SCK <= 0; + valid <= 0; + counter_clk <= 0; + counter_send <= 0; + //read_addr_reg <= 0; + end_transaction <= 0; + //bunch of commands to read status registers as well as the flash from the datasheet + read_cmd <= 8'h03; //read + write_en_cmd <= 8'h06; // page program + write_cmd <= 8'h02; // page program + + SPI_MOSI <= 0; + spi_ss_reg <= 1; //active low + rd_data <= 0; + + // words_to_read_reg <= 0; + // end signals from initial + + if(en == 1) begin + read_addr_reg <= addr; + wr_data_reg <= wr_data; + state <= read_req?SEND_CMD:SEND_WREN_CMD; //go directly to the sending of the READ command + cmd <= read_req?read_cmd:write_cmd; + read_req_r <= read_req; + words_to_read_reg <= words_to_read; + end + end + + //send a wake up command to the flash, not needed when only reading the flash + //skipped here + SEND_WREN_CMD : begin + counter_clk <= counter_clk + 1; + spi_ss_reg <= 0; + + if(counter_clk == 3'b000)begin + SPI_MOSI <= write_en_cmd[7]; //MSB + SPI_SCK <= 0; + end + + if(counter_clk >= 3'b001) begin + SPI_SCK <= 1; + write_en_cmd[7:0] <= {write_en_cmd[6:0], write_en_cmd[7]}; + counter_clk <= 0; + counter_send <= counter_send + 1; + if(counter_send == 7) begin + spi_ss_reg <= 1; + state <= SEND_CMD; + counter_send <= 0; + end + end + + end + + //send the read command (8 bit) + SEND_CMD : begin + counter_clk <= counter_clk + 1; + spi_ss_reg <= 0; + + if(counter_clk == 3'b000)begin + SPI_SCK <= 0; + SPI_MOSI <= cmd[7]; //MSB + end + + if(counter_clk >= 3'b001) begin + SPI_SCK <= 1; + cmd[7:0] <= {cmd[6:0], cmd[7]}; + counter_clk <= 0; + counter_send <= counter_send + 1; + if(counter_send == 7) begin + state <= SEND_ADDR; + counter_send <= 0; + end + end + + end + + //send the 24bit address we want to read from + SEND_ADDR : begin + counter_clk <= counter_clk + 1; + spi_ss_reg <= 0; //slave is selected + + if(counter_clk == 3'b000) begin + SPI_MOSI <= read_addr_reg[23]; //MSB + SPI_SCK <= 0; + end + + if(counter_clk == 3'b001) begin + SPI_SCK <= 1; + end + + if(counter_clk == 3'b010) begin + SPI_SCK <= 0; + read_addr_reg[23:0] <= {read_addr_reg[22:0], read_addr_reg[23]}; + counter_clk <= 0; + counter_send <= counter_send + 1; + if(counter_send == 23) begin + state <= read_req_r?READ_FLASH:WRITE_FLASH; + words_to_read_reg_sub0 <= words_to_read_reg; + counter_send <= 0; + + end + end + end + + //read the actual flash value (32bit) + READ_FLASH: begin + counter_clk <= counter_clk + 1; + SPI_MOSI <= 0; + spi_ss_reg <= 0; //slave is selected + valid = 0; // init + + if(counter_clk == 3'b000) begin + SPI_SCK <= 1; + words_to_read_reg_sub1 <= words_to_read_reg_sub0-1; + + end + + if(counter_clk == 3'b001) begin + SPI_SCK <= 0; + rd_data[7:0] <= {rd_data[6:0], SPI_MISO}; + counter_clk <= 0; + counter_send <= counter_send + 1; + if(counter_send[2:0] == 7) begin + valid <= 1; + if(counter_send == /* words_to_read_reg-1 */words_to_read_reg_sub1) begin + counter_send <= 0; + state <= WAIT_ACK; + spi_ss_reg <= 1; //un select slave + end + end + else valid <= 0; + end + + end + + + + //now that the data is saved, wait for the next read request + WAIT_ACK: begin + spi_ss_reg <= 1; //un select slave + end_transaction <= 1; + valid <= 0; + if(rd_ack == 1) begin + state <= IDLE; + end_transaction <= 0; + end + end + default: begin + state <= IDLE; + end + endcase + + end + end +endmodule +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 06.03.2024 16:14:13 +// Design Name: +// Module Name: delta_modulator_multichannel +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module delta_modulator_multichannel #( + parameter CHANNELS = 16, + parameter WIDTH = 16 + ) +( + input wire clk, // Clock input + input wire rst, // Reset input + input wire en, + input wire signed [WIDTH-1:0] samples, // Analog input samples (8-bit resolution) + output reg pos_spike, neg_spike, // Delta modulation output + output reg valid +); + + reg signed [WIDTH-1:0] data_in_pipe; + wire signed [WIDTH-1:0] delta; + + reg [clogb2(CHANNELS-1)-1:0] channel_cnt, r_channel_cnt, rr_channel_cnt; + always @(posedge clk) + if (rst) begin + channel_cnt <= 0; + r_channel_cnt <= 0; + rr_channel_cnt <= 0; + end + else begin + if(en) + channel_cnt <= channel_cnt + 1'b1; + r_channel_cnt <= channel_cnt; + rr_channel_cnt <= r_channel_cnt; + end + + wire signed [WIDTH-1:0] data_old; // old sample + + ihp_dualport_256x48_dualmem + #( + .RAM_WIDTH(WIDTH), + .RAM_DEPTH(CHANNELS), + .RAM_PERFORMANCE("LOW_LATENCY"), + .INIT_FILE("") + ) + sample_mem + ( + .addra(rr_channel_cnt), + .addrb(channel_cnt), + .dina(prev_sample), + .clk(clk), + .wea(en_dd), + .ena(en_dd), + .enb(en), + .rst(rst), + .regceb(1'b1), + + .doutb(data_old) + ); + + ihp_single_port_256x48 + #( + .RAM_WIDTH(WIDTH), + .RAM_DEPTH(CHANNELS), + .RAM_PERFORMANCE("LOW_LATENCY"), + .INIT_FILE("sim/mem/emg/delta.txt") + ) + delta_mem + ( + .addra(), + .addrb(channel_cnt), + .dina(), + .clk(clk), + .wea(1'b0), + .ena(1'b0), + .enb(en), + .rst(rst), + .regceb(1'b1), + + .doutb(delta) + ); + + reg signed [WIDTH-1:0] prev_sample; // next value to store + reg signed [WIDTH-1:0] samples_d; + always @(posedge clk) samples_d <= samples; + + + always @(posedge clk ) begin + if (rst) begin + prev_sample <= 0; + {pos_spike, neg_spike} <= 0; + end else + begin + if (samples_d < (data_old - delta)) + begin + {pos_spike, neg_spike} <= 2'b01; + prev_sample <= data_old-delta; + end + else if (samples_d > (data_old + delta)) + begin + {pos_spike, neg_spike} <= 2'b10; + prev_sample <= data_old+delta; + end + else + begin + {pos_spike, neg_spike} <= 2'b00; + prev_sample <= data_old; + end + end + end + + reg en_d, en_dd; + always @(posedge clk) + begin + en_d <= en; + en_dd <= en_d; + valid <= en_d; + end + +//////////////////////////// +// _ ____ // +// | | ___ __ _ |___ \ // +// | |/ _ \ / _` | __) // +// | | (_) | (_| | / __/ // +// |_|\___/ \__, | |_____ // +// |___/ // +//////////////////////////// + +// The following function calculates the address width based on specified RAM depth +function integer clogb2; + input integer depth; + for (clogb2=0; depth>0; clogb2=clogb2+1) + depth = depth >> 1; +endfunction + +endmodule +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 03.11.2022 10:58:43 +// Design Name: +// Module Name: fifo +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module fifo +#( +parameter DATA_WIDTH = 25, DEPTH = 256 +) +( +input clk, rst, +input [DATA_WIDTH-1:0] DI, +input rden, wren, +output [DATA_WIDTH-1:0] DO + ); + +reg [DATA_WIDTH-1:0] fifo [DEPTH-1:0]; + +integer i; +always @(posedge clk) + if(rst) + for(i=0;i0; clogb2=clogb2+1) + depth = depth >> 1; + endfunction + +endmodule +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 03.11.2022 11:06:53 +// Design Name: +// Module Name: stack +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module stack +#( +parameter DATA_WIDTH = 4, +parameter DEPTH = 24 +) +( +input clk, rst, +input [DATA_WIDTH-1:0] din, +input wr_en, clear, +input stream_out, + +output [DATA_WIDTH-1:0] dout, +output reg done, +output [clogb2(DEPTH-1)-1:0] active_entries, +output empty +); + +// shift register +reg [DATA_WIDTH-1:0] shift [DEPTH-1:0]; +integer i; +always@(posedge clk) + if (rst) + for(i=0;i0; clogb2=clogb2+1) + depth = depth >> 1; +endfunction + +endmodule diff --git a/designs/src/SYNtzulA/config.txt b/designs/src/SYNtzulA/config.txt new file mode 100644 index 0000000..3405d39 --- /dev/null +++ b/designs/src/SYNtzulA/config.txt @@ -0,0 +1,21 @@ +`define DW 8 +`define INPUT_CHANNELS 16 +`define INPUT_SPIKE_1 32 +`define NEURON_1 64 +`define NEURON_2 128 +`define NEURON_3 64 +`define NEURON_4 16 +`define CURRENT_DECAY_1 4096-4096 +`define CURRENT_DECAY_2 4096-4096 +`define CURRENT_DECAY_3 4096-4096 +`define CURRENT_DECAY_4 4096-4096 + +`define VOLTAGE_DECAY_1 4096-42 +`define VOLTAGE_DECAY_2 4096-42 +`define VOLTAGE_DECAY_3 4096-42 +`define VOLTAGE_DECAY_4 4096-41 + +`define THRESHOLD_1 19 +`define THRESHOLD_2 17 +`define THRESHOLD_3 11 +`define THRESHOLD_4 32767 diff --git a/designs/src/SYNtzulA/dev/patch-synsnn.patch b/designs/src/SYNtzulA/dev/patch-synsnn.patch new file mode 100644 index 0000000..3371daf --- /dev/null +++ b/designs/src/SYNtzulA/dev/patch-synsnn.patch @@ -0,0 +1,351 @@ +diff --git a/rtl/behavioural_ihp/RM_IHPSG13_1P_2048x64_c2_bm_bist.v b/rtl/behavioural_ihp/RM_IHPSG13_1P_2048x64_c2_bm_bist.v +index 879690e..ba9b1b6 100755 +--- a/rtl/behavioural_ihp/RM_IHPSG13_1P_2048x64_c2_bm_bist.v ++++ b/rtl/behavioural_ihp/RM_IHPSG13_1P_2048x64_c2_bm_bist.v +@@ -55,14 +55,6 @@ module RM_IHPSG13_1P_2048x64_c2_bm_bist #(parameter INIT_FILE="") ( + input [63:0] A_BIST_DIN; + input [63:0] A_BIST_BM; + +- //inserito perchè openSTA nella report activity mette ad unknown data out perchè forse è a x all'inizio +- initial begin +- +- $deposit(i_SRAM_1P_behavioral_bm_bist.A_DOUT, 64'b0); +- +- end +- +- + `ifdef FUNCTIONAL // functional // + + +diff --git a/rtl/behavioural_ihp/RM_IHPSG13_1P_core_behavioral_bm_bist.v b/rtl/behavioural_ihp/RM_IHPSG13_1P_core_behavioral_bm_bist.v +index 38b3fd5..eb81821 100755 +--- a/rtl/behavioural_ihp/RM_IHPSG13_1P_core_behavioral_bm_bist.v ++++ b/rtl/behavioural_ihp/RM_IHPSG13_1P_core_behavioral_bm_bist.v +@@ -67,14 +67,14 @@ input wire A_BIST_CLK; + + + +- +-reg [P_DATA_WIDTH-1:0] memory [0:2**(P_ADDR_WIDTH)-1]; // memory +-reg [P_DATA_WIDTH-1:0] dr_r; +- +-wire [63:0] debug1, debug2, debug3; +-assign debug1 = memory[0]; +-assign debug2 = memory[2048]; +-assign debug3 = memory[3000]; ++// ++// reg [P_DATA_WIDTH-1:0] memory [0:2**(P_ADDR_WIDTH)-1]; // memory ++// reg [P_DATA_WIDTH-1:0] dr_r; ++// ++// wire [63:0] debug1, debug2, debug3; ++// assign debug1 = memory[0]; ++// assign debug2 = memory[2048]; ++// assign debug3 = memory[3000]; + + wire [P_ADDR_WIDTH-1:0] ADDR_MUX; + wire [P_DATA_WIDTH-1:0] DIN_MUX; +@@ -93,45 +93,102 @@ assign WEN_MUX =(A_BIST_EN==1'b1)? A_BIST_WEN :A_WEN; + assign REN_MUX =(A_BIST_EN==1'b1)? A_BIST_REN :A_REN; + assign CLK_MUX =(A_BIST_EN==1'b1)? A_BIST_CLK :A_CLK; + +-always @(posedge CLK_MUX) begin +- if(MEN_MUX==1'b1 && WEN_MUX==1'b1) begin +- memory[ADDR_MUX] <= (memory[ADDR_MUX] & ~BM_MUX) | (DIN_MUX & BM_MUX); +- if (REN_MUX==1'b1) begin +- dr_r<= (memory[ADDR_MUX] & ~BM_MUX) | (DIN_MUX & BM_MUX); +- end ++generate ++ if (P_ADDR_WIDTH == 6 && P_DATA_WIDTH == 64) begin : gen_fakeram_64x64 ++ fakeram_64x64_1rw i_fakeram ( ++ .rw0_clk (CLK_MUX), ++ .rw0_ce_in (MEN_MUX), ++ .rw0_addr_in (ADDR_MUX), ++ .rw0_we_in (WEN_MUX), ++ .rw0_wd_in (DIN_MUX), ++ .rw0_wmask_in (BM_MUX), ++ .rw0_rd_out (A_DOUT) ++ ); + end +- else if(MEN_MUX==1'b1 && REN_MUX==1'b1) begin +- dr_r<=memory[ADDR_MUX]; ++ else if (P_ADDR_WIDTH == 8 && P_DATA_WIDTH == 48) begin : gen_fakeram_48x256 ++ fakeram_48x256_1rw i_fakeram ( ++ .rw0_clk (CLK_MUX), ++ .rw0_ce_in (MEN_MUX), ++ .rw0_addr_in (ADDR_MUX), ++ .rw0_we_in (WEN_MUX), ++ .rw0_wd_in (DIN_MUX), ++ .rw0_wmask_in (BM_MUX), ++ .rw0_rd_out (A_DOUT) ++ ); + end +-end +- +-assign A_DOUT= dr_r; ++ else if (P_ADDR_WIDTH == 8 && P_DATA_WIDTH == 64) begin : gen_fakeram_64x256 ++ fakeram_64x256_1rw i_fakeram ( ++ .rw0_clk (CLK_MUX), ++ .rw0_ce_in (MEN_MUX), ++ .rw0_addr_in (ADDR_MUX), ++ .rw0_we_in (WEN_MUX), ++ .rw0_wd_in (DIN_MUX), ++ .rw0_wmask_in (BM_MUX), ++ .rw0_rd_out (A_DOUT) ++ ); ++ end ++ else if (P_ADDR_WIDTH == 9 && P_DATA_WIDTH == 64) begin : gen_fakeram_64x512 ++ fakeram_64x512_1rw i_fakeram ( ++ .rw0_clk (CLK_MUX), ++ .rw0_ce_in (MEN_MUX), ++ .rw0_addr_in (ADDR_MUX), ++ .rw0_we_in (WEN_MUX), ++ .rw0_wd_in (DIN_MUX), ++ .rw0_wmask_in (BM_MUX), ++ .rw0_rd_out (A_DOUT) ++ ); ++ end ++ else if (P_ADDR_WIDTH == 10 && P_DATA_WIDTH == 64) begin : gen_fakeram_64x1024 ++ fakeram_64x1024_1rw i_fakeram ( ++ .rw0_clk (CLK_MUX), ++ .rw0_ce_in (MEN_MUX), ++ .rw0_addr_in (ADDR_MUX), ++ .rw0_we_in (WEN_MUX), ++ .rw0_wd_in (DIN_MUX), ++ .rw0_wmask_in (BM_MUX), ++ .rw0_rd_out (A_DOUT) ++ ); ++ end ++ else if (P_ADDR_WIDTH == 11 && P_DATA_WIDTH == 64) begin : gen_fakeram_64x2048 ++ fakeram_64x2048_1rw i_fakeram ( ++ .rw0_clk (CLK_MUX), ++ .rw0_ce_in (MEN_MUX), ++ .rw0_addr_in (ADDR_MUX), ++ .rw0_we_in (WEN_MUX), ++ .rw0_wd_in (DIN_MUX), ++ .rw0_wmask_in (BM_MUX), ++ .rw0_rd_out (A_DOUT) ++ ); ++ end ++ else begin : gen_unsupported ++ initial begin ++ $error("SRAM_1P_behavioral_bm_bist: Unsupported configuration P_ADDR_WIDTH=%0d P_DATA_WIDTH=%0d", ++ P_ADDR_WIDTH, P_DATA_WIDTH); ++ $fatal(1, "Unsupported SRAM configuration, aborting simulation."); ++ end ++ end ++endgenerate + + + // The following code either initializes the memory values to a specified file or to all zeros to match hardware +- generate +- if (INIT_FILE != "") begin: use_init_file +- initial +- $readmemh(INIT_FILE, memory, 0, DEPTH-1); +- end else begin: init_bram_to_zero +- integer ram_index; +- initial +- for (ram_index = 0; ram_index < DEPTH; ram_index = ram_index + 1) +- memory[ram_index] = {P_DATA_WIDTH{1'b0}}; +- end +- endgenerate ++ // generate ++ // if (INIT_FILE != "") begin: use_init_file ++ // initial ++ // $readmemh(INIT_FILE, memory, 0, DEPTH-1); ++ // end else begin: init_bram_to_zero ++ // integer ram_index; ++ // initial ++ // for (ram_index = 0; ram_index < DEPTH; ram_index = ram_index + 1) ++ // memory[ram_index] = {P_DATA_WIDTH{1'b0}}; ++ // end ++ // endgenerate + + +-wire [63:0] debug200; +-wire [63:0] debug400; ++// ++// wire [63:0] debug200; ++// wire [63:0] debug400; + +-assign debug200 = memory[200]; +-assign debug400 = memory[400]; ++// assign debug200 = memory[200]; ++// assign debug400 = memory[400]; + + endmodule +- +- +- +- +- +- +diff --git a/rtl/define.v b/rtl/define.v +index 0899905..dc13459 100644 +--- a/rtl/define.v ++++ b/rtl/define.v +@@ -1,3 +1,4 @@ ++`default_nettype wire + `ifdef SIM //se sto simulando + `define POTENTIAL + //`define IEEG +@@ -35,3 +36,4 @@ + //`define UART_HP + `define LOW_POWER + `endif ++`define FUNCTIONAL +diff --git a/rtl/memorie_ihp/dual_port_ihp.v b/rtl/memorie_ihp/dual_port_ihp.v +index 74fccaf..5188c46 100755 +--- a/rtl/memorie_ihp/dual_port_ihp.v ++++ b/rtl/memorie_ihp/dual_port_ihp.v +@@ -49,6 +49,7 @@ reg [5:0] control; + reg [9:0] AD_0, AD_1; + wire [31:0] DO_0, DO_1; + ++wire en_0, ren0, wren0, en_1, ren1, wren1; + assign {en_0, ren0, wren0, en_1, ren1, wren1} = control; + + always@(*) begin +@@ -198,6 +199,7 @@ reg [9:0] AD_0, AD_1; + wire [31:0] DO_0, DO_1; + + ++wire en_0, ren0, wren0, en_1, ren1, wren1; + assign {en_0, ren0, wren0, en_1, ren1, wren1} = control; + + always@(*) begin +diff --git a/rtl/memorie_ihp/ihp_ram.v b/rtl/memorie_ihp/ihp_ram.v +index c3c909b..e98fd2e 100644 +--- a/rtl/memorie_ihp/ihp_ram.v ++++ b/rtl/memorie_ihp/ihp_ram.v +@@ -13,6 +13,8 @@ module ihp_ram # (parameter memfile="") + reg [7:0] B1, B2, B3, B4; + + ++ wire wea; ++ + assign wea = (|we); + //bitmask + always @(posedge clk) begin +diff --git a/rtl/memorie_ihp/single_port_ihp.v b/rtl/memorie_ihp/single_port_ihp.v +index e3888f7..9020fcc 100644 +--- a/rtl/memorie_ihp/single_port_ihp.v ++++ b/rtl/memorie_ihp/single_port_ihp.v +@@ -18,6 +18,9 @@ module ihp_single_port_256x48 #( + output [47:0] doutb + ); + ++wire MEN; ++wire WEN; ++wire REN; + + assign MEN = ena || enb ; + assign WEN = ena || wea ; +diff --git a/rtl/servant/accelerator_if.v b/rtl/servant/accelerator_if.v +index 602f9ef..4dea92e 100755 +--- a/rtl/servant/accelerator_if.v ++++ b/rtl/servant/accelerator_if.v +@@ -3,7 +3,7 @@ + `ifdef SIM + `include `CONFIG_PATH + `else +- `include "/home/luca/SYNtzulu_ihp/rtl/config/emg/config.txt" ++ `include "./config.txt" + `endif + + module accelerator_if #( +diff --git a/rtl/servant/service_ihp.v b/rtl/servant/service_ihp.v +index 21ce8ec..c2937b0 100755 +--- a/rtl/servant/service_ihp.v ++++ b/rtl/servant/service_ihp.v +@@ -3,7 +3,7 @@ + `ifdef SIM + `include `CONFIG_PATH + `else +- `include "/home/luca/SYNtzulu_ihp/rtl/config/emg/config.txt" ++ `include "./config.txt" + `endif + + module service_ihp #( +diff --git a/rtl/servant/service_ihp_chip.v b/rtl/servant/service_ihp_chip.v +index aba1007..6696ec0 100644 +--- a/rtl/servant/service_ihp_chip.v ++++ b/rtl/servant/service_ihp_chip.v +@@ -5,7 +5,7 @@ + `ifdef SIM + `include `CONFIG_PATH + `else +- `include "/home/luca/SYNtzulu_ihp/rtl/config/emg/config.txt" ++ `include "./config.txt" + `endif + + module service_ihp_chip +@@ -45,19 +45,31 @@ module service_ihp_chip + + wire o_txd_i; + +- sg13g2_IOPadIn pad_wb_clk (.pad(wb_clk), .p2c(wb_clk_i)); +- sg13g2_IOPadIn pad_wb_rst (.pad(wb_rst), .p2c(wb_rst_i)); +- sg13g2_IOPadIn pad_enb_debug (.pad(enb_debug), .p2c(enb_debug_i)); +- sg13g2_IOPadIn pad_timer_clk (.pad(timer_clk), .p2c(timer_clk_i)); ++ // sg13g2_IOPadIn pad_wb_clk (.pad(wb_clk), .p2c(wb_clk_i)); ++ // sg13g2_IOPadIn pad_wb_rst (.pad(wb_rst), .p2c(wb_rst_i)); ++ // sg13g2_IOPadIn pad_enb_debug (.pad(enb_debug), .p2c(enb_debug_i)); ++ // sg13g2_IOPadIn pad_timer_clk (.pad(timer_clk), .p2c(timer_clk_i)); + +- sg13g2_IOPadIn pad_i_flash_miso (.pad(i_flash_miso), .p2c(i_flash_miso_i)); +- sg13g2_IOPadOut16mA pad_o_flash_ss (.pad(o_flash_ss), .c2p(o_flash_ss_i)); +- sg13g2_IOPadOut16mA pad_o_flash_sck (.pad(o_flash_sck), .c2p(o_flash_sck_i)); +- sg13g2_IOPadOut16mA pad_o_flash_mosi (.pad(o_flash_mosi), .c2p(o_flash_mosi_i)); +- +- sg13g2_IOPadIn pad_buttons_0 (.pad(buttons[0]), .p2c(buttons_i[0])); +- sg13g2_IOPadIn pad_buttons_1 (.pad(buttons[1]), .p2c(buttons_i[1])); +- sg13g2_IOPadIn pad_buttons_2 (.pad(buttons[2]), .p2c(buttons_i[2])); ++ // sg13g2_IOPadIn pad_i_flash_miso (.pad(i_flash_miso), .p2c(i_flash_miso_i)); ++ // sg13g2_IOPadOut16mA pad_o_flash_ss (.pad(o_flash_ss), .c2p(o_flash_ss_i)); ++ // sg13g2_IOPadOut16mA pad_o_flash_sck (.pad(o_flash_sck), .c2p(o_flash_sck_i)); ++ // sg13g2_IOPadOut16mA pad_o_flash_mosi (.pad(o_flash_mosi), .c2p(o_flash_mosi_i)); ++ ++ // sg13g2_IOPadIn pad_buttons_0 (.pad(buttons[0]), .p2c(buttons_i[0])); ++ // sg13g2_IOPadIn pad_buttons_1 (.pad(buttons[1]), .p2c(buttons_i[1])); ++ // sg13g2_IOPadIn pad_buttons_2 (.pad(buttons[2]), .p2c(buttons_i[2])); ++ ++ assign wb_clk_i = wb_clk; ++ assign wb_rst_i = wb_rst; ++ assign enb_debug_i = enb_debug; ++ assign timer_clk_i = timer_clk; ++ assign i_flash_miso_i = i_flash_miso; ++ assign o_flash_ss = o_flash_ss_i; ++ assign o_flash_sck = o_flash_sck_i; ++ assign o_flash_mosi = o_flash_mosi_i; ++ assign buttons_i[0] = buttons[0]; ++ assign buttons_i[1] = buttons[1]; ++ assign buttons_i[2] = buttons[2]; + + //sg13g2_IOPadOut16mA pad_o_txd (.pad(o_txd), .c2p(o_txd_i)); + +diff --git a/rtl/servant/service_ihp_top.v b/rtl/servant/service_ihp_top.v +index 20c8137..fdf1b9c 100755 +--- a/rtl/servant/service_ihp_top.v ++++ b/rtl/servant/service_ihp_top.v +@@ -3,7 +3,7 @@ + `ifdef SIM + `include `CONFIG_PATH + `else +- `include "/home/luca/SYNtzulu_ihp/rtl/config/emg/config.txt" ++ `include "./config.txt" + `endif + + module service_ihp_top #( +diff --git a/rtl/syntzulu_ihp/Syntzulu.sv b/rtl/syntzulu_ihp/Syntzulu.sv +index 66b3dac..0a849ef 100755 +--- a/rtl/syntzulu_ihp/Syntzulu.sv ++++ b/rtl/syntzulu_ihp/Syntzulu.sv +@@ -19,7 +19,7 @@ + // + ////////////////////////////////////////////////////////////////////////////////// + +-`include "/home/luca/SYNtzulu_ihp/rtl/define.v" ++// `include "/home/luca/SYNtzulu_ihp/rtl/define.v" + + + module Syntzulu diff --git a/designs/src/SYNtzulA/dev/repo b/designs/src/SYNtzulA/dev/repo new file mode 160000 index 0000000..8c875bf --- /dev/null +++ b/designs/src/SYNtzulA/dev/repo @@ -0,0 +1 @@ +Subproject commit 8c875bfe2fbdd5113f54e8f0324e31d306d7fc70 diff --git a/designs/src/SYNtzulA/dev/setup.sh b/designs/src/SYNtzulA/dev/setup.sh new file mode 100644 index 0000000..ae29e55 --- /dev/null +++ b/designs/src/SYNtzulA/dev/setup.sh @@ -0,0 +1,122 @@ +#!/usr/bin/bash +# Using OpenROAD-flow-scripts/build_openroad.sh as a template + +set -eu + +DIR="$(dirname $(readlink -f $0))" +cd "$DIR" + + +INSTALL_PATH="$(pwd)" + + +PROC=-1 + +function usage() { + cat << EOF + +Usage: $0 [-h|--help] [-o|--local] [-t|--threads N] [--clean] [--clean-force] + +Options: + -h, --help Print this help message. + + -o, --local Build locally instead of building a Docker image. + + -t, --threads N Use N cpus when compiling software. + + --install-path PATH Path to install tools. Default is ${INSTALL_PATH}. + + --clean Call git clean interactively before compile. + Also removes any files native to SYNtzulA. + + --clean-force Call clean before compile. WARNING: this option + will not ask for confirmation. +EOF +} + +# Parse arguments +__CMD="$0 $@" +while (( "$#" )); do + case "$1" in + -h|--help) + usage 2> /dev/null + exit + ;; + -o|--local) + LOCAL_BUILD=1 + ;; + -t|--threads) + PROC="$2" + shift + ;; + --install-path) + INSTALL_PATH="$2" + shift + ;; + --clean) + CLEAN_BEFORE=1 + ;; + --clean-force) + CLEAN_BEFORE=1 + CLEAN_FORCE=1 + ;; + -*|--*) # unsupported flags + echo "[ERROR FLW-0005] Unsupported flag $1." >&2 + usage 2> /dev/null + exit 1 + ;; + esac + shift +done + +if [[ "$PROC" == "-1" ]]; then + if [[ "$OSTYPE" == "linux-gnu"* ]]; then + PROC=$(nproc --all) + elif [[ "$OSTYPE" == "darwin"* ]]; then + PROC=$(sysctl -n hw.ncpu) + else + cat << EOF +[WARNING FLW-0025] Unsupported OSTYPE: cannot determine number of host CPUs" +Defaulting to 2 threads. Use --threads N to use N threads" +EOF + PROC=2 + fi +fi + + +__cleanup() +{ + if [ ! -z "${CLEAN_FORCE+x}" ]; then + CLEAN_CMD="-x -d --force" + else + CLEAN_CMD="-x -d --interactive" + fi + echo "Cleaning up binaries and build files." + git clean ${CLEAN_CMD} tools + git submodule foreach --recursive git clean ${CLEAN_CMD} + rm sv2v +} + +if [ ! -z "${CLEAN_BEFORE+x}" ]; then + __cleanup +fi + +# Check if sv2v exists already (and set up if not) +if [ ! -f "./sv2v" ]; then + echo "A local sv2v installation doesn't exist. Cloning and building..." + rm -rf sv2v_main + git clone https://github.com/zachjs/sv2v.git sv2v_main + # Download haskell stack locally + curl -sSL https://get.haskellstack.org/ | sh -s - -d $(pwd)/sv2v_main + cd sv2v_main + # Change default STACK_ROOT dir from ~/.stack to the current dir + export STACK_ROOT=$(pwd)/sv2v_main + ./stack setup + ./stack build + cp "$(./stack path --local-install-root)/bin/sv2v" ../sv2v + cd .. + rm -rf sv2v_main + echo "Local sv2v build completed!" +else + echo "sv2v already present in directory" +fi diff --git a/designs/src/SYNtzulA/macros.v b/designs/src/SYNtzulA/macros.v new file mode 100644 index 0000000..13837ee --- /dev/null +++ b/designs/src/SYNtzulA/macros.v @@ -0,0 +1,201 @@ +//////////////////////////////////////////////////////////////////////// +// Macro wrappers for SRAM primitives (1RW with bit mask) +// Auto-generated — do not edit manually +//////////////////////////////////////////////////////////////////////// + +module fakeram_1rw_64x64 ( + clk, + en, + we, + wmask, + addr, + wdata, + rdata +); + parameter DATA_WIDTH = 64; + parameter SIZE = 64; + parameter ADDR_WIDTH = $clog2(SIZE); + + input clk; + input en; + input we; + input [DATA_WIDTH-1:0] wmask; + input [ADDR_WIDTH-1:0] addr; + input [DATA_WIDTH-1:0] wdata; + output reg [DATA_WIDTH-1:0] rdata; + + fakeram_1rw_64x64 fakeram_1rw_64x64_inst ( + .rw0_clk (clk), + .rw0_ce_in (en), + .rw0_we_in (we), + .rw0_wmask_in (wmask), + .rw0_addr_in (addr), + .rw0_wd_in (wdata), + .rw0_rd_out (rdata) + ); +endmodule + + +module fakeram_1rw_48x256 ( + clk, + en, + we, + wmask, + addr, + wdata, + rdata +); + parameter DATA_WIDTH = 48; + parameter SIZE = 256; + parameter ADDR_WIDTH = $clog2(SIZE); + + input clk; + input en; + input we; + input [DATA_WIDTH-1:0] wmask; + input [ADDR_WIDTH-1:0] addr; + input [DATA_WIDTH-1:0] wdata; + output reg [DATA_WIDTH-1:0] rdata; + + fakeram_1rw_48x256 fakeram_1rw_48x256_inst ( + .rw0_clk (clk), + .rw0_ce_in (en), + .rw0_we_in (we), + .rw0_wmask_in (wmask), + .rw0_addr_in (addr), + .rw0_wd_in (wdata), + .rw0_rd_out (rdata) + ); +endmodule + + +module fakeram_1rw_64x256 ( + clk, + en, + we, + wmask, + addr, + wdata, + rdata +); + parameter DATA_WIDTH = 64; + parameter SIZE = 256; + parameter ADDR_WIDTH = $clog2(SIZE); + + input clk; + input en; + input we; + input [DATA_WIDTH-1:0] wmask; + input [ADDR_WIDTH-1:0] addr; + input [DATA_WIDTH-1:0] wdata; + output reg [DATA_WIDTH-1:0] rdata; + + fakeram_1rw_64x256 fakeram_1rw_64x256_inst ( + .rw0_clk (clk), + .rw0_ce_in (en), + .rw0_we_in (we), + .rw0_wmask_in (wmask), + .rw0_addr_in (addr), + .rw0_wd_in (wdata), + .rw0_rd_out (rdata) + ); +endmodule + + +module fakeram_1rw_64x512 ( + clk, + en, + we, + wmask, + addr, + wdata, + rdata +); + parameter DATA_WIDTH = 64; + parameter SIZE = 512; + parameter ADDR_WIDTH = $clog2(SIZE); + + input clk; + input en; + input we; + input [DATA_WIDTH-1:0] wmask; + input [ADDR_WIDTH-1:0] addr; + input [DATA_WIDTH-1:0] wdata; + output reg [DATA_WIDTH-1:0] rdata; + + fakeram_1rw_64x512 fakeram_1rw_64x512_inst ( + .rw0_clk (clk), + .rw0_ce_in (en), + .rw0_we_in (we), + .rw0_wmask_in (wmask), + .rw0_addr_in (addr), + .rw0_wd_in (wdata), + .rw0_rd_out (rdata) + ); +endmodule + + +module fakeram_1rw_64x1024 ( + clk, + en, + we, + wmask, + addr, + wdata, + rdata +); + parameter DATA_WIDTH = 64; + parameter SIZE = 1024; + parameter ADDR_WIDTH = $clog2(SIZE); + + input clk; + input en; + input we; + input [DATA_WIDTH-1:0] wmask; + input [ADDR_WIDTH-1:0] addr; + input [DATA_WIDTH-1:0] wdata; + output reg [DATA_WIDTH-1:0] rdata; + + fakeram_1rw_64x1024 fakeram_1rw_64x1024_inst ( + .rw0_clk (clk), + .rw0_ce_in (en), + .rw0_we_in (we), + .rw0_wmask_in (wmask), + .rw0_addr_in (addr), + .rw0_wd_in (wdata), + .rw0_rd_out (rdata) + ); +endmodule + + +module fakeram_1rw_64x2048 ( + clk, + en, + we, + wmask, + addr, + wdata, + rdata +); + parameter DATA_WIDTH = 64; + parameter SIZE = 2048; + parameter ADDR_WIDTH = $clog2(SIZE); + + input clk; + input en; + input we; + input [DATA_WIDTH-1:0] wmask; + input [ADDR_WIDTH-1:0] addr; + input [DATA_WIDTH-1:0] wdata; + output reg [DATA_WIDTH-1:0] rdata; + + fakeram_1rw_64x2048 fakeram_1rw_64x2048_inst ( + .rw0_clk (clk), + .rw0_ce_in (en), + .rw0_we_in (we), + .rw0_wmask_in (wmask), + .rw0_addr_in (addr), + .rw0_wd_in (wdata), + .rw0_rd_out (rdata) + ); +endmodule diff --git a/designs/src/SYNtzulA/verilog.mk b/designs/src/SYNtzulA/verilog.mk new file mode 100644 index 0000000..cc218d2 --- /dev/null +++ b/designs/src/SYNtzulA/verilog.mk @@ -0,0 +1,61 @@ +export ADDITIONAL_LEFS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_64x64_1rw.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_48x256_1rw.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_64x256_1rw.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_64x512_1rw.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_64x1024_1rw.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_64x2048_1rw.lef + +export ADDITIONAL_LIBS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_64x64_1rw.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_48x256_1rw.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_64x256_1rw.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_64x512_1rw.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_64x1024_1rw.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_64x2048_1rw.lib + +SYNSNN_SRC_DIR := $(BENCH_DESIGN_HOME)/src/$(DESIGN_NICKNAME) +SYNSNN_TOP_V := $(SYNSNN_SRC_DIR)/SYNtzulATop.v + +ifneq ($(wildcard $(DEV_FLAG)),) + +SYNSNN_DEV_DIR := $(SYNSNN_SRC_DIR)/dev + +SYNSNN_REPO_RTL_DIR = $(SYNSNN_DEV_DIR)/repo/rtl + +SYNSNN_ALL_REPO_FILES = $(shell find $(SYNSNN_REPO_RTL_DIR) -mindepth 2 -maxdepth 2 -type f \ + -not -name "*.rej") \ + $(SYNSNN_REPO_RTL_DIR)/define.v + +SYNSNN_REPO_INCLUDE_FILES := $(SYNSNN_REPO_RTL_DIR)/define.v + +SYNSNN_REPO_SV_FILES = $(filter-out \ + $(wildcard $(SYNSNN_REPO_RTL_DIR)/*/*.v) \ + $(wildcard $(SYNSNN_REPO_RTL_DIR)/*.v) \ + $(SYNSNN_REPO_INCLUDE_FILES), \ + $(SYNSNN_ALL_REPO_FILES)) + +SYNSNN_REPO_V_FILES = $(filter-out \ + $(wildcard $(SYNSNN_REPO_RTL_DIR)/*/*.sv) \ + $(wildcard $(SYNSNN_REPO_RTL_DIR)/*.sv) \ + $(SYNSNN_REPO_INCLUDE_FILES), \ + $(SYNSNN_ALL_REPO_FILES)) + +$(SYNSNN_TOP_V): $(SYNSNN_ALL_REPO_FILES) + @bash $(SYNSNN_DEV_DIR)/setup.sh + patch -p1 -N --directory=$(SYNSNN_DEV_DIR)/repo \ + < $(SYNSNN_DEV_DIR)/patch-synsnn.patch; \ + RET=$$?; [ $$RET -eq 0 ] || [ $$RET -eq 1 ] + cat $(SYNSNN_REPO_INCLUDE_FILES) > $(SYNSNN_TOP_V) + $(SYNSNN_DEV_DIR)/sv2v -w stdout \ + -I $(SYNSNN_REPO_RTL_DIR) \ + $(SYNSNN_REPO_SV_FILES) \ + >> $(SYNSNN_TOP_V) + cat $(SYNSNN_REPO_V_FILES) >> $(SYNSNN_TOP_V) + +export VERILOG_FILES = $(SYNSNN_TOP_V) \ + $(SYNSNN_SRC_DIR)/macros.v + +else +export VERILOG_FILES = $(SYNSNN_TOP_V) \ + $(SYNSNN_SRC_DIR)/macros.v + +endif From b5272551c05c18c22eb04f561df4165dbbc50a35 Mon Sep 17 00:00:00 2001 From: Paolo Pedroso <108847100+paolopedroso@users.noreply.github.com> Date: Mon, 30 Mar 2026 17:16:09 -0700 Subject: [PATCH 2/2] fix license --- designs/src/SYNtzulA/LICENSE | 21 +++++++++++++++++++++ designs/src/SYNtzulA/dev/setup.sh | 18 +++++++++++++----- 2 files changed, 34 insertions(+), 5 deletions(-) create mode 100644 designs/src/SYNtzulA/LICENSE diff --git a/designs/src/SYNtzulA/LICENSE b/designs/src/SYNtzulA/LICENSE new file mode 100644 index 0000000..9b0fe4d --- /dev/null +++ b/designs/src/SYNtzulA/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2025 EOLAB-2025 + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/designs/src/SYNtzulA/dev/setup.sh b/designs/src/SYNtzulA/dev/setup.sh index ae29e55..f5365e2 100644 --- a/designs/src/SYNtzulA/dev/setup.sh +++ b/designs/src/SYNtzulA/dev/setup.sh @@ -3,12 +3,10 @@ set -eu -DIR="$(dirname $(readlink -f $0))" -cd "$DIR" - - -INSTALL_PATH="$(pwd)" +SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +cd "$SCRIPT_DIR" +INSTALL_PATH="$SCRIPT_DIR" PROC=-1 @@ -120,3 +118,13 @@ if [ ! -f "./sv2v" ]; then else echo "sv2v already present in directory" fi + +REPO_LICENSE="$SCRIPT_DIR/LICENSE" +PARENT_LICENSE="$SCRIPT_DIR/../LICENSE" + +if [ -f "$REPO_LICENSE" ]; then + echo "Copying $REPO_LICENSE -> $PARENT_LICENSE" + cp -u "$REPO_LICENSE" "$PARENT_LICENSE" +else + echo "Source LICENSE not found in dev directory" +fi \ No newline at end of file