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title Sky130 PDK
nav_order 1
parent Technologies

Google/Skywater 130 nm Open-Source PDK

Sky130 is a fully open, manufacturable 130 nm CMOS process design kit (PDK). It was opened by Google and SkyWater Technology in 2020, and since then has been the workhorse technology for every chipforge-style multi-project wafer (MPW) run aimed at the open-source silicon community. If you are reading this repo, you will almost certainly tape out in Sky130.

Primary references:

Why Sky130 matters

Every commercial PDK before 2020 was locked behind a non-disclosure agreement. If you wanted to design a real chip, you had to first sign an NDA with the foundry, which made open-source EDA tools, academic reproducibility, and hobbyist tape-outs essentially impossible. Sky130 broke that wall:

  • The entire PDK — transistor models, DRC rules, LVS decks, standard cell libraries, I/O cells, SRAM macros — is licensed under Apache 2.0 and lives on GitHub.
  • Multi-project wafer runs (MPW 1 through 8+) were funded so that anyone in the community could tape out a chip at no cost.
  • Open-source flows (OpenLane, OpenROAD, Magic, KLayout, Netgen, Xschem, Xyce, Ngspice) could finally target a real process, which drove a generation of tool maturation.

Installing the PDK

The supported way to get Sky130 locally is with ciel, which downloads a prebuilt, open_pdks-processed snapshot of the PDK:

pip install ciel
ciel enable --pdk sky130 7b70722e33c03fcb5dabcf4d479fb0822d9251c9

This installs two variants to ~/.ciel/:

~/.ciel/
├── ciel/                  # ciel's own bookkeeping
├── sky130A/               # the "A" variant
└── sky130B/               # the "B" variant

You will almost always use sky130A for coursework and open MPW runs. sky130B exists to support one specific device family (SONOS flash memories) and is otherwise identical to sky130A.

Each variant has the same top-level layout:

sky130A/
├── SOURCES                # provenance: open_pdks + commit hash
├── libs.tech/             # tool-specific files (one directory per tool)
└── libs.ref/              # the actual circuit IP libraries

Point your flows at $PDK_ROOT=~/.ciel and $PDK=sky130A.

libs.tech/: tool configurations

libs.tech/ contains per-tool technology files. Everything a specific EDA tool needs to know about the process lives in its own subdirectory:

Directory Tool Key files
ngspice Ngspice SPICE simulator sky130.lib.spice, corners/, r+c/
magic Magic VLSI sky130A.tech, DRC/density scripts
klayout KLayout tech/, drc/, lvs/, macros/
netgen Netgen LVS sky130A_setup.tcl
xschem Xschem schematic capture symbol libraries
openlane OpenLane flow per-library configs
qflow, irsim, xcircuit legacy tools setup files

The two you will touch most are libs.tech/ngspice/sky130.lib.spice (the corner selector for SPICE; see Spice Syntax) and libs.tech/klayout/drc/ (the rule decks for sign-off DRC; see KLayout DRC).

libs.ref/: the circuit IP libraries

libs.ref/ is where the actual circuits live. Sky130 ships six libraries:

Library Contents
sky130_fd_pr Primitive devices — transistors, resistors, capacitors, diodes, inductors, BJTs. The "technology" in the literal sense.
sky130_fd_sc_hd High-density standard cells. 437 cells. This is what digital synthesis targets.
sky130_fd_sc_hvl High-voltage level-shifter cells (for 1.8 V ↔ 3.3 V / 5 V interfaces).
sky130_fd_io I/O pad cells (ESD, power, signal pads, analog pass-through).
sky130_sram_macros Pre-laid-out SRAM blocks of common sizes.
sky130_ml_xx_hd Machine-learning-optimized standard cell variant (experimental).

The fd in every name stands for foundry, indicating that SkyWater itself (not a third party) provides these. The final suffix (hd, hvl, pr, io) indicates the library purpose.

Naming convention

Every cell and device in Sky130 follows this pattern:

sky130_<provider>_<library>__<cell_name>

Note the double underscore separating library from cell name — this is intentional and tools parse it. Examples:

  • sky130_fd_sc_hd__inv_1 — size-1 inverter from the HD standard cells
  • sky130_fd_pr__nfet_01v8 — 1.8 V nominal NMOS primitive
  • sky130_fd_pr__nfet_01v8_lvt — low-V_T 1.8 V NMOS
  • sky130_fd_io__top_power_hvc_wpad — a power pad with wire-bond pad

Views

Each library in libs.ref/ ships the same circuit in multiple views, one per abstraction level or downstream consumer:

View directory What it is Consumers
gds/ Mask-level layout (binary GDSII) Foundry, DRC, LVS, streaming
lef/ Abstract layout (pin locations + blockage) Placement, routing
techlef/ Metal stack / DRC-lite for routers OpenROAD, placement
lib/ Liberty timing + power models (per PVT) STA, synthesis
spice/ Transistor-level SPICE netlist Analog sim, LVS
cdl/ Cadence Design Language netlist (for LVS) LVS
verilog/ Behavioral + switch-level Verilog RTL simulation, gate sim
mag/ Magic layout (full detail) Magic
maglef/ Magic abstract layout Magic (P&R-style flows)

If you are doing digital flows, you primarily consume lef/ + lib/ + verilog/. If you are doing analog, it's spice/ + gds/ + mag/. If you are doing sign-off, it's gds/ + cdl/.

Device primitives (sky130_fd_pr)

sky130_fd_pr is the most important library to understand because every other IP in the PDK is ultimately built out of it. The primitive families:

Core MOSFETs (1.8 V)

These are the workhorses for digital logic and low-voltage analog:

Device V_T flavor Notes
sky130_fd_pr__nfet_01v8 Regular Default NMOS, V_TH ≈ 0.49 V
sky130_fd_pr__nfet_01v8_lvt Low-V_T Faster, leakier
sky130_fd_pr__pfet_01v8 Regular Default PMOS
sky130_fd_pr__pfet_01v8_hvt High-V_T Slower, less leaky; used heavily in the HD std cell library
sky130_fd_pr__pfet_01v8_lvt Low-V_T Faster, leakier
sky130_fd_pr__pfet_01v8_mvt Medium-V_T Middle ground

High-voltage MOSFETs

Used for I/O, analog, power management. The number encodes gate-voltage / drain-voltage:

Device V_GS max V_DS max Use
sky130_fd_pr__nfet_03v3_nvt 3.3 V 3.3 V Native-V_T for analog
sky130_fd_pr__nfet_05v0_nvt 5.0 V 5.0 V Native-V_T 5 V analog
sky130_fd_pr__nfet_g5v0d10v5 5.0 V 10.5 V Drain-extended 5 V I/O
sky130_fd_pr__nfet_g5v0d16v0 5.0 V 16 V High-voltage DEMOS
sky130_fd_pr__nfet_20v0* 5.0 V 20 V LDMOS for power

Passives

  • Resistors: res_generic_pd/res_generic_nd (diffusion), res_high_po, res_xhigh_po (poly of various sheet-resistance flavors), res_iso_pw (isolated P-well).
  • MIM capacitors: cap_mim_m3_1, cap_mim_m3_2 — metal-insulator-metal between metal 3 and the cap-top layer.
  • Varactors: cap_var_lvt, cap_var_hvt — MOS varactors for VCOs / PLLs.
  • VPP (vertical parallel plate) capacitors: cap_vpp_* — a large family of fingered metal stacks with different shapes, shields, and floor-plan footprints. The name encodes the dimensions and which metals are used.
  • Inductors: ind_03_90, ind_05_125, ind_05_220 — a handful of pre-characterized spiral inductors.
  • BJTs: npn_05v5, pnp_05v5 — bipolar devices for bandgaps and analog references.
  • Diodes: diode_pd2nw_05v5, diode_pw2nd_11v0, etc.

ESD and RF variants

esd_* devices are characterized for electrostatic-discharge events. rf_* devices carry S-parameter and noise data for small-signal RF simulation. Use these in I/O design and anything above a few GHz; for regular analog you want the plain nfet_01v8 / pfet_01v8.

Device models (SPICE)

Every device ships as a BSIM4 (level=54) model binned across W/L, with separate corner files for tt/ss/ff/sf/fs/leak/wafer and Monte Carlo mismatch terms built in. For a deep dive on the model structure, see Spice Device Models.

Standard cells (sky130_fd_sc_hd)

The high-density standard cell library is what yosys + OpenROAD targets for digital synthesis and place-and-route. 437 cells covering the usual surface area: inverters, NAND/NOR (2- through 4-input), AOI/OAI complex gates, flip-flops with assorted reset/preset/scan variants, latches, buffers, tie cells, fill cells, decaps, and clock gating cells.

Every cell has drive-strength variants encoded as a trailing integer: _1, _2, _4, _8, ... A larger number means wider transistors and higher drive. sky130_fd_sc_hd__inv_1 is the smallest inverter; inv_16 drives 16× more load at 16× the area.

Cell height is fixed at 2.72 µm (7 metal-1 tracks). This is a constraint of the library, not the process — the hvl library has a different row height.

Metal stack

Sky130 has 5 routing metals plus a local-interconnect layer:

                        (top, thickest, cheapest R)
       met5   ──────────  1.6 µm thick, ~0.47 Ω/sq
       via4
       met4
       via3
       met3
       via2
       met2
       via
       met1
       mcon
       li1     ──────────  local interconnect (NOT a routing metal for
                           general digital; used inside std cells)
       licon
       (poly + diff + wells)
                        (bottom)

Key conventions:

  • li1 (local interconnect, colored khaki/olive in the standard palette) sits below metal 1. It is low-resistance poly, used inside standard cells for local connections. OpenROAD does not use li1 as a routing layer by default.
  • Cuts/vias: licon (poly/diff to li1), mcon (li1 to met1), via (met1 to met2), via2, via3, via4.
  • Preferred routing directions alternate: met1 horizontal, met2 vertical, met3 horizontal, met4 vertical, met5 horizontal.
  • met5 is thick and meant for power straps, clock trunks, and long global routes. Do not waste met5 on short signals.

For full design rules: https://skywater-pdk.readthedocs.io/en/main/rules/periphery.html.

For the authoritative layer list and GDS numbers: https://skywater-pdk.readthedocs.io/en/main/rules/layers.html.

Corners

Sky130 ships seven process corners in libs.tech/ngspice/corners/:

Corner Meaning When you use it
tt Typical NMOS, typical PMOS Nominal design center
ss Slow NMOS, slow PMOS Setup (worst-case) timing
ff Fast NMOS, fast PMOS Hold timing, max-power analysis
sf Slow NMOS, fast PMOS PMOS-dominated path corners
fs Fast NMOS, slow PMOS NMOS-dominated path corners
leak Worst-case leakage Static power / sleep analysis
wafer Wafer-level device variation Statistical yield studies

Each corner is a .lib block inside sky130.lib.spice. You select one in your testbench with, e.g., .lib "$PDK_ROOT/sky130A/libs.tech/ngspice/sky130.lib.spice" tt.

For signing off digital timing across corners — reading ss/ff/tt Liberty views in one STA session and reporting per-corner — see Multi-Corner Timing Analysis (note: that tutorial's "mc" stands for multi-corner, not Monte Carlo). For transistor-level Monte Carlo mismatch, the machinery is the MC_MM_SWITCH parameter and AGAUSS(...) terms wired into every BSIM4 card; see Spice Device Models.

Standard cell timing views (.lib)

Sky130 ships 18 Liberty files for the HD standard cell library, covering the cross-product of corner × temperature × voltage:

  • Corners: ss, tt, ff
  • Temperatures: -40 °C, 25 °C, 100 °C
  • Voltages: 1v28, 1v35, 1v40, 1v44, 1v56, 1v60, 1v65, 1v76, 1v80, 1v95

For example, sky130_fd_sc_hd__ss_n40C_1v60.lib is slow-slow at −40 °C, V_DD = 1.60 V. Pick the .lib that matches each corner you care about when you set up multi-corner STA.

A few of the .lib files are _ccsnoise variants, which carry Composite-Current-Source noise data for more accurate noise-aware timing.

SRAM macros (sky130_sram_macros)

The sky130_sram_macros library bundles a handful of pre-laid-out, pre-characterized SRAM blocks of common shapes (e.g. 1 kB, 2 kB, 4 kB single- and dual-port). These are generated by OpenRAM, the UCSC open-source memory compiler. If you need a size that isn't in the shipping set, you generate a fresh one with OpenRAM rather than hand-laying it out.

sky130A vs sky130B

You will see both directories after ciel enable. They are mostly the same process; the difference is:

  • sky130A — the "A" variant, without the SONOS flash option. 99% of academic work and MPW tape-outs target sky130A.
  • sky130B — the "B" variant adds SONOS (silicon-oxide-nitride-oxide-silicon) non-volatile memory cells. If you need embedded flash, use sky130B. Otherwise ignore it.

The two variants are DRC-compatible; you cannot mix them in a single chip, but you do not need to re-port designs between them unless you add or remove SONOS.

Related tutorials

Rather than duplicating content, these other tutorials cover Sky130-specific detail:

Historical FOSSi Dial-Up talks

The 2020–2021 FOSSi Dial-Up video series is still the best oral history of how Sky130 came to exist: