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Add AD936x frequency hopping example
Signed-off-by: Travis Collins <travis.collins@analog.com>
1 parent 49e7094 commit 28c1b14

37 files changed

+2082
-12
lines changed

‎.gitlab-ci.yml‎

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Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ build:master:
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- matlab
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stage: build
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script:
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- export HDLBRANCH=master
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- export HDLBRANCH=hdl_2018_r2
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- export MLRELEASE=R2018b
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- ./CI/scripts/dockermake build
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- export HDLBRANCH=
@@ -82,17 +82,35 @@ test_installer:2018_R1_Installer:
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reports:
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junit: test/BSPTestResults.xml
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# Test weekly fully sythesized design
86-
test:Synthesize:
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when: manual
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# Test HWA no install
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test:2018_R1:
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tags:
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- vivado
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- matlab
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stage: test
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dependencies:
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- build:2018_R1
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script:
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- ./CI/scripts/dockermake test
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- ./CI/scripts/dockermake zip
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artifacts:
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when: always
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paths:
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- zip/
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- test/logs/
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reports:
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junit: test/BSPTestResults.xml
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# Test targeting demos (no hardware)
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test:targeting_demos:
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tags:
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- matlab
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- vivado
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stage: test
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dependencies:
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- build:2018_R1
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script:
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- ./CI/scripts/dockermake test_synth
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- ./CI/scripts/dockermake test_targeting_demos
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artifacts:
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when: always
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name: "$CI_COMMIT_REF_NAME"

‎CI/projects/adrv9361z7035/common/config_rx.tcl‎

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -16,9 +16,11 @@ connect_bd_net [get_bd_pins util_ad9361_adc_pack/adc_valid_0] [get_bd_pins util_
1616

1717
global dma_config
1818
# Configure DMA
19-
if {$dma_config eq "Packetized"} {
20-
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64} CONFIG.DMA_DATA_WIDTH_DEST {256} CONFIG.SYNC_TRANSFER_START {false} CONFIG.DMA_AXI_PROTOCOL_DEST {0} CONFIG.DMA_TYPE_SRC {1} CONFIG.MAX_BYTES_PER_BURST {32768}] [get_bd_cells axi_ad9361_adc_dma]
21-
connect_bd_net [get_bd_pins axi_ad9361_adc_dma/s_axis_aclk] [get_bd_pins util_ad9361_divclk/clk_out]
22-
connect_bd_net [get_bd_pins util_ad9361_adc_pack/adc_data] [get_bd_pins axi_ad9361_adc_dma/s_axis_data]
23-
connect_bd_net [get_bd_pins axi_ad9361_adc_dma/s_axis_valid] [get_bd_pins util_ad9361_adc_pack/adc_valid]
24-
}
19+
if {[info exists dma_config]} {
20+
if {$dma_config eq "Packetized"} {
21+
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64} CONFIG.DMA_DATA_WIDTH_DEST {256} CONFIG.SYNC_TRANSFER_START {false} CONFIG.DMA_AXI_PROTOCOL_DEST {0} CONFIG.DMA_TYPE_SRC {1} CONFIG.MAX_BYTES_PER_BURST {32768}] [get_bd_cells axi_ad9361_adc_dma]
22+
connect_bd_net [get_bd_pins axi_ad9361_adc_dma/s_axis_aclk] [get_bd_pins util_ad9361_divclk/clk_out]
23+
connect_bd_net [get_bd_pins util_ad9361_adc_pack/adc_data] [get_bd_pins axi_ad9361_adc_dma/s_axis_data]
24+
connect_bd_net [get_bd_pins axi_ad9361_adc_dma/s_axis_valid] [get_bd_pins util_ad9361_adc_pack/adc_valid]
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}
26+
}

‎CI/scripts/Docker‎

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@@ -1,8 +1,10 @@
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FROM ubuntu:16.04
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MAINTAINER Travis Collins <travis.collins@analog.com>
4-
RUN apt update
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RUN DEBIAN_FRONTEND=noninteractive apt update
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RUN DEBIAN_FRONTEND=noninteractive apt-get install -y libpng-dev libfreetype6-dev libblas-dev liblapack-dev gfortran build-essential xorg
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RUN DEBIAN_FRONTEND=noninteractive apt-get install -y openjdk-8-jre openjdk-8-jdk libgtk2.0-0 libxss1 libxt6 zip unzip curl wget tar git xvfb
7+
RUN DEBIAN_FRONTEND=noninteractive apt-get install -y fakeroot libncurses5-dev libssl-dev ccache dfu-util u-boot-tools device-tree-compiler
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RUN DEBIAN_FRONTEND=noninteractive apt-get install -y libssl-dev mtools bc python cpio zip unzip rsync file wget
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RUN DEBIAN_FRONTEND=noninteractive dpkg --add-architecture i386
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RUN DEBIAN_FRONTEND=noninteractive apt-get install -y lib32stdc++6

‎CI/scripts/Makefile‎

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@@ -97,6 +97,9 @@ test_modem:
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test_synth:
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bash synth_designs.sh
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test_targeting_demos:
101+
bash targeting_designs.sh
102+
100103
gen_tlbx:
101104
${MLPATH}/$(MLRELEASE)/bin/matlab $(MLFLAGS) -r "genTlbx;exit();"
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‎CI/scripts/targeting_designs.sh‎

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1+
#!/bin/bash
2+
3+
MLFLAGS="-nodisplay -nodesktop -nosplash"
4+
5+
if [ -z "$MLRELEASE" ]
6+
then
7+
MLRELEASE=R2018b
8+
fi
9+
10+
MLPATH=/usr/local/MATLAB
11+
12+
cd ../..
13+
source /opt/Xilinx/Vivado/2017.4/settings64.sh
14+
Xvfb :77 &
15+
export DISPLAY=:77
16+
export SWT_GTK3=0
17+
source /opt/Xilinx/Vivado/2017.4/settings64.sh
18+
$MLPATH/$MLRELEASE/bin/matlab $MLFLAGS -r "addpath(genpath('test'));addpath(genpath('deps'));runDemoTests;"
19+
kill -9 `pidof Xvfb`

‎targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/add_rx_tx_io.m‎

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1+
function add_rx_tx_io(hRD)
2+
3+
% add AXI4 and AXI4-Lite slave interfaces
4+
hRD.addAXI4SlaveInterface( ...
5+
'InterfaceConnection', 'axi_cpu_interconnect/M11_AXI', ...
6+
'BaseAddress', '0x43C00000', ...
7+
'MasterAddressSpace', 'sys_ps7/Data');
8+
9+
% % AGC control input for transceiver
10+
% hRD.addInternalIOInterface( ...
11+
% 'InterfaceID', 'Enable AGC', ...
12+
% 'InterfaceType', 'OUT', ...
13+
% 'PortName', 'en_agc', ...
14+
% 'PortWidth', 1, ...
15+
% 'InterfaceConnection', 'gpio_en_agc', ...
16+
% 'IsRequired', false);
17+
18+
% GPIO status output for transceiver
19+
hRD.addInternalIOInterface( ...
20+
'InterfaceID', 'CTRL_STATUS', ...
21+
'InterfaceType', 'IN', ...
22+
'PortName', 'gpio_status', ...
23+
'PortWidth', 8, ...
24+
'InterfaceConnection', 'gpio_status', ...
25+
'IsRequired', false);
26+
27+
% GPIO Control input for transceiver
28+
hRD.addInternalIOInterface( ...
29+
'InterfaceID', 'AD9361 CTRL IN', ...
30+
'InterfaceType', 'OUT', ...
31+
'PortName', 'gpio_ctl', ...
32+
'PortWidth', 4, ...
33+
'InterfaceConnection', 'gpio_ctl', ...
34+
'IsRequired', false);
35+
36+
% DMA Ready signal
37+
hRD.addInternalIOInterface( ...
38+
'InterfaceID', 'DMA Ready', ...
39+
'InterfaceType', 'IN', ...
40+
'PortName', 'dma_rdy', ...
41+
'PortWidth', 1, ...
42+
'InterfaceConnection', 'axi_ad9361_adc_dma/s_axis_ready', ...
43+
'IsRequired', false);
44+
45+
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
46+
% Rx Reference design interfaces
47+
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
48+
hRD.addInternalIOInterface( ...
49+
'InterfaceID', 'IP Data Valid OUT', ...
50+
'InterfaceType', 'OUT', ...
51+
'PortName', 'dut_data_valid', ...
52+
'PortWidth', 1, ...
53+
'InterfaceConnection', 'util_ad9361_adc_pack/adc_valid_0', ...
54+
'IsRequired', false);
55+
56+
hRD.addInternalIOInterface( ...
57+
'InterfaceID', 'IP Data 0 OUT', ...
58+
'InterfaceType', 'OUT', ...
59+
'PortName', 'dut_data_0', ...
60+
'PortWidth', 16, ...
61+
'InterfaceConnection', 'util_ad9361_adc_pack/adc_data_0', ...
62+
'IsRequired', false);
63+
64+
hRD.addInternalIOInterface( ...
65+
'InterfaceID', 'IP Data 1 OUT', ...
66+
'InterfaceType', 'OUT', ...
67+
'PortName', 'dut_data_1', ...
68+
'PortWidth', 16, ...
69+
'InterfaceConnection', 'util_ad9361_adc_pack/adc_data_1', ...
70+
'IsRequired', false);
71+
72+
hRD.addInternalIOInterface( ...
73+
'InterfaceID', 'IP Data 2 OUT', ...
74+
'InterfaceType', 'OUT', ...
75+
'PortName', 'dut_data_2', ...
76+
'PortWidth', 16, ...
77+
'InterfaceConnection', 'util_ad9361_adc_pack/adc_data_2', ...
78+
'IsRequired', false);
79+
80+
hRD.addInternalIOInterface( ...
81+
'InterfaceID', 'IP Data 3 OUT', ...
82+
'InterfaceType', 'OUT', ...
83+
'PortName', 'dut_data_3', ...
84+
'PortWidth', 16, ...
85+
'InterfaceConnection', 'util_ad9361_adc_pack/adc_data_3', ...
86+
'IsRequired', false);
87+
88+
hRD.addInternalIOInterface( ...
89+
'InterfaceID', 'AD9361 ADC Data I0', ...
90+
'InterfaceType', 'IN', ...
91+
'PortName', 'sys_wfifo_0_dma_wdata', ...
92+
'PortWidth', 16, ...
93+
'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_0', ...
94+
'IsRequired', false);
95+
96+
hRD.addInternalIOInterface( ...
97+
'InterfaceID', 'AD9361 ADC Data Q0', ...
98+
'InterfaceType', 'IN', ...
99+
'PortName', 'sys_wfifo_1_dma_wdata', ...
100+
'PortWidth', 16, ...
101+
'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_1', ...
102+
'IsRequired', false);
103+
104+
hRD.addInternalIOInterface( ...
105+
'InterfaceID', 'AD9361 ADC Data I1', ...
106+
'InterfaceType', 'IN', ...
107+
'PortName', 'sys_wfifo_2_dma_wdata', ...
108+
'PortWidth', 16, ...
109+
'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_2', ...
110+
'IsRequired', false);
111+
112+
hRD.addInternalIOInterface( ...
113+
'InterfaceID', 'AD9361 ADC Data Q1', ...
114+
'InterfaceType', 'IN', ...
115+
'PortName', 'sys_wfifo_3_dma_wdata', ...
116+
'PortWidth', 16, ...
117+
'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_3', ...
118+
'IsRequired', false);
119+
120+
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
121+
% Tx Reference design interfaces
122+
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
123+
hRD.addInternalIOInterface( ...
124+
'InterfaceID', 'AD9361 DAC Data I0', ...
125+
'InterfaceType', 'OUT', ...
126+
'PortName', 'axi_ad9361_dac_data_i0', ...
127+
'PortWidth', 16, ...
128+
'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_0', ...
129+
'IsRequired', false);
130+
131+
hRD.addInternalIOInterface( ...
132+
'InterfaceID', 'AD9361 DAC Data Q0', ...
133+
'InterfaceType', 'OUT', ...
134+
'PortName', 'axi_ad9361_dac_data_q0', ...
135+
'PortWidth', 16, ...
136+
'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_1', ...
137+
'IsRequired', false);
138+
139+
hRD.addInternalIOInterface( ...
140+
'InterfaceID', 'AD9361 DAC Data I1', ...
141+
'InterfaceType', 'OUT', ...
142+
'PortName', 'axi_ad9361_dac_data_i1', ...
143+
'PortWidth', 16, ...
144+
'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_2', ...
145+
'IsRequired', false);
146+
147+
hRD.addInternalIOInterface( ...
148+
'InterfaceID', 'AD9361 DAC Data Q1', ...
149+
'InterfaceType', 'OUT', ...
150+
'PortName', 'axi_ad9361_dac_data_q1', ...
151+
'PortWidth', 16, ...
152+
'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_3', ...
153+
'IsRequired', false);
154+
155+
hRD.addInternalIOInterface( ...
156+
'InterfaceID', 'IP Data 0 IN', ...
157+
'InterfaceType', 'IN', ...
158+
'PortName', 'util_dac_unpack_dac_data_00', ...
159+
'PortWidth', 16, ...
160+
'InterfaceConnection', 'util_ad9361_dac_upack/dac_data_0', ...
161+
'IsRequired', false);
162+
163+
hRD.addInternalIOInterface( ...
164+
'InterfaceID', 'IP Data 1 IN', ...
165+
'InterfaceType', 'IN', ...
166+
'PortName', 'util_dac_unpack_dac_data_01', ...
167+
'PortWidth', 16, ...
168+
'InterfaceConnection', 'util_ad9361_dac_upack/dac_data_1', ...
169+
'IsRequired', false);
170+
171+
hRD.addInternalIOInterface( ...
172+
'InterfaceID', 'IP Data 2 IN', ...
173+
'InterfaceType', 'IN', ...
174+
'PortName', 'util_dac_unpack_dac_data_02', ...
175+
'PortWidth', 16, ...
176+
'InterfaceConnection', 'util_ad9361_dac_upack/dac_data_2', ...
177+
'IsRequired', false);
178+
179+
hRD.addInternalIOInterface( ...
180+
'InterfaceID', 'IP Data 3 IN', ...
181+
'InterfaceType', 'IN', ...
182+
'PortName', 'util_dac_unpack_dac_data_03', ...
183+
'PortWidth', 16, ...
184+
'InterfaceConnection', 'util_ad9361_dac_upack/dac_data_3', ...
185+
'IsRequired', false);
186+
187+
hRD.addInternalIOInterface( ...
188+
'InterfaceID', 'IP Load Tx Data OUT', ...
189+
'InterfaceType', 'OUT', ...
190+
'PortName', 'util_dac_unpack_dac_valid_00', ...
191+
'PortWidth', 1, ...
192+
'InterfaceConnection', 'util_ad9361_dac_upack/dac_valid_0', ...
193+
'IsRequired', false);
194+
195+
hRD.addInternalIOInterface( ...
196+
'InterfaceID', 'IP Valid Tx Data IN', ...
197+
'InterfaceType', 'IN', ...
198+
'PortName', 'util_dac_unpack_upack_valid_00', ...
199+
'PortWidth', 1, ...
200+
'InterfaceConnection', 'util_ad9361_dac_upack/upack_valid_0', ...
201+
'IsRequired', false);

‎targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/hdlcoder_ref_design_customization.m‎

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function [rd, boardName] = hdlcoder_ref_design_customization
2+
% Reference design plugin registration file
3+
% 1. The registration file with this name inside of a board plugin folder
4+
% will be picked up
5+
% 2. Any registration file with this name on MATLAB path will also be picked up
6+
% 3. The registration file returns a cell array pointing to the location of
7+
% the reference design plugins
8+
% 4. The registration file also returns its associated board name
9+
% 5. Reference design plugin must be a package folder accessible from
10+
% MATLAB path, and contains a reference design definition file
11+
12+
% Copyright 2013-2014 The MathWorks, Inc.
13+
14+
rd = {'AnalogDevicesDemo.adrv9361z7035.ccfmc_lvds_hop.rxtx.plugin_rd', ...
15+
};
16+
17+
boardName = 'AnalogDevicesDemo adrv9361z7035 fmc lvds hop (Rx & Tx)';
18+
19+
end
20+

‎targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/plugin_board.m‎

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1+
function hP = plugin_board()
2+
% Zynq Platform PCore
3+
% Use Plugin API to create board plugin object
4+
5+
% Copyright 2015 The MathWorks, Inc.
6+
7+
% Call the common board definition function
8+
hP = AnalogDevices.adrv9361z7035.common.plugin_board('fmc lvds hop', 'Rx & Tx');
9+

‎targeting_models/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccfmc_lvds_hop/+rxtx/plugin_rd.m‎

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1+
function hRD = plugin_rd
2+
% Reference design definition
3+
4+
% Copyright 2014-2015 The MathWorks, Inc.
5+
6+
% Call the common reference design definition function
7+
hRD = AnalogDevicesDemo.adrv9361z7035.common.plugin_rd('ccfmc_lvds_hop', 'Rx & Tx');
8+
AnalogDevicesDemo.adrv9361z7035.ccfmc_lvds_hop.rxtx.add_rx_tx_io(hRD);

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