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ADP151 + + + + MAX16895 + + 3.5V + + SUP_3.3V + SUP_3.3V + + + + MAX42500 + MONITOR + + + + + + + 3.3V + 1.8V + 1.1V + RESET_OUT + I2C/WATCHDOG + + + MAX6613 + + PCB_TEMP + HYPERBUS + SUPERVISOR + TEMPERATURESENSOR + SUP_3.3V + + + + + + + + LOAD_E + POWER AND COMMS IS BOARD + DIGITAL NON-IS ONLY + BUCK + LDO + + + + + + + LOAD_N + LDO + ISO-POWER + + + MAX17626 + + + + ADP151 + + + + ADP151 + + BUCK + LDO + LDO + + + + + + + LOAD_N + 3.5V + x2 + + + + + + + + + + + + + + + + + + + + + DIGITAL IS ONLY + + + + + + + + + + + + + + + + QSPI + 1.8V + + 1.8V + + + + MAXQ1065 + + SECURITYCHIP + SPI 2 Security + + 3.3V + + ≥1.8k + + + SWD / UARTARM debugger + JTAGRISC-V debugger + I2C + + ToMAX32690 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LOAD_E + + DIGITAL IS AND NON-IS BOARD + + + + + LOAD_E + + + + + + + x3 + + + + + + + + + + + + For Development/Debugging Only + + + + + + + DIN-B CHASSIS EARTH + + + + + + + + SUPERVISOR + + + ADP123 + + LDO + + + + + + + + + + + + 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_ethernet-apl-considerations: + +Ethernet-APL Considerations +=========================== + +Surge Protection +---------------- + +Ethernet-APL specifications requires the use of 25A surge protection +devices to avoid damage due to fast transients. To fulfill this +requiremnts a 25A TVS diode is needed. Due to the parasitic +capacitance of this component (D3), it is important to implement a +low capacitance diodes bridge (D26 to D29) to minimize the TVS diode +capacitance to gurantee proper Ethernet communication. + +In addition, due to the voltage generated by the TVS diode, it is +important to protect the ADIN1110 Tx pins. To achieve this +requirement, a second pair of TVS diodes (D15 and D16) has been +included in these pins. + +Power-up Requirements +--------------------- + +To guarantee that the connection of a new device into the field +switch won't impact other devices connected to the same field +switch, there are mandatory power-up requirements: + +- Maximum current step must be <50mA +- Maximum di/dt of 10mA/ms +- Maximum charge of 20μJ +- No more than 6 current events during the first second + +After the first second the maximum di/dt is limited to 10mA/ms. + +More details can be found in APL Port Profile Specification or the +IEC TS 63444 standard. + +.. figure:: Power-up.png + :width: 450 px + :align: left + :alt: Illustrative Current Step Characteristics During Power-up + + Illustrative Current Step Characteristics During Power-up + +The main way is to make sure there is sequencing implemented on the +power circuit of the APL field device; the power parts should never +start-up at the same time such that it will cause huge spike that +violates the APL specifications or even cause malfunction if it is +not design as intended. + +In addition, a proper power sequence is necessary for the +microcontroller MAX32690, this is for the sequence specific for the +following voltage lines of the microcontroller's main supply pins: +3V3 (VDDIOH/VDD3A), 1V8 (VDDIO/VDDA) and 1V1 (VCORE). It is +recommended that at least every voltage signal rise has a sequence in +which have a time distances apart, either to the time difference +between amplitude, or more specifically, the time difference between +the minimum or threshold/reset voltages of the three main supply +pins of MAX32690: VRST(VDDIOH_MIN) = 1.71V, VRST(VDDIO_MIN) = 1.71V +and VCORE(MIN) = 1.05V. + +.. figure:: MCU_sequence.png + :width: 450 px + :align: left + :alt: Power Up and Power Down Requirements of MAX32690 + + Power Up and Power Down Requirements of MAX32690 + +In power-up capture of the LINE_P current along with the voltages of +REG_3V5, SUP_3V3 and ISO_3V3 one main observation is that the spikes +are generated during the beginning of conduction of every voltage +regulator (e.g., LDO and Buck Converter). If there is no power +sequencing, all of these parts might start-up at the same time, +failing the charge requirement on the spike from the large peak +current it might generate, and may cause other failures on the +reference design. + +.. figure:: Hot_input1.png + + Hot Input LINE_P Current Capture w/ REG_3V5, SUP_3V3, ISO_3V3 + Voltages + +There is another power-up capture, in which the line current is +captured along with the LINE_P voltage and the LOAD_P voltage shown +in below figure. During hot plugging scenario, the LINE_P voltage rise +is extremely fast which generate the main inrush, and this is to be +expected. The inrush does not necessarily have to pass the 20uC +charge maximum, but it is still measured to see and prove that even +at very high peak, the charge is small granted that it happened too +fast. The critical events of current however, are the spikes that +happened after the inrush along with the di/dt. + +Looking at Figure cc, the start-up or di/dt slope or slew rate is +only at 1.5003 mA/ms which is slow enough and it didn't violate the +SPUR di/dt maximum of 10mA/ms. None of the spikes happening after +the inrush has a charge value violating the 20μC maximum. In +addition to the charge and di/dt, the amplitude of all the "events" +which are the spikes and steps of the line current should not exceed +the maximum amplitude feasible, which is dictated on its power +specification, which for Power Class A, the maximum value should +never exceed 55.56mA. The reference design has passed the APL port +profile current step characteristics requirement for start-up during +hot-plug scenario. + +.. figure:: Hot_input2.png + + Hot Input LINE_P Current Capture w/ REG_3V5, LINE_P, LOAD_P Voltages + +Zooming in the beginning of the power-up sequence the following are +measured: The inrush only has a 2.4μC of charge despite the high peak +current of 126mA because of its very fast time, take note that the +inrush doesn't require to pass the 20μC. The more critical spike is +the one happening after the inrush which has a charge of around +13μC to 17μC with a peak of 36.4mA but has a wider time on the +spike. To optimize the 2nd Spike, it is recommended to have a very +small shunt capacitance in the load side of LT8440 or the LOAD_P +node, the lower the capacitance, the lower the spike peak will be +and the shorter the charging time, thus reducing the spike's +effective charge. + +.. figure:: Zoom_hot_input.png + :width: 450 px + :align: left + :alt: Zoomed Hot Input LINE_P Current Capture + + Zoomed Hot Input LINE_P Current Capture + +For the same power sequence during power-up, the LINE_P current is +capture along with the primary three supply voltages of the signal +chain: 3V3, 1V8 and 1V1. The time distance between 3V3 and 1V8 is +186.03ms, between 3V3 and 1V1 is 189.23ms, and zooming in further, +the time distance between 1V8 and 1V1 is 3.2ms. The sequence is in +correct order for start-up, which is 3V3 first, 1V8 second and 1V1 +third or last. + +.. figure:: Hot-Input3.png + :width: 450 px + :align: left + :alt: Hot Input Power-up Sequence of 3V3, 1V8 and 1V1 + + Hot Input Power-up Sequence of 3V3, 1V8 and 1V1 + +.. figure:: Zoom_hot_input3.png + :width: 450 px + :align: left + :alt: Zoomed Power-up Sequence for 1V8 and 1V1 + + Zoomed Power-up Sequence for 1V8 and 1V1 + +The capture for the power shut down sequence of LINE_P current and +the main three supply voltages for the microcontroller, following +the threshold or the minimum reset voltages of each supply: The +time between 3V3 (min = 1.71V) and 1V8 (min = 1.71V) is 0.4ms, +between 3V3 (min = 1.71V) and 1V1 (min = 1.05V) is 0.56ms and +between 1V8 (min = 1.71V) and 1V1 (min = 1.05V) is 0.16ms. It is +also following the correct sequence for shutdown being 1V1 first, +1V8 second and 3V3 third or last. + +.. figure:: shutdown.png + :width: 450 px + :align: left + :alt: Shut-down Sequence for 3V3, 1V8 and 1V1 + + Shut-down Sequence for 3V3, 1V8 and 1V1 \ No newline at end of file diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Ethernet-APL/shutdown.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Ethernet-APL/shutdown.png new file mode 100644 index 000000000..e2b13d561 --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Ethernet-APL/shutdown.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:93371540b5b96f7a8be82ec3607e9bd020804575a84292060d9e47c9597b5f86 +size 123750 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Ethernet-APL/zoom_hot_input.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Ethernet-APL/zoom_hot_input.png new file mode 100644 index 000000000..cd2c2d739 --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Ethernet-APL/zoom_hot_input.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:e31ace4cb6fc0c7bfb8f4308fbf68ce534c80ecb3f0e4afba18dc415c4ef5138 +size 107759 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Connection.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Connection.png new file mode 100644 index 000000000..0a83e237e --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Connection.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:fdbdf00aaf94e0dcca71637d75d78d60778bf31e7590754756c91c3fc825c24b +size 230500 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Current_performance.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Current_performance.png new file mode 100644 index 000000000..062549946 --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Current_performance.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:d059088fbb790ec5a7e3fef3d85a56dcd277e8f84cf93140b48c6d9deaaea303 +size 61681 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Efficiency.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Efficiency.png new file mode 100644 index 000000000..4f935e14e --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Efficiency.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:978da8375c0e8b701584fc7228b9e604318df4afdbe3f7aba4a172865e486726 +size 43201 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/LOAD_P.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/LOAD_P.png new file mode 100644 index 000000000..091ed6b26 --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/LOAD_P.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:a663483a4a4dd3f0b9a96ec5a91f7cfebd9e454eeaa93fa4289588de0a2f8b50 +size 73837 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/LT8440-connection.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/LT8440-connection.png new file mode 100644 index 000000000..16f9da3db --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/LT8440-connection.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:26f4abf536b1d7091234889fdf30200d5bf8ee19bd387897332eb31171bb60c8 +size 241712 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/LT8440-simplify.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/LT8440-simplify.png new file mode 100644 index 000000000..9245a6679 --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/LT8440-simplify.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7fa027383c1ce4ca5f578263b4695ee0e6cf99fc4af11095fcb4637b3afe32e3 +size 130248 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Line_thresolds.csv b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Line_thresolds.csv new file mode 100644 index 000000000..f6136ecd5 --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Line_thresolds.csv @@ -0,0 +1,4 @@ +Condition |VLINEA - VLINEB|,Minimum (V),Typical (V),Maximum(V) +Levels 1 to 2,10.14,10.5,10.82 +Levels 10 to 11,14.57,15,15.43 +Levels 15 to 16,17.02,17.5,17.95 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Power_estimation.csv b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Power_estimation.csv new file mode 100644 index 000000000..d126eafcd --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Power_estimation.csv @@ -0,0 +1,16 @@ +Section,Device analised,Rail,Voltage(V),Current(mA),Power(mW),Comments +"10Base-T1L Circuit ADIN1110",,DVDD_1V1,1.1,12,13.2,1.1V can be taken from internal LDO of ADIN1110 +,,VDDIO,1.8,18,32.4, +,,AVDD_H,1.8,28,50.4, +,,AVDD_L,1.8,28,50.4, +Digital Circuit,MAX32690,VCORE,1.1,9.18,10.098,7.65uA/MHz @ 120MHz (maximum) +,,VDD_3A,3.3,0.339,1.1187,VDD3A connected with VDDIOH +,,VDD_IOH,3.3,8,26.4,I_OL and I_OH max current +,,VDD_A,1.8,0.399,0.7182,VDDA connected with VDDIO +,,VDD_IO,1.8,4,7.2,I_OL and I_OH max current +Analog-to-Digital Converter/ Temperature Sensor Circuit,ADFS7124-4,AVDD (isolated side),3.3,2.2,7.26,being supplied via isolate power +,,IOVDD (isolated side),3.3,1.08,3.564,being supplied via isolate power +Digital Isolator,ADuM1441,VDD1,3.3,0.9,"2,97", +,,VDD2 (isolated side),3.3,0.9,2.97, being supplied via isolate power +Supervisory Circuit,MAX42500,VDD,"3,3",0.15,0.495,being supplied via separate line using LDO (Functional Safety) +,MAX6613,VCC,3.3,0.013,0.0429,being supplied via separate line using LDO (Functional Safety) \ No newline at end of file diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Power_performance.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Power_performance.png new file mode 100644 index 000000000..a8f5d7496 --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Power_performance.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1a0fdc53bdb18e12e1b406a0586e3d2b103139d2bf5b7427a06c40a3f5fe1b84 +size 60496 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Regulation.csv b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Regulation.csv new file mode 100644 index 000000000..dfefce56e --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/Regulation.csv @@ -0,0 +1,8 @@ +Condition |VLINEA - VLINEB|,Minimum (mA),Typica (mA),Maximum(mA) +|VLINEA-VLINEB| = 9V,37.7,40.5,43.3 +Level 1 ,37.7,40.5,43.3 +Level 2,36.9,39.7,42.4 +Level 10,26.3,28.7,31.3 +Level 11,25.3,27.7,30.3 +Level 15,21.7,24.2,26.7 +Level 16,20.9,23.4,25.9 \ No newline at end of file diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/index.rst b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/index.rst new file mode 100644 index 000000000..3095813ca --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/index.rst @@ -0,0 +1,363 @@ +.. _instrinsic_safety_design: + +Intrinsic Safety Design +======================== + +Ethernet-APL Field Platform Power Description +""""""""""""""""""""""""""""""""""""""""""""" + +Introduction +------------ + +The :adi:`AD-ETHERNETAPLDEVICE-SL` follows specification based on +Ethernet-APL Port Profile Power consumption. As a complete system, +with the power conditioner involve as main part of the entire power +tree (along with switching converters and LDO regulators), the +following signal names are identified: + +.. csv-table:: Description for Significant Signals in the Board + :file: power_specifications.csv + :header-rows: 1 + :widths: auto + +As shown in Table 2 - Electrical Characteristics of Power Classes, the +:adi:`AD-ETHERNETAPLDEVICE-SL` has a required Power Class A +specification. For the complete table, read the document's Table 6 +of `Ethernet-APL Port Profile specification +`_. + +.. csv-table:: Electrical Characteristics of Power Classes + (Excerpt only/incomplete table) + :file: power_class.csv + +Circuit Analysis +---------------- +The main goal for the power circuit of the reference design is to +make sure that even if the power produced from the source port is as +minimal as 540mW, or if the power received of the load port (field +device or the :adi:`AD-ETHERNETAPLDEVICE-SL` itself) is as minimal as +only 500mW for Power Class A, the board should still operate normally +on those circumstances. Which means the reference design board should +consume low power as possible that it doesn't violate the boundaries +of line current and voltage range indicated in the specifications. + +This is why the :adi:`LT8440` Power conditioner is important and acts +as main anchor part of the design, because it pulls at minimum 20mA +to drive the protection diodes of the APL line to conduct power and +provide data communication, and also enters shunt regulation mode to +pull enough power for the device to function, while also limiting the +current and power at 650mW maximum worst case to prevent overheating +to comply with intrinsic safety. Ideally its best to select power +parts of the best efficiency so it will only pull much lesser current +on the LINE_P and LOAD_P during normal operation. However, if cost +and small form-factor is the primary concern (in this case on this +reference design with DIN-B form factor), we can slightly compromise +the efficiency but making sure first that it won't violate the line +current ceiling it can pull to the :adi:`LT8440`. + +.. figure:: Connection.png + :alt: Source to Load Simplified 2-WISE/APL Port Connection + + Source to Load Simplified 2-WISE/APL Port Connection + +LT8440 Operation +~~~~~~~~~~~~~~~~ + +The LT8440 can operate on two different constant current regulation: +Shunt Regulation Mode and Current Limit Mode, depending on the +voltage sensed by the LINEA and LINEB pins of LT8440, and the current +that will flow to the LOAD_P thru the system of +AD-EthernetAPLDevice-SL, it will dictate the regulation amplitude of +the line current and which mode it will regulate. For the complete +specification of LT8440 for Table 4, Table 5 and Table 6, see the +Electrical Characteristics on LT8440 datasheet. + +The line current will also depend on both the shunt current +(I_SHUNT) and LOAD_P current (I_LOADP) as the line current (I_LINEP) +is the summation of I_LOADP and I_SHUNT shown in Equation 1. + +.. math:: + + I_LINEP = I_LOADP+I_SHUNT (1) + +.. figure:: LT8440-simplify.png + :alt: Simplified Partial Circuit of LT8440 + + Simplified Partial Circuit of LT8440 + +.. csv-table:: Line Voltage Threshold for sensed voltage between LINEA + and LINEB (Excerpt only - incomplete table) + :file: Line_thresolds.csv + +During Shunt Regulation Mode, the shunt pin of the LT8440 is +conducting in which it satisfies Equation 1. + +The shunt pin will conduct if the current I_LOADP is not conducting +(0mA) or I_LOADP is only minimal or lesser than the typical Shunt +Regulation Mode current indicated in table 5 so the shunt pin detects +the lack of I_LOADP, then the shunt pin pulls more current so that +I_LINEP will regulate the current within the boundaries indicated on +Table 5. + +Shunt current will only be equal to the line current if LOAD_P is +operating at No-Load (0mA). If there is a minimal I_LOADP current, +the Shunt current self-adjust to be what is indicated on Equation 2, +which is simply a linear algebra manipulation of Equation 1. + +.. math:: + + I_SHUNT = I_LINEP - I_LOADP (2) + +For example: for LINE_P voltage of 10.5V, and I_LOADP = 10mA, the +Shunt pin will pull the current I_SHUNT = 30mA approximately, so that +it will satisfy the I_LINEP = 40.5mA (for Level 1) or I_LINEP = +39.7mA (for Level 2). + +.. csv-table:: Regulating Line Current during Shunt Regulation Mode + (Excerpt only - incomplete table) + :file: Regulation.csv + +The LINEA and LINEB pins sensed the voltage on the input line and +dictate the current regulation, the position in which the LINEA/B +connected will have a different measured or sensed voltage while +still complies to the specifications indicated on Table 3 and Table +4, which is provided completely on the LT8440 datasheet. + +The LINEA/B should be connected after the polarity protection diodes +indicated in Figure 3, so that the effective capacitances and +inductances that will generate discharges of the system is being +isolated by the diodes, and it will not be counted to the effective +capacitance nad inductance of the input line or the load port, this +is based on Table 1 of IEC60079-47, the allowable internal line +capacitance is only 5nF, and allowable line inductance is 10uH. This +will however result for the sensed voltage to be lower at normal +operation because of the forward voltages of diodes reducing the +sensed voltage. + +At lower sensed voltage, the current regulation of the LT8440 will +have a higher offset current, but it is still in line with the +electrical specification of LT8440, and the power limiter will still +work as intended. + +Figure 3 is the designed configuration for AD-EthernetAPLDevice-SL +to pass the Intrinsic safety design certification. + +.. figure:: LT8440-connection.png + :alt: Required Frontend Design with Large Effective Capacitance & + Inductance on the Load Side + + Required Frontend Design with Large Effective Capacitance & + Inductance on the Load Side + +Power Tree Design +~~~~~~~~~~~~~~~~~ + +Initial step is to design the power parts after the LT8440 with the +theoretical assumption of the power at maximum load condition that +guarantees to operate the critical signal chain parts of +AD-EthernetAPLDevice-SL, which are going to pull power from the +LT8440's LOAD_P node. The performance of the design for current and +power on LOAD_P shall not exceed the specifications or shall not trip +the limits of LT8440 itself and the APL Specifications. + +Tabulating the estimated power budget of AD-EthernetAPLDevice-SL at +maximum load based on the datasheets of the significant parts of the +signal chain, we can calculate the theoretical power consumption at +worst case and select appropriate power parts for the power tree +using the LTPOWERPLANNER for the Power Tree calculation. + +.. csv-table:: Power Budget at Estimated Full Load + :file: Power_estimation.csv + +In the power tree provided in Figure 8 based on estimated power +budget at full load. + +The reference design incorporates a for the different needed rails, +mainly the triple output of 3.3V (3V3), 1.8V (1V8) and 1.1V (1V1) +lines to power-up the common parts, a separate 3.3V line (SUP_3V3) +dedicated to supplying power for the supervisory circuit, and an +isolated 3.3V (ISO_3V3) for supplying the data isolator and A/D +Converter temperature sensor interface. + +.. figure:: Power_planner.png + :alt: AD-EthernetAPLDevice-SL Power Tree + + AD-EthernetAPLDevice-SL Power Tree + +The LT8606 acts as the pre-regulator of the power tree, it has a +wide range of input voltage, capable of up to 42V maximum operation, +small, efficient, and requires low component, this is suitable to the +wide voltage range of 9V to 15V (or 17.5V maximum) on the LINE_P that +will translate to a slightly reduced wide voltage on the LOAD_P node, +take note that the voltage rating of the selected buck converter is +considered with the 2/3 derating. The 350mA max current can provide +more leeway (from 2/3 de-rating) and still is suitable for this 500mW +system. The UVLO prevents the converter from operating if the LOAD_P +voltage from the ethernet cable is too low, thus preventing some +faulty operating conditions. Zener diodes are added to clamp the +output rail and guarantee it will not exceed the VZ = 4.7V under any +conditions, important as overvoltage protection for intrinsic safety, +because it relaxes the requirements for picking parts when the +voltage and power are much lower after the LT8440 and the Zener +diodes. + +For simulation using LTSPICE for example (or estimation via +datasheet), the LT8606 buck has an estimated efficiency of 90.3% and +in the LTPOWERPLANNER power tree, the calculated maximum pulled +current is 42.8mA in the input of LT8606, which is also the LOAD_P +node. Among the parts for the main voltages 3V3, 1V8 and 1V1, the +1V8 is the one that needs the most current as most of the signal +chain parts, which are ADIN1110 and MAX32690, needed the supply +voltage of 1.8V. To sustain a better efficiency so it won't pull too +much current from the output of LT8606, we need another buck +converter. The selected part for 1V8 output is MAX17626, it is +small, high efficiency capable and requires low component count so +it's easy to implement. By simulation using for example the EE-SIM +Oasis software (or estimation via datasheet), the estimated +efficiency given by the input and output voltages is 83.2% in which +is indicated in the power tree of LTPOWERPLANNER. + +The 3V3 and 1V1 pulls very low current, so LDO regulators are better +and cheaper with negligible effect on power loss. In this case we +picked the ADP151 series of LDOs with fixed values for 1.1V and 3.3V +because of small form factor, reduced cost and lower component +count. + +The MAX253 push-pull converter is the selected isolated power part +because of minimal design requirement or low component count. Based +on the datasheet using 1:1.3 transformer, the estimated efficiency is +84%. This is negligible for estimated drawn current of 4.5mA at the +output with calculated output voltage of 4V to 4.3V. The push-pull +won't regulate properly at light load or lower current, so a post +regulator LDO is included to provide the fixed 3.3V isolated voltage +for the A/D converter and digital isolator. The AVDD of ADFS7124-4 +can be sensitive or in risk of noise, so an optional RLC low pass +filter is included. Zener Diodes are also included in the MAX253 +output to prevent overvoltage by clamping it to VZ = 4.7V during +potential overvoltage fault and for general intrinsic safety. + +For functional safety specifically on the supply for the supervisory +circuit like the MAX42500, the voltage line that is supplying should +not be the voltage it monitors. A separate 3.3V line is powering the +supervisor using ADP151-3.3V LDO which is labeled SUP_3V3, therefore +the MAX42500 will still work properly even if there is an OV/UV +event occurring to 3V3, 1V1, and 1V8. + +For the external SPI of AD-EthernetAPLDevice-SL, we included a +dedicated supply pin of external 3.3V, although it is not counted in +the overall power calculation because the SPI's load specification +is not defined. However, the extra power that is available or unused +will be dedicated to the external SPI, with the main LDO selected is +ADP123. The LDO's dedicated VOUT feedback is usable for application +were we need to modify the output voltage it will regulate. This is +specific for intrinsic safety case where a limiting resistor is +added, but the output should still maintain in 3.3V. + +Based on the calculation of the LTPOWERPLANNER, the maximum power or +full load is approximately 300mW which is the estimated power pulled +on the LOAD_P, and the I_LOADP only pulls an estimated maximum +current of 42.85mA, which didn't exceed the limit of 55.56mA of APL. + +Note: The actual power on the board can be much lesser than the +calculated power because the parts like the MAX32690 and ADIN1110 +won't require to fully utilized that much power to function. The +actual or measured power and current are discussed on the Power +Consumption section. + +Power Consumption +~~~~~~~~~~~~~~~~~ + +Characterizing the performance of the LT8440 Power Conditioner and +the entire Power Tree, the following curves are captured at ambient +temperature of 25 degrees Celsius (typical). + +.. figure:: LOAD_P.png + :alt: LOAD_P (Load Side) and Shunt Parameters + + LOAD_P (Load Side) and Shunt Parameters + +The load side power and current are pulling approximately 288mW and +21.38mA respectively at 15V line voltage, these are the highest +parameters that the load side or LOAD_P node will consume during +normal operation. + +For 9V line, the load side power and current are pulling +approximately 260.9mW and 19.706mA respectively at normal operation. + +The reference design is operating on LT8440's shunt regulation mode, +where the shunt pin is pulling current. The shunt power and current +are pulling approximately 122.03mW and 9.03mA respectively at 15V +line voltage, while its approximately 19.71mW and 2.79mA +respectively at 9V line voltage. The highest shunt power occurred +at 12.7V line voltage which is approximately 139.46mW. + +The shunt and load side power are small enough to not violate the APL +limit when adding the two parameters. + +.. figure:: Efficiency.png + :alt: Efficiency and Current of Power Tree + + Efficiency and Current of Power Tree + +The power tree was designed with the intention of prioritizing the +small form factor and cost of parts, so there is a trade-off in the +power efficiency for these power parts that are connected after the +load side of LT8440. + +As shown in Figure 6, the efficiency in range of 33.04% up to +36.65% which is not high and is a significant trade-off despite the +very low power consumption, as long as it does not exceed the APL +Limit power consumption of 500mW. Which on another point of focus, +the efficiency can be trade-off, but the power pulled, or to be more +specific, the current being pulled should be low enough that it +would not exceed the current ceiling of the APL limit as shown also +in Figure 6. So, when sacrificing the efficiency, it will pull more +current and power, but those two parameters must not exceed what is +indicated on the APL requirements like the 55.56mA maximum current at +9V, and the 500mW limit for the entire line voltage range. + +.. figure:: Power_performance.png + :alt: LINE_P Power Performance at Normal Operation, Shorted and + Opened Load + + LINE_P Power Performance at Normal Operation, Shorted and + Opened Load + +Speaking of the line voltage range of APL, the actual entire power +consumption range of the whole reference design is measured, the +power curves are shown in Figure 7. During normal operation, which +is for the boundaries of APL profile specs in the line voltage range +of 9V to 15V, the maximum power occurred at LINE_P for line voltage +of 12.7V is 484mW, which if compared to the open or disconnected +load side of LT8440 at shunt mode, the power is the same 484mW at +12.8V line voltage instead. + +For Intrinsic safety scenario at line voltage range of 9V to 17.5V as +dictated by IEC60079-47 standard, the maximum APL line power is +625.62mW during the scenario that the load side is intentional +faulted/shorted, it did not exceed the maximum die power rating of +650mW, and is within below the 5.32W specification of IEC60079-47, +therefore the LT8440 is doing its function as a power conditioner at +normal operation and as a power limiter during fault scenario. + +.. figure:: Current_performance.png + :alt: LINE_P Current Performance at Normal Operation, Shorted and + Opened Load + + LINE_P Current Performance at Normal Operation, Shorted and + Opened Load + +The triangular nature of the power curve of LINE_P is a result of the +staircase like nature of the I_LINEP or APL line current. This is +from the inherent design or construction of the LT8440 silicon in +which it has hysteresis in its sensing of voltage during current +regulation, so the shifting of current regulated has hysteresis +transition first whenever the sensed voltage changes or varies. + +For the line currents, none of it exceeds to the limits of APL +during normal operation, and also shorted operation of IEC60079-47 +as shown in Figure 8. + +For questions and more information, please visit the `EngineerZone +`_ community or contact your local ADI +representative. diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_class.csv b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_class.csv new file mode 100644 index 000000000..2a1de46bd --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_class.csv @@ -0,0 +1,8 @@ +Specs,Class A,Class C,Class 3 +UPS(max) (VDC) ,15,15,50 +UPS(min) (VDC) ,9.6,11.61,46 +IPS(min) (mA) ,55.56,95,1250 +PPS(min) (W) ,0.54,1.1,57.5 +UPL(min) (VDC) ,9,1,36 +PPL(min) (W) ,0.5,1,36 +IPL(min) (mA) ,20,20,40 \ No newline at end of file diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_planner.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_planner.png new file mode 100644 index 000000000..d21e1cc0a --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_planner.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:376c8f6269e7c791e75a6591722ab9c63d5cdfc454dd50c5a2085c3c73209ab0 +size 5611138 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_specifications.csv b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_specifications.csv new file mode 100644 index 000000000..6db82ceb2 --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/Power/power_specifications.csv @@ -0,0 +1,14 @@ +Node Name,Value,Description +1V1,1.1V,"1.1V output of AD151-1.1 LDO, supplying the MAX32690's VCORE" +1V8,1.8V,"1.8V output of MAX17626 buck converter, for VDDIO of 1.8V in the entire signal chain" +3V3,3.3V,"Output voltage of ADP151-3.3 LDO, powering up VDD with 3.3V requirement" +3V5,3.5V to 3.6V,"Output voltage of LT8606 buck converter, approximately within 3.5V, can have a bit more margin if increase to 3.6V" +I_LINEP,20mA to 55.56mA,"Current at the Ethernet-APL Line, the main input current, or the line current, or the main DC current consumption" +I_LOADP,0mA to 55mA,"Current at Load side of LT8440, also known as input current of LT8606 Buck Converter" +I_SHUNT,0mA to 43.3mA,Current flowing to the Shunt Pin of LT8440 +ISO_3V3,3.3V,Isolated output of 3.3V produced by combination of MAX253 push-pull and ADP151-3.3 LDO. w/ respect to secondary/isolated ground +ISO_GND,Ground (0V),isolated ground +LINE_P,9V to 15V (typical),"Input APL Line (the differential connection of LINE_P and LINE_N is the ""LOAD PORT"" of APL field device)" +LOAD_N,Ground (0V),main local ground (named LOAD_E on secondary board of AD-EthernetAPLDevice-SL) +LOAD_P,approx. 8V to 14V (typical),"Voltage at Load Side of LT8440, also the input of LT8606 Buck converter" +SUP_3V3,3.3V,"Separate 3.3V output for supplying supervisory circuits like MAX42500 and MAX6613, using ADP151-3.3 LDO " \ No newline at end of file diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/index.rst b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/index.rst index 4bd49616a..031bb4722 100644 --- a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/index.rst +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/index.rst @@ -59,14 +59,14 @@ Hardware Design Files ~~~~~~~~~~~~~~~~~~~~~ - :download:`Schematic Power and Comms board <02-083152-01-b.pdf>` -- :download:`Schematic Digital IS board <02-083153-01-c.pdf>` +- :download:`Schematic Digital IS board <02-083153-01-d.pdf>` - :download:`Schematic Digital NON-IS board <02-084576-01-b.pdf>` -- :download:`Layout Power and Comms board <08-083152-01-b-1.pdf>` -- :download:`Layout Digital IS board <08-083153-01-c.pdf>` +- :download:`Layout Power and Comms board <08-083152-01-b.pdf>` +- :download:`Layout Digital IS board <08-083153-01-d.pdf>` - :download:`Layout Digital NON-IS board <08-084576-01-b.pdf>` -- :download:`Bill of Materials Power and Comms board <05-083152-01-b.csv.zip>` -- :download:`Bill of Materials Digital IS board <05-083153-01-c.csv.zip>` -- :download:`Bill of Materials Digital NON-IS board <05-084576-01-b.csv.zip>` +- :download:`Bill of Materials Power and Comms board <05-083152-01-b.zip>` +- :download:`Bill of Materials Digital IS board <05-083153-01-d.zip>` +- :download:`Bill of Materials Digital NON-IS board <05-084576-01-b.zip>` Package Contents ---------------- @@ -195,11 +195,8 @@ The software stack includes: - Secure boot and authentication via MAXQ1065 - Zephyr RTOS support -.. - Enable this after adding content - - Complementary Documentation - --------------------------- +Complementary Documentation +--------------------------- .. toctree:: :titlesonly: diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/02-083152-01-b.pdf b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/02-083152-01-b.pdf new file mode 100644 index 000000000..7786d705a Binary files /dev/null and b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/02-083152-01-b.pdf differ diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/02-083153-01-c.pdf b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/02-083153-01-c.pdf new file mode 100644 index 000000000..d10a2b2de Binary files /dev/null and b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/02-083153-01-c.pdf differ diff --git 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b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/05-083153-01-c.csv.zip new file mode 100644 index 000000000..fb6579fe8 --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/05-083153-01-c.csv.zip @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ff98c998a3ff22d3716311c89298e130510eb30bc1453c870bdbc802fefb4bbf +size 4356 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/05-084576-01-b.csv.zip b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/05-084576-01-b.csv.zip new file mode 100644 index 000000000..49eb07f3f --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/05-084576-01-b.csv.zip @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f44c3d63c9db0b64b83f806931f5c0563fd6b8952dce74ae7bc97add5718bd18 +size 4357 diff --git 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CM + POWER LIMITER + POLARITY PROTECTION + ETHERNETCONNECTOR + EXTERNAL SPICONNECTOR + TEMPERATURE SENSECONNECTOR + ISOLATED DOMAIN + DM + + + LT8606 + + + + + + ADIN1110TX/RX + + + + + + SRAM + + FLASH + + + + + + ADFS7124-4ADC + + + + + + + + + + + + + + + + + + + + LOAD_N + LOAD_P + SHUNT + 1.8V + + + MAX32690PROCESSOR + + ADuM1441ISOLATION + + 3.3V + + 3.5V + + 1.1V + + 1.8V + + + 3.3V iso + 3.3V_iso + + + 3.3V + + 3.5V + + + + + MAX253 + + + + + + + + + + + + + 3.5V + + + + + + + + ADP151 + + + + + + + 3.3V + 3.5V + 3.3V + 3.3V + + 1.8V + + 1.1V + + + + + + SPI 3 + SPI 4 + SPI 1 + + SPI 0 iso + SPI 1 + SPI 0 + + + + + + + + + + + + + + + + + + iso + + + + + + + + + iso + iso + + + + + iso + + + + + iso + + + + + + + + + + NTC + + ≥3k + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + < 2 : 2 > + < 2 : 2 > + LOAD_N + LOAD_N + LOAD_N + LOAD_E + x3 + x3 + x2 + + + ADP151 + + + + MAX16895 + + 3.5V + + SUP_3.3V + SUP_3.3V + + + + MAX42500 + MONITOR + + + + + + + 3.3V + 1.8V + 1.1V + RESET_OUT + I2C/WATCHDOG + + + MAX6613 + + PCB_TEMP + HYPERBUS + SUPERVISOR + TEMPERATURESENSOR + SUP_3.3V + + + + + + + + LOAD_E + POWER AND COMMS IS BOARD + DIGITAL NON-IS ONLY + BUCK + LDO + + + + + + + LOAD_N + LDO + ISO-POWER + + + MAX17626 + + + + ADP151 + + + + ADP151 + + BUCK + LDO + LDO + + + + + + + LOAD_N + 3.5V + x2 + + + + + + + + + + + + + + + + + + + + + DIGITAL IS ONLY + + + + + + + + + + + + + + + + QSPI + 1.8V + + 1.8V + + + + MAXQ1065 + + SECURITYCHIP + SPI 2 Security + + 3.3V + + ≥1.8k + + + SWD / UARTARM debugger + JTAGRISC-V debugger + I2C + + ToMAX32690 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LOAD_E + + DIGITAL IS AND NON-IS BOARD + + + + + LOAD_E + + + + + + + x3 + + + + + + + + + + + + For Development/Debugging Only + + + + + + + DIN-B CHASSIS EARTH + + + + + + + + SUPERVISOR + + + ADP123 + + LDO + + + + + + + + + + + + + + + + + + + 25A + LT8440 + + + + + + + + + + + + + + + + diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/CM-choke.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/CM-choke.png new file mode 100644 index 000000000..08b1833c2 --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/CM-choke.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:cdbe14cf4ca0e8b46524a5a8e3dd8a7a16641135151e78c19fb8380720547757 +size 42694 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/COMB_TOP.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/COMB_TOP.png new file mode 100644 index 000000000..5b4bb501c --- /dev/null +++ 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b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/IS-block-analysis.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1b8f571b0c8cb47d434389716398a37844f37c4380c025e1262224895a199556 +size 338653 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/IS-connector.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/IS-connector.png new file mode 100644 index 000000000..6424e724e --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/IS-connector.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9b76e1dbf0928d194ef83132facb63f3e78f03f39b41bf6e1ca034441f06ed7f +size 278261 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/Power-connectors.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/Power-connectors.png new file mode 100644 index 000000000..55fbc6def --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/Power-connectors.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:0d3d25512686d8ad047e2021f36229e669d6c7cf6e507256ae3f0316b6aef223 +size 349761 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/index.rst b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/index.rst new file mode 100644 index 000000000..c96ca52f5 --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/index.rst @@ -0,0 +1,259 @@ +Intrinsic Safety Design +======================== + +Ethernet-APL Field Platform Intrinsic Safety Analysis +""""""""""""""""""""""""""""""""""""""""""""""""""""" + +Introduction +------------ + +The :adi:`AD-ETHERNETAPLDEVICE-SL` has been certify for Ex ia IIC Ga intrinsic safety requirements +according to IEC 60079-11:2011 standard. + +Key Parameters +~~~~~~~~~~~~~~~ + +.. csv-table:: Electrical Data + :file: specifications.csv + +**DISCLAIMER** + +The electrical circuits must be protected by encapsulation within the final device. Such an encapsulation is required for: + +- protection against spark ignition (IEC 60079-11:2023, 6.6.2.1) +- protection against thermal ignition (IEC 60079-11:2023, 6.6.2.2) +- rating of electrical components from which the intrinsic safety depends (IEC 60079-11:2023, 6.6.6) +- application of separation distances through casting compound (IEC 60079-11:2023, Table 7, column 3) + +The corresponding sections of EN 60079-11:2012 shall be applied in addition. + +An enclosure is not part of this certification. + +The full technical requirements of manufacturer's specification must be considered for the final device. +The local temperature range of -40 °C ≤ Tamb ≤ +85 °C shall never be exceeded. The maximum surface temperature +does not exceed 135 °C (for T4), if the end user fulfills all requirements. + +This Ex Component has no "Ex" marking as it is not offered separately for sale, but is solely for integration +by the Ex Component manufacturer into their own Ex Components or Ex Equipment. + +Circuit Analysis +---------------- +Other than the classical considerations for intrinsic safety component selection, such power ratings, +distances or temperature coefficients, special attention has been paid to the blocks +highlighted in the diagram. + +.. figure:: IS-block-analysis.png + :width: 500 px + :alt: AD-EthernetAPLDevice-SL Board + + AD-EthernetAPLDevice-SL Board + +Surge Protection +~~~~~~~~~~~~~~~~ + +Ethernet-APL specifications requires the use of 25A surge protection devices to avoid damage due to high voltage transients. +While this requirement is not part of the intrinsic safety certification, it is important to use a low capacitance diodes +to minimize the TVS diode capacitance to gurantee proper Ethernet communication. + +Common-mode Inductor +~~~~~~~~~~~~~~~~~~~~ + +The primary function of this industor is to remove the common mode noise that can be present in the field wiring. +The required value exceeds the maximum value for intrinsic safety. + +To qualify the component, independent measurements have been performed to verify that the energy stored by +the inductor is within allowable limits at different conditions. + +.. figure:: CM-choke.png + :width: 500 px + :alt: CM choke + + CM choke peak energy + +LT8440 Sensing and Power Limiter +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The :adi:`LT8440` has been specially designed for Ethernet-APL Intrinsic Safety applications. + +It serves two primary functions, the first one is to minimize input current glitches that could disrupt +the Ethernet communication, and the second one is to limit the power that can be delivered +to the system in case of a fault condition. The :adi:`LT8440` adjust teh maximum current allowable to teh load by sensing +the input voltage provided by the field switch so deliver teh maximum possible power to the load. + +In our design, the sensing input pins from the :adi:`LT8440` has been connected after the diode bridge +as this allows for a higher capacitance values. + +Zener diodes +~~~~~~~~~~~~ + +The Zener diodes will limit the maximum voltage seeing by the circuitr in case of failure. +Remember that the maximum voltage allowed in the intrinsic safety analysis is 28V. + +- Certified for intrinsic safety (Ex ia IIC Ga) +- Pre-certified Ethernet-APL +- Functional safety ready (SIL2) with: + + - :adi:`MAX42500` voltage monitor with integrated windowing watchdog + - :adi:`MAX66132` temperature sensor + - :adi:`ADFS7124-4` sigma-delta ADC (SC3 certified) + - Complete FMEDA documentation + +- :adi:`MAX32690` dual-core MCU (ARM Cortex-M4 with FPU + RISC-V co-processor) +- External RAM (512 Mb) and Flash (64 Mb) +- :adi:`MAXQ1065` security co-processor for: + + - Root-of-trust + - Mutual authentication + - Data confidentiality and integrity + - Secure boot and communications + +- 10BASE-T1L Ethernet via :adi:`ADIN1110` MAC/PHY +- Powered via Single-Pair Power over Ethernet (SPoE), :adi:` ADIN1100D2Z`recommended +- Open-source software stack with drivers and example applications +- Zephyr RTOS support and integration with Code Fusion Studio + +.. figure:: COMB_TOP.png + :width: 450 px + :align: left + :alt: AD-EthernetAPLDevice-SL Board + + AD-EthernetAPLDevice-SL Board + +.. figure:: APL_Hockeypuck_block_diagram.svg + :width: 450 px + :align: right + :alt: Simplified Block Diagram + + Simplified Block Diagram + +.. csv-table:: Specifications + :file: specifications.csv + +Hardware Design Files +~~~~~~~~~~~~~~~~~~~~~ + +- :download:`Schematic Power and Comms board <02-083152-01-b.pdf>` +- :download:`Schematic Digital IS board <02-083153-01-c.pdf>` +- :download:`Schematic Digital NON-IS board <02-084576-01-b.pdf>` +- :download:`Layout Power and Comms board <08-083152-01-b-1.pdf>` +- :download:`Layout Digital IS board <08-083153-01-c.pdf>` +- :download:`Layout Digital NON-IS board <08-084576-01-b.pdf>` +- :download:`Bill of Materials Power and Comms board <05-083152-01-b.csv.zip>` +- :download:`Bill of Materials Digital IS board <05-083153-01-c.csv.zip>` +- :download:`Bill of Materials Digital NON-IS board <05-084576-01-b.csv.zip>` + +Package Contents +---------------- + +The development kit is delivered with a set of accessories required to put the system together and get it up and running in no time. + +This is what you’ll find in the development kit box: + +- 1x AD-EthernetAPLDevice-SL intrinsic safety certify kit (Power and Comms + Digital IS boards) +- 1x Digital NON-IS board. This board is not IS certify and enables acces to the RISC-V JTAG for debugging pourposes (Digital NON-IS board) +- 1x MAX32650PICO programmer (ARM) + cable +- 1x OLIMEX programmer (RISC-V) +- 1x OLIMEX adapter + cable + +Application Development +----------------------- + +.. figure:: sw_block_diagram.png + :width: 400 px + + Software Architecture + +The :adi:`AD-ETHERNETAPLDEVICE-SL ` firmware examples are based on ADI’s +open-source no-OS framework. It includes the bare-metal device drivers for all +the components in the system as well as example applications enabling +connectivity via the 10BASE-T1L interface for system configuration and data +transfer. + +`AD-ETHERNETAPLDEVICE-SL Firmware Source Code and User Guide `__ + +Additionaly, a propietary PROFINET stack software application is available to enable easy evaluation and system prototyping (myanalog.com registration required). + +The board is fully supported in Code Fusion Studio. link. + +Hardware Components and Connections +----------------------------------- + +.. figure:: Power-connectors.png + :width: 600 px + + Power Board Connections + +.. figure:: IS-connector.png + :width: 600 px + + Digital IS Board Connections + + .. figure:: non-IS-connectors.png + :width: 600 px + + Digital NON_IS Board Connections + +.. csv-table:: Pin Description + :file: pin-descriptions.csv + +Hardware Setup +-------------- + +Required Hardware +~~~~~~~~~~~~~~~~~ + +- **Development kit**: AD-EthernetAPLDevice-SL +- **Debugging board**: If Risc-V co-processor need to be debugged, replace the IS digital board with the NON-IS Digital board +- **Power supply**: Single-Pair Power over Ethernet (SPoE) via DEMO-ADIN1100D2Z supplied from external power connector (from 9V to 15V), or a Ethernet-APL field switch +- **ARM programmer**: MAX32625PICO or any SWD-compatible programmer +- **RISC-V programmer** Olimex ARM-USB-OCD +- **Media converter** 10BASE-T1L to 10BASE-T or similar. DEMO-ADIN1100D2Z includes a media converter and can be used for both power and data or , or a Ethernet-APL field switch + +Setup Instructions +~~~~~~~~~~~~~~~~~~ + +1. Connect the AD-EthernetAPLDevice-SL to the DEMO-ADIN1100D2Z and ensure all connectors are fully seated. + +2. Connect a 2- or 4-wire PT100 sensor to the temperature connector. + +3. Attach the MAX32625PICO programmer to the ARM debug header using the 10-pin ribbon cable. + +4. For RISC‑V debugging, install the NON‑IS digital board and connect the RISC‑V debug probe to the RISC‑V JTAG header (available only on the NON‑IS board). + +5. Connect the DEMO-ADIN1100D2Z to your PC via Ethernet. + +6. Apply power to the DEMO-ADIN1100D2Z (9V to 15V input). The AD-EthernetAPLDevice-SL will be powered via SPoE. + +.. figure:: Config.png + :width: 600 px + :alt: Hardware Setup + + AD-EthernetAPLDevice-SL Hardware Setup + +Software Setup +-------------- + +Programming the AD-EthernetAPLDevice-SL +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The AD-EthernetAPLDevice-SL is supported by an open-source software stack based on Analog Devices’ no-OS framework. It includes: + +- Bare-metal drivers for all on-board components +- Example applications for data acquisition and system configuration via 10BASE-T1L +- Zephyr RTOS board definition +- Integration with Code Fusion Studio + +For a complete experience, donwload latest Code Fusion Studio from `here `_. + +The software stack includes: + +- no-OS drivers and HAL +- Example applications for ADCs, DACs, sensors +- UART and Ethernet (10BASE-T1L) communication support +- Secure boot and authentication via MAXQ1065 +- Zephyr RTOS support + +Help and Support +---------------- + +For questions and more information, please visit the :ez:`/` community or contact your local ADI representative. diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/non-IS-connectors.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/non-IS-connectors.png new file mode 100644 index 000000000..dbc8e17a8 --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/non-IS-connectors.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1c0543ad44766f8bf261e889ee9d83419df79b11f5b0bb5f109fce874d98e1ad +size 283677 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/pin-descriptions.csv b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/pin-descriptions.csv new file mode 100644 index 000000000..649725ddd --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/pin-descriptions.csv @@ -0,0 +1,6 @@ +Jumper settings, + +R25 & R24,Configure the MAX42500 I2C address +R30 & R68,Configure the ADIN1110 SPI protocol +R98,Connects MAXQ1065 HW Reset pin to teh MAX32690 HW reset pin +R100,Connects the MAX42500 reset pin to the MAX32690 and ADIN1110 HW reset pins diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/specifications.csv b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/specifications.csv new file mode 100644 index 000000000..08b0c5378 --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/specifications.csv @@ -0,0 +1,9 @@ +Computing Resources, +CPU,MAX32690 Ultralow Power ARM Cortex-M4 with FPU-Based Microcontroller (MCU) with 3 MB Flash and 1 MB SRAM +Memory,512 Gb RAM +Storage,64 Mb QSPI Flash +Security,MAXQ1065 Ultralow Power Cryptographic Controller with ChipDNATM +Connectivity, +Ethernet,"ADIN1110 Robust, Industrial, Low Power 10BASE-T1L Ethernet MAC-PHY" +Power supply, +PoDL,9V DC to 15V DC diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/sw_block_diagram.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/sw_block_diagram.png new file mode 100644 index 000000000..f7bacfa1d --- /dev/null +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/intrinsic-safety/sw_block_diagram.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:869c2524a94f2a4cb83a83edbcc8850540da50a335079c325e72b124dfcb1375 +size 119657 diff --git a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/sw_block_diagram.png b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/sw_block_diagram.png index f7bacfa1d..01ef8b996 100644 --- a/docs/solutions/reference-designs/ad-ethernetapldevice-sl/sw_block_diagram.png +++ b/docs/solutions/reference-designs/ad-ethernetapldevice-sl/sw_block_diagram.png @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:869c2524a94f2a4cb83a83edbcc8850540da50a335079c325e72b124dfcb1375 -size 119657 +oid sha256:67022734e6fdc51c776b0947b1c865e8dd5d1ebc427ab411d564be30ac9581d0 +size 103423