Merge pull request #1 from Cook879/main

MarkA21 · web-flow · commit 9b136ef5fb9e · 2022-12-13T15:46:00.000Z
Fix paths in config.js
diff --git a/Zybo_Z7_10_Board/html/js/config.js b/Zybo_Z7_10_Board/html/js/config.js
@@ -24,17 +24,17 @@ var index =
       {
         "column": "modules",
         "name": "Module 1: Introduction to Arm-based System on Chip Design",
-        "link": "contents/Module_1/Presentation1.pptx"
+        "link": "contents/Module 01_Introduction to Arm-based System on Chip Design/Presentation1.pptx"
       },
 	  {
         "column": "exercises",
         "name": "Quiz 1",
-        "link": "contents/Module_1/Quiz1.docx"
+        "link": "contents/Module 01_Introduction to Arm-based System on Chip Design/Quiz1.docx"
       },
 	  {
         "column": "exercises",
         "name": "Getting Started Guide",
-        "link": "contents/Module_1/Getting_Started.docx"
+        "link": "contents/Module 01_Introduction to Arm-based System on Chip Design/Getting_Started.docx"
       }
     ],
 	
@@ -43,12 +43,12 @@ var index =
       {
         "column": "modules",
         "name": "Module 2: Arm and Arm Processors",
-        "link": "contents/Module_2/Presentation2.pptx"
+        "link": "contents/Module 02_Arm and Arm Processors/Presentation2.pptx"
       },
 	  {
         "column": "exercises",
         "name": "Quiz 2",
-        "link": "contents/Module_2/Quiz2.docx"
+        "link": "contents/Module 02_Arm and Arm Processors/Quiz2.docx"
       }
     ],
 	
@@ -57,7 +57,7 @@ var index =
       {
         "column": "modules",
         "name": "Module 3: Armv7-A/R Instruction Set Architecture Overview Part 1",
-        "link": "contents/Module_3/Presentation3.pptx"
+        "link": "contents/Module 03_Armv7-AR Instruction Set Architecture Overview_part 1/Presentation3.pptx"
       }
     ],
 	
@@ -66,23 +66,23 @@ var index =
       {
         "column": "modules",
         "name": "Module 4: Armv7-A/R Instruction Set Architecture Overview Part 2",
-        "link": "contents/Module_4/Presentation4.pptx"
+        "link": "contents/Module 04_Armv7-AR Instruction Set Architecture Overview Part 2/Presentation4.pptx"
       },
 	  {
         "column": "exercises",
         "name": "Quiz 3_4",
-        "link": "contents/Module_4/Quiz3_4.docx"
+        "link": "contents/Module 04_Armv7-AR Instruction Set Architecture Overview Part 2/Quiz3_4.docx"
       },
 	  {
         "column": "exercises",
         "name": "Lab 4: Programming a processor using Arm Assembly Language and C",
-        "link": "contents/Module_4/Lab4_manual.docx"
+        "link": "contents/Module 04_Armv7-AR Instruction Set Architecture Overview Part 2/Lab4_manual.docx"
       },
 
       {
         "column": "files",
         "name": "Lab 4 Files",
-        "link": "contents/Module_4/lab_file/"
+        "link": "contents/Module 04_Armv7-AR Instruction Set Architecture Overview Part 2/lab_file"
       }
     ],
 	
@@ -91,12 +91,12 @@ var index =
       {
         "column": "modules",
         "name": "Module 5: Arm Cortex-A9 processor",
-        "link": "contents/Module_5/Presentation5.pptx"
+        "link": "contents/Module 05_Arm Cortex-A9 processor/Presentation5.pptx"
       },
 	  {
         "column": "exercises",
         "name": "Quiz 5",
-        "link": "contents/Module_5/Quiz5.docx"
+        "link": "contents/Module 05_Arm Cortex-A9 processor/Quiz5.docx"
       }
     ],
 	
@@ -105,12 +105,12 @@ var index =
 	  {
         "column": "modules",
         "name": "Module 6: AMBA AXI4 Bus Architecture",
-        "link": "contents/Module_6/Presentation6.pptx"
+        "link": "contents/Module 06_Arm Cortex-A9 processor/Presentation6.pptx"
       },
 	  {
         "column": "exercises",
         "name": "Quiz 6",
-        "link": "contents/Module_6/Quiz6.docx"
+        "link": "contents/Module 06_Arm Cortex-A9 processor/Quiz6.docx"
       }
     ],
 	
@@ -119,23 +119,23 @@ var index =
       {
         "column": "modules",
         "name": "Module 7: AXI4-Lite GPIO Peripheral and DDR memory controller",
-        "link": "contents/Module_7/Presentation7.pptx"
+        "link": "contents/Module 07_AXI4-Lite GPIO Peripheral and DDR memory controller/Presentation7.pptx"
       },
 	  {
         "column": "exercises",
         "name": "Quiz 7",
-        "link": "contents/Module_7/Quiz7.docx"
+        "link": "contents/Module 07_AXI4-Lite GPIO Peripheral and DDR memory controller/Quiz7.docx"
       },
 	  {
         "column": "exercises",
         "name": "Lab 7: AXI-Lite and GPIOs",
-        "link": "contents/Module_7/Lab7_manual.docx"
+        "link": "contents/Module 07_AXI4-Lite GPIO Peripheral and DDR memory controller/Lab7_manual.docx"
       },
 
       {
         "column": "files",
         "name": "Lab 7 Files",
-        "link": "contents/Module_7/lab_file/"
+        "link": "contents/Module 07_AXI4-Lite GPIO Peripheral and DDR memory controller/lab_file"
       }
     ],
 	
@@ -144,12 +144,12 @@ var index =
       {
         "column": "modules",
         "name": "Module 8: AXI UART and AXI4-Stream Peripherals",
-        "link": "contents/Module_8/Presentation8.pptx"
+        "link": "contents/Module 08_AXI UART and AXI4-Stream Peripherals/Presentation8.pptx"
       },
       {
         "column": "exercises",
         "name": "Quiz 8",
-        "link": "contents/Module_8/Quiz8.docx"
+        "link": "contents/Module 08_AXI UART and AXI4-Stream Peripherals/Quiz8.docx"
       }
     ],
 	
@@ -158,22 +158,22 @@ var index =
       {
         "column": "modules",
         "name": "Module 9: HDMI overview",
-        "link": "contents/Module_9/Presentation9.pptx"
+        "link": "contents/Module 09_HDMI overview/Presentation9.pptx"
       },
 	  {
         "column": "exercises",
         "name": "Quiz 9",
-        "link": "contents/Module_9/Quiz9.docx"
+        "link": "contents/Module 09_HDMI overview/Quiz9.docx"
       },
 	  {
         "column": "exercises",
         "name": "Lab 9: HDMI output",
-        "link": "contents/Module_9/Lab9_manual.docx"
+        "link": "contents/Module 09_HDMI overview/Lab9_manual.docx"
       },
       {
         "column": "files",
         "name": "Lab 9 Files",
-        "link": "contents/Module_9/lab_file/"
+        "link": "contents/Module 09_HDMI overview/lab_file"
       }
     ],
 	
@@ -182,12 +182,12 @@ var index =
 	  {
         "column": "modules",
         "name": "Module 10: HDMI input peripheral",
-        "link": "contents/Module_10/Presentation10.pptx"
+        "link": "contents/Module 10_HDMI input peripheral/Presentation10.pptx"
       },
       {
         "column": "exercises",
         "name": "Quiz 10",
-        "link": "contents/Module_10/Quiz10.docx"
+        "link": "contents/Module 10_HDMI input peripheral/Quiz10.docx"
       }
 	],
 	
@@ -197,12 +197,12 @@ var index =
       {
         "column": "modules",
         "name": "Module 11: System debugging",
-        "link": "contents/Module_11/Presentation11.pptx"
+        "link": "contents/Module 11_System debugging/Presentation11.pptx"
       },
       {
         "column": "exercises",
         "name": "Quiz 11",
-        "link": "contents/Module_11/Quiz11.docx"
+        "link": "contents/Module 11_System debugging/Quiz11.docx"
       }
     ],
 	
@@ -211,12 +211,12 @@ var index =
       {
         "column": "modules",
         "name": "Module 12: Image-Processing Application",
-        "link": "contents/Module_12/Presentation12.pptx"
+        "link": "contents/Module 12_Image-Processing Application/Presentation12.pptx"
       },
       {
         "column": "exercises",
         "name": "Quiz 12",
-        "link": "contents/Module_12/Quiz12.docx"
+        "link": "contents/Module 12_Image-Processing Application/Quiz12.docx"
       }
     ],
 	
@@ -225,7 +225,7 @@ var index =
       {
         "column": "modules",
         "name": "Module 13: Accelerate Image Processing using SIMD engine",
-        "link": "contents/Module_13/Presentation13.pptx"
+        "link": "contents/Module 13_Accelerate Image Processing using SIMD engine/Presentation13.pptx"
       }
     ],
 	
@@ -234,7 +234,7 @@ var index =
       {
         "column": "modules",
         "name": "Module 14: Accelerate Image Processing using FPGA hardware",
-        "link": "contents/Module_14/Presentation14.pptx"
+        "link": "contents/Module 14_Accelerate Image Processing using FPGA hardware/Presentation14.pptx"
       }
     ],
 	

Original file line number	Diff line number	Diff line change
`@@ -24,17 +24,17 @@ var index =`
`24`	`24`	`{`
`25`	`25`	`"column": "modules",`
`26`	`26`	`"name": "Module 1: Introduction to Arm-based System on Chip Design",`
`27`		`- "link": "contents/Module_1/Presentation1.pptx"`
	`27`	`+ "link": "contents/Module 01_Introduction to Arm-based System on Chip Design/Presentation1.pptx"`
`28`	`28`	`},`
`29`	`29`	`{`
`30`	`30`	`"column": "exercises",`
`31`	`31`	`"name": "Quiz 1",`
`32`		`- "link": "contents/Module_1/Quiz1.docx"`
	`32`	`+ "link": "contents/Module 01_Introduction to Arm-based System on Chip Design/Quiz1.docx"`
`33`	`33`	`},`
`34`	`34`	`{`
`35`	`35`	`"column": "exercises",`
`36`	`36`	`"name": "Getting Started Guide",`
`37`		`- "link": "contents/Module_1/Getting_Started.docx"`
	`37`	`+ "link": "contents/Module 01_Introduction to Arm-based System on Chip Design/Getting_Started.docx"`
`38`	`38`	`}`
`39`	`39`	`],`
`40`	`40`
`@@ -43,12 +43,12 @@ var index =`
`43`	`43`	`{`
`44`	`44`	`"column": "modules",`
`45`	`45`	`"name": "Module 2: Arm and Arm Processors",`
`46`		`- "link": "contents/Module_2/Presentation2.pptx"`
	`46`	`+ "link": "contents/Module 02_Arm and Arm Processors/Presentation2.pptx"`
`47`	`47`	`},`
`48`	`48`	`{`
`49`	`49`	`"column": "exercises",`
`50`	`50`	`"name": "Quiz 2",`
`51`		`- "link": "contents/Module_2/Quiz2.docx"`
	`51`	`+ "link": "contents/Module 02_Arm and Arm Processors/Quiz2.docx"`
`52`	`52`	`}`
`53`	`53`	`],`
`54`	`54`
`@@ -57,7 +57,7 @@ var index =`
`57`	`57`	`{`
`58`	`58`	`"column": "modules",`
`59`	`59`	`"name": "Module 3: Armv7-A/R Instruction Set Architecture Overview Part 1",`
`60`		`- "link": "contents/Module_3/Presentation3.pptx"`
	`60`	`+ "link": "contents/Module 03_Armv7-AR Instruction Set Architecture Overview_part 1/Presentation3.pptx"`
`61`	`61`	`}`
`62`	`62`	`],`
`63`	`63`
`@@ -66,23 +66,23 @@ var index =`
`66`	`66`	`{`
`67`	`67`	`"column": "modules",`
`68`	`68`	`"name": "Module 4: Armv7-A/R Instruction Set Architecture Overview Part 2",`
`69`		`- "link": "contents/Module_4/Presentation4.pptx"`
	`69`	`+ "link": "contents/Module 04_Armv7-AR Instruction Set Architecture Overview Part 2/Presentation4.pptx"`
`70`	`70`	`},`
`71`	`71`	`{`
`72`	`72`	`"column": "exercises",`
`73`	`73`	`"name": "Quiz 3_4",`
`74`		`- "link": "contents/Module_4/Quiz3_4.docx"`
	`74`	`+ "link": "contents/Module 04_Armv7-AR Instruction Set Architecture Overview Part 2/Quiz3_4.docx"`
`75`	`75`	`},`
`76`	`76`	`{`
`77`	`77`	`"column": "exercises",`
`78`	`78`	`"name": "Lab 4: Programming a processor using Arm Assembly Language and C",`
`79`		`- "link": "contents/Module_4/Lab4_manual.docx"`
	`79`	`+ "link": "contents/Module 04_Armv7-AR Instruction Set Architecture Overview Part 2/Lab4_manual.docx"`
`80`	`80`	`},`
`81`	`81`
`82`	`82`	`{`
`83`	`83`	`"column": "files",`
`84`	`84`	`"name": "Lab 4 Files",`
`85`		`- "link": "contents/Module_4/lab_file/"`
	`85`	`+ "link": "contents/Module 04_Armv7-AR Instruction Set Architecture Overview Part 2/lab_file"`
`86`	`86`	`}`
`87`	`87`	`],`
`88`	`88`
`@@ -91,12 +91,12 @@ var index =`
`91`	`91`	`{`
`92`	`92`	`"column": "modules",`
`93`	`93`	`"name": "Module 5: Arm Cortex-A9 processor",`
`94`		`- "link": "contents/Module_5/Presentation5.pptx"`
	`94`	`+ "link": "contents/Module 05_Arm Cortex-A9 processor/Presentation5.pptx"`
`95`	`95`	`},`
`96`	`96`	`{`
`97`	`97`	`"column": "exercises",`
`98`	`98`	`"name": "Quiz 5",`
`99`		`- "link": "contents/Module_5/Quiz5.docx"`
	`99`	`+ "link": "contents/Module 05_Arm Cortex-A9 processor/Quiz5.docx"`
`100`	`100`	`}`
`101`	`101`	`],`
`102`	`102`
`@@ -105,12 +105,12 @@ var index =`
`105`	`105`	`{`
`106`	`106`	`"column": "modules",`
`107`	`107`	`"name": "Module 6: AMBA AXI4 Bus Architecture",`
`108`		`- "link": "contents/Module_6/Presentation6.pptx"`
	`108`	`+ "link": "contents/Module 06_Arm Cortex-A9 processor/Presentation6.pptx"`
`109`	`109`	`},`
`110`	`110`	`{`
`111`	`111`	`"column": "exercises",`
`112`	`112`	`"name": "Quiz 6",`
`113`		`- "link": "contents/Module_6/Quiz6.docx"`
	`113`	`+ "link": "contents/Module 06_Arm Cortex-A9 processor/Quiz6.docx"`
`114`	`114`	`}`
`115`	`115`	`],`
`116`	`116`
`@@ -119,23 +119,23 @@ var index =`
`119`	`119`	`{`
`120`	`120`	`"column": "modules",`
`121`	`121`	`"name": "Module 7: AXI4-Lite GPIO Peripheral and DDR memory controller",`
`122`		`- "link": "contents/Module_7/Presentation7.pptx"`
	`122`	`+ "link": "contents/Module 07_AXI4-Lite GPIO Peripheral and DDR memory controller/Presentation7.pptx"`
`123`	`123`	`},`
`124`	`124`	`{`
`125`	`125`	`"column": "exercises",`
`126`	`126`	`"name": "Quiz 7",`
`127`		`- "link": "contents/Module_7/Quiz7.docx"`
	`127`	`+ "link": "contents/Module 07_AXI4-Lite GPIO Peripheral and DDR memory controller/Quiz7.docx"`
`128`	`128`	`},`
`129`	`129`	`{`
`130`	`130`	`"column": "exercises",`
`131`	`131`	`"name": "Lab 7: AXI-Lite and GPIOs",`
`132`		`- "link": "contents/Module_7/Lab7_manual.docx"`
	`132`	`+ "link": "contents/Module 07_AXI4-Lite GPIO Peripheral and DDR memory controller/Lab7_manual.docx"`
`133`	`133`	`},`
`134`	`134`
`135`	`135`	`{`
`136`	`136`	`"column": "files",`
`137`	`137`	`"name": "Lab 7 Files",`
`138`		`- "link": "contents/Module_7/lab_file/"`
	`138`	`+ "link": "contents/Module 07_AXI4-Lite GPIO Peripheral and DDR memory controller/lab_file"`
`139`	`139`	`}`
`140`	`140`	`],`
`141`	`141`
`@@ -144,12 +144,12 @@ var index =`
`144`	`144`	`{`
`145`	`145`	`"column": "modules",`
`146`	`146`	`"name": "Module 8: AXI UART and AXI4-Stream Peripherals",`
`147`		`- "link": "contents/Module_8/Presentation8.pptx"`
	`147`	`+ "link": "contents/Module 08_AXI UART and AXI4-Stream Peripherals/Presentation8.pptx"`
`148`	`148`	`},`
`149`	`149`	`{`
`150`	`150`	`"column": "exercises",`
`151`	`151`	`"name": "Quiz 8",`
`152`		`- "link": "contents/Module_8/Quiz8.docx"`
	`152`	`+ "link": "contents/Module 08_AXI UART and AXI4-Stream Peripherals/Quiz8.docx"`
`153`	`153`	`}`
`154`	`154`	`],`
`155`	`155`
`@@ -158,22 +158,22 @@ var index =`
`158`	`158`	`{`
`159`	`159`	`"column": "modules",`
`160`	`160`	`"name": "Module 9: HDMI overview",`
`161`		`- "link": "contents/Module_9/Presentation9.pptx"`
	`161`	`+ "link": "contents/Module 09_HDMI overview/Presentation9.pptx"`
`162`	`162`	`},`
`163`	`163`	`{`
`164`	`164`	`"column": "exercises",`
`165`	`165`	`"name": "Quiz 9",`
`166`		`- "link": "contents/Module_9/Quiz9.docx"`
	`166`	`+ "link": "contents/Module 09_HDMI overview/Quiz9.docx"`
`167`	`167`	`},`
`168`	`168`	`{`
`169`	`169`	`"column": "exercises",`
`170`	`170`	`"name": "Lab 9: HDMI output",`
`171`		`- "link": "contents/Module_9/Lab9_manual.docx"`
	`171`	`+ "link": "contents/Module 09_HDMI overview/Lab9_manual.docx"`
`172`	`172`	`},`
`173`	`173`	`{`
`174`	`174`	`"column": "files",`
`175`	`175`	`"name": "Lab 9 Files",`
`176`		`- "link": "contents/Module_9/lab_file/"`
	`176`	`+ "link": "contents/Module 09_HDMI overview/lab_file"`
`177`	`177`	`}`
`178`	`178`	`],`
`179`	`179`
`@@ -182,12 +182,12 @@ var index =`
`182`	`182`	`{`
`183`	`183`	`"column": "modules",`
`184`	`184`	`"name": "Module 10: HDMI input peripheral",`
`185`		`- "link": "contents/Module_10/Presentation10.pptx"`
	`185`	`+ "link": "contents/Module 10_HDMI input peripheral/Presentation10.pptx"`
`186`	`186`	`},`
`187`	`187`	`{`
`188`	`188`	`"column": "exercises",`
`189`	`189`	`"name": "Quiz 10",`
`190`		`- "link": "contents/Module_10/Quiz10.docx"`
	`190`	`+ "link": "contents/Module 10_HDMI input peripheral/Quiz10.docx"`
`191`	`191`	`}`
`192`	`192`	`],`
`193`	`193`
`@@ -197,12 +197,12 @@ var index =`
`197`	`197`	`{`
`198`	`198`	`"column": "modules",`
`199`	`199`	`"name": "Module 11: System debugging",`
`200`		`- "link": "contents/Module_11/Presentation11.pptx"`
	`200`	`+ "link": "contents/Module 11_System debugging/Presentation11.pptx"`
`201`	`201`	`},`
`202`	`202`	`{`
`203`	`203`	`"column": "exercises",`
`204`	`204`	`"name": "Quiz 11",`
`205`		`- "link": "contents/Module_11/Quiz11.docx"`
	`205`	`+ "link": "contents/Module 11_System debugging/Quiz11.docx"`
`206`	`206`	`}`
`207`	`207`	`],`
`208`	`208`
`@@ -211,12 +211,12 @@ var index =`
`211`	`211`	`{`
`212`	`212`	`"column": "modules",`
`213`	`213`	`"name": "Module 12: Image-Processing Application",`
`214`		`- "link": "contents/Module_12/Presentation12.pptx"`
	`214`	`+ "link": "contents/Module 12_Image-Processing Application/Presentation12.pptx"`
`215`	`215`	`},`
`216`	`216`	`{`
`217`	`217`	`"column": "exercises",`
`218`	`218`	`"name": "Quiz 12",`
`219`		`- "link": "contents/Module_12/Quiz12.docx"`
	`219`	`+ "link": "contents/Module 12_Image-Processing Application/Quiz12.docx"`
`220`	`220`	`}`
`221`	`221`	`],`
`222`	`222`
`@@ -225,7 +225,7 @@ var index =`
`225`	`225`	`{`
`226`	`226`	`"column": "modules",`
`227`	`227`	`"name": "Module 13: Accelerate Image Processing using SIMD engine",`
`228`		`- "link": "contents/Module_13/Presentation13.pptx"`
	`228`	`+ "link": "contents/Module 13_Accelerate Image Processing using SIMD engine/Presentation13.pptx"`
`229`	`229`	`}`
`230`	`230`	`],`
`231`	`231`
`@@ -234,7 +234,7 @@ var index =`
`234`	`234`	`{`
`235`	`235`	`"column": "modules",`
`236`	`236`	`"name": "Module 14: Accelerate Image Processing using FPGA hardware",`
`237`		`- "link": "contents/Module_14/Presentation14.pptx"`
	`237`	`+ "link": "contents/Module 14_Accelerate Image Processing using FPGA hardware/Presentation14.pptx"`
`238`	`238`	`}`
`239`	`239`	`],`
`240`	`240`