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| 1 | +#include "chip_db_table_model.h" |
| 2 | + |
| 3 | +ChipDbTableModel::ChipDbTableModel(ChipDb *chipDb, QObject *parent) : |
| 4 | + QAbstractTableModel(parent) |
| 5 | +{ |
| 6 | + this->chipDb = chipDb; |
| 7 | +} |
| 8 | + |
| 9 | +int ChipDbTableModel::rowCount(const QModelIndex & /*parent*/) const |
| 10 | +{ |
| 11 | + return chipDb->size(); |
| 12 | +} |
| 13 | + |
| 14 | +int ChipDbTableModel::columnCount(const QModelIndex & /*parent*/) const |
| 15 | +{ |
| 16 | + return CHIP_PARAM_NUM; |
| 17 | +} |
| 18 | + |
| 19 | +QVariant ChipDbTableModel::data(const QModelIndex &index, int role) const |
| 20 | +{ |
| 21 | + if (role != Qt::DisplayRole) |
| 22 | + return QVariant(); |
| 23 | + |
| 24 | + switch (index.column()) |
| 25 | + { |
| 26 | + case CHIP_PARAM_NAME: |
| 27 | + return (*chipDb)[index.row()]->name; |
| 28 | + case CHIP_PARAM_PAGE_SIZE: |
| 29 | + return (*chipDb)[index.row()]->params[CHIP_PARAM_PAGE_SIZE]; |
| 30 | + case CHIP_PARAM_BLOCK_SIZE: |
| 31 | + return (*chipDb)[index.row()]->params[CHIP_PARAM_BLOCK_SIZE]; |
| 32 | + case CHIP_PARAM_SIZE: |
| 33 | + return (*chipDb)[index.row()]->params[CHIP_PARAM_SIZE]; |
| 34 | + case CHIP_PARAM_T_CS: |
| 35 | + return (*chipDb)[index.row()]->params[CHIP_PARAM_T_CS]; |
| 36 | + case CHIP_PARAM_T_CLS: |
| 37 | + return (*chipDb)[index.row()]->params[CHIP_PARAM_T_CLS]; |
| 38 | + case CHIP_PARAM_T_ALS: |
| 39 | + return (*chipDb)[index.row()]->params[CHIP_PARAM_T_ALS]; |
| 40 | + case CHIP_PARAM_T_CLR: |
| 41 | + return (*chipDb)[index.row()]->params[CHIP_PARAM_T_CLR]; |
| 42 | + case CHIP_PARAM_T_AR: |
| 43 | + return (*chipDb)[index.row()]->params[CHIP_PARAM_T_AR]; |
| 44 | + case CHIP_PARAM_T_WP: |
| 45 | + return (*chipDb)[index.row()]->params[CHIP_PARAM_T_WP]; |
| 46 | + case CHIP_PARAM_T_RP: |
| 47 | + return (*chipDb)[index.row()]->params[CHIP_PARAM_T_RP]; |
| 48 | + case CHIP_PARAM_T_DS: |
| 49 | + return (*chipDb)[index.row()]->params[CHIP_PARAM_T_DS]; |
| 50 | + case CHIP_PARAM_T_CH: |
| 51 | + return (*chipDb)[index.row()]->params[CHIP_PARAM_T_CH]; |
| 52 | + case CHIP_PARAM_T_CLH: |
| 53 | + return (*chipDb)[index.row()]->params[CHIP_PARAM_T_CLH]; |
| 54 | + case CHIP_PARAM_T_ALH: |
| 55 | + return (*chipDb)[index.row()]->params[CHIP_PARAM_T_ALH]; |
| 56 | + case CHIP_PARAM_T_WC: |
| 57 | + return (*chipDb)[index.row()]->params[CHIP_PARAM_T_WC]; |
| 58 | + case CHIP_PARAM_T_RC: |
| 59 | + return (*chipDb)[index.row()]->params[CHIP_PARAM_T_RC]; |
| 60 | + case CHIP_PARAM_T_REA: |
| 61 | + return (*chipDb)[index.row()]->params[CHIP_PARAM_T_REA]; |
| 62 | + } |
| 63 | + |
| 64 | + return QVariant(); |
| 65 | +} |
| 66 | + |
| 67 | +QVariant ChipDbTableModel::headerData(int section, Qt::Orientation orientation, |
| 68 | + int role) const |
| 69 | +{ |
| 70 | + if (!(role == Qt::DisplayRole && orientation == Qt::Horizontal)) |
| 71 | + return QVariant(); |
| 72 | + |
| 73 | + switch (section) |
| 74 | + { |
| 75 | + case CHIP_PARAM_NAME: return tr("Name"); |
| 76 | + case CHIP_PARAM_PAGE_SIZE: return tr("Page size"); |
| 77 | + case CHIP_PARAM_BLOCK_SIZE: return tr("Block size"); |
| 78 | + case CHIP_PARAM_SIZE: return tr("Size"); |
| 79 | + case CHIP_PARAM_T_CS: return tr("tCH"); |
| 80 | + case CHIP_PARAM_T_CLS: return tr("tCLS"); |
| 81 | + case CHIP_PARAM_T_ALS: return tr("tALS"); |
| 82 | + case CHIP_PARAM_T_CLR: return tr("tCLR"); |
| 83 | + case CHIP_PARAM_T_AR: return tr("tAR"); |
| 84 | + case CHIP_PARAM_T_WP: return tr("tWP"); |
| 85 | + case CHIP_PARAM_T_RP: return tr("tRP"); |
| 86 | + case CHIP_PARAM_T_DS: return tr("tDS"); |
| 87 | + case CHIP_PARAM_T_CH: return tr("tCH"); |
| 88 | + case CHIP_PARAM_T_CLH: return tr("tCLH"); |
| 89 | + case CHIP_PARAM_T_ALH: return tr("tALH"); |
| 90 | + case CHIP_PARAM_T_WC: return tr("tWC"); |
| 91 | + case CHIP_PARAM_T_RC: return tr("tRC"); |
| 92 | + case CHIP_PARAM_T_REA: return tr("tREA"); |
| 93 | + } |
| 94 | + |
| 95 | + return QVariant(); |
| 96 | +} |
| 97 | + |
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