Skip to content

Synthesis with fully Open Source tools #6

@alikates

Description

@alikates

Just FYI, there's an ongoing effort to develop a SystemVerilog frontend for Yosys, and one of the goals is to be able to synthesize the whole core_tile: povik/yosys-slang#31

Metadata

Metadata

Assignees

No one assigned

    Labels

    No labels
    No labels

    Type

    No type
    No fields configured for issues without a type.

    Projects

    No projects

    Milestone

    No milestone

    Relationships

    None yet

    Development

    No branches or pull requests

    Issue actions