diff --git a/includes/sargantana_icache_pkg.sv b/includes/sargantana_icache_pkg.sv index 3557dfe..4429d77 100644 --- a/includes/sargantana_icache_pkg.sv +++ b/includes/sargantana_icache_pkg.sv @@ -18,45 +18,59 @@ * under the License. */ +`ifdef PITON_SARG + `include "l15.tmp.h" +`endif + package sargantana_icache_pkg; import drac_pkg::*; //------------------------------------------------ Global Configuration -`ifdef ICACHE_32B - localparam int unsigned ICACHE_MEM_BLOCK = 32 ; //32 Bytes +// I$ line size in bits +// NOTE: I$ only supports 32/64-byte cache lines +`ifdef PITON_SARG + // When using Sargantana with OpenPiton, inherits the size from l15.tmp.h. + // NOTE: this is the responsibility of sims to enable the ICACHE_32B macro + // when CONFIG_L1I_CACHELINE_WIDTH equals 256. + localparam int unsigned ICACHELINE_SIZE = `CONFIG_L1I_CACHELINE_WIDTH; +`elsif ICACHE_32B + localparam int unsigned ICACHELINE_SIZE = 256; +`else + localparam int unsigned ICACHELINE_SIZE = 512; +`endif + +// I$ total size in KB +`ifdef PITON_SARG + localparam int unsigned ICACHE_SIZE = `CONFIG_L1I_SIZE/1024; `else - localparam int unsigned ICACHE_MEM_BLOCK = 64 ; //64 Bytes -`endif -localparam int unsigned ICACHE_SIZE = 16 ; // Total size in KB -localparam int unsigned ASSOCIATIVE = 4 ; // Associativity + localparam int unsigned ICACHE_SIZE = 16; +`endif + +// I$ associativity (number of ways) +`ifdef PITON_SARG + localparam int unsigned ICACHE_ASSOC = `CONFIG_L1I_ASSOCIATIVITY; +`else + localparam int unsigned ICACHE_ASSOC = 4; +`endif //------------------------------------------------ -localparam int unsigned SET_WIDHT = ICACHE_MEM_BLOCK*8 ; //- Cache line -localparam int unsigned ICACHE_DEPTH = (((ICACHE_SIZE*1024)/ASSOCIATIVE)/ICACHE_MEM_BLOCK) ; +localparam int unsigned SET_WIDHT = ICACHELINE_SIZE ; //- Cache line +localparam int unsigned ICACHE_DEPTH = (((ICACHE_SIZE*1024)/ICACHE_ASSOC)/(ICACHELINE_SIZE/8)) ; -localparam int unsigned ICACHE_N_WAY = ASSOCIATIVE ; //- Number of ways. -localparam int unsigned ICACHE_N_WAY_CLOG2 = $clog2( ICACHE_N_WAY ); -localparam int unsigned TAG_DEPTH = ICACHE_DEPTH ; //- . +localparam int unsigned ICACHE_N_WAY = ICACHE_ASSOC ; //- Number of ways. localparam int unsigned ADDR_WIDHT = $clog2( ICACHE_DEPTH ) ; //- icache Addr vector -localparam int unsigned TAG_ADDR_WIDHT = $clog2( TAG_DEPTH ) ; //- localparam int unsigned WAY_WIDHT = SET_WIDHT ; //- +localparam int unsigned ICACHE_INDEX_SIZE = $clog2(ICACHE_DEPTH) + $clog2(SET_WIDHT/8); -localparam int unsigned ICACHE_OFFSET_WIDTH = $clog2(SET_WIDHT/8); // align to 64bytes -localparam int unsigned ICACHE_INDEX_WIDTH = $clog2(ICACHE_DEPTH) + ICACHE_OFFSET_WIDTH; - -localparam int unsigned PPN_BIT_SIZE = drac_pkg::PHY_ADDR_SIZE - ICACHE_INDEX_WIDTH; -localparam int unsigned TAG_WIDHT = drac_pkg::PHY_ADDR_SIZE - ICACHE_INDEX_WIDTH; //- Tag size. -localparam int unsigned VADDR_SIZE = drac_pkg::VIRT_ADDR_SIZE; // TODO: check this - -localparam int unsigned ICACHE_TAG_WIDTH = TAG_WIDHT; -localparam int unsigned ICACHE_IDX_WIDTH = ADDR_WIDHT; +localparam int unsigned ICACHE_PPN_SIZE = drac_pkg::PHY_VIRT_MAX_ADDR_SIZE - ICACHE_INDEX_SIZE; +localparam int unsigned ICACHE_VPN_SIZE = drac_pkg::PHY_VIRT_MAX_ADDR_SIZE - ICACHE_INDEX_SIZE; `ifdef FETCH_ONE_INST localparam int unsigned FETCH_WIDHT = riscv_pkg::INST_SIZE; `else - localparam int unsigned FETCH_WIDHT = drac_pkg::ICACHELINE_SIZE; + localparam int unsigned FETCH_WIDHT = ICACHELINE_SIZE; `endif //------------------------------------------------------- exception @@ -70,12 +84,16 @@ typedef struct packed { //--------------------------------------------------------- iCache +typedef logic [ICACHELINE_SIZE-1:0] icache_line_t; +typedef reg [ICACHELINE_SIZE-1:0] icache_line_reg_t; +typedef logic [ICACHE_INDEX_SIZE-1:0] icache_idx_t; +typedef logic [ICACHE_VPN_SIZE-1:0] icache_vpn_t; typedef struct packed { logic valid ; // we request a new word logic kill ; // kill the current request - drac_pkg::icache_idx_t idx; - drac_pkg::icache_vpn_t vpn; + icache_idx_t idx; + icache_vpn_t vpn; } ireq_i_t; typedef struct packed { @@ -100,15 +118,15 @@ typedef enum logic[2:0] {NO_REQ, //------------------------------------------------------ //------------------------------------------------- MMU typedef struct packed { - logic miss ; - logic ptw_v ; // ptw response valid - logic [PPN_BIT_SIZE-1:0] ppn ; // physical address in - logic xcpt ; // exception occurred during fetch + logic miss ; + logic ptw_v ; // ptw response valid + logic [ICACHE_PPN_SIZE-1:0] ppn ; // physical address in + logic xcpt ; // exception occurred during fetch } tresp_i_t; typedef struct packed { logic valid ; // address translation request - drac_pkg::icache_vpn_t vpn ; + icache_vpn_t vpn ; } treq_o_t; @@ -117,7 +135,7 @@ typedef enum logic[2:0] {NO_REQ, typedef struct packed { logic valid ; //- valid invalidation and - logic [ICACHE_INDEX_WIDTH-1:0] paddr ; //- index to invalidate + logic [ICACHE_INDEX_SIZE-1:0] paddr ; //- index to invalidate } inv_t; typedef struct packed { diff --git a/rtl/sargantana_top_icache.sv b/rtl/sargantana_top_icache.sv index d9f6c04..41a7bcc 100644 --- a/rtl/sargantana_top_icache.sv +++ b/rtl/sargantana_top_icache.sv @@ -25,23 +25,19 @@ module sargantana_top_icache parameter logic KILL_RESP = 1'b1, parameter logic LINES_256 = 1'b0, - parameter int unsigned ICACHE_MEM_BLOCK = 64, - parameter int unsigned PADDR_SIZE = 40, //! Physical address size. + parameter int unsigned ICACHE_SIZE = 16, // Total size in KB + parameter int unsigned ASSOCIATIVE = 4, // Associativity + parameter int unsigned ICACHE_MEM_BLOCK = 64, // Cache line size in Bytes + parameter int unsigned PADDR_SIZE = 40, //! Physical address size. + parameter int unsigned ADDR_SIZE = 40, //! Maximum between physical address size and virtual address size. + parameter int unsigned FETCH_WIDHT = 128, + parameter int unsigned ITLB_CYCLE = 0, //! Pick cycle to do asynch ITLB transaction {0, 1} - parameter int unsigned ADDR_SIZE = 40, //! Maximum between physical address size and virtual address size. - parameter int unsigned IDX_BITS_SIZE = 12, //! Bits used for idx - parameter int unsigned VPN_BITS_SIZE = ADDR_SIZE - IDX_BITS_SIZE, //! Bits used for vpn - - parameter int unsigned FETCH_WIDHT = 128, - - parameter int unsigned ITLB_CYCLE = 0, //! Pick cycle to do asynch ITLB transaction {0, 1} - - localparam int unsigned ICACHE_SIZE = 16, // Total size in KB - localparam int unsigned ASSOCIATIVE = 4, // Associativity - - //localparam int unsigned WORD_SIZE = 64, //- Word size in a set. localparam int unsigned SET_WIDHT = ICACHE_MEM_BLOCK*8, //- Cache line localparam int unsigned ICACHE_DEPTH = (((ICACHE_SIZE*1024)/ASSOCIATIVE)/ICACHE_MEM_BLOCK), + localparam int unsigned ICACHE_OFFSET_WIDTH = $clog2(SET_WIDHT/8), // align to 64bytes + localparam int unsigned IDX_BITS_SIZE = $clog2(ICACHE_DEPTH) + ICACHE_OFFSET_WIDTH, + localparam int unsigned VPN_BITS_SIZE = ADDR_SIZE - IDX_BITS_SIZE, //! Bits used for vpn localparam int unsigned ICACHE_N_WAY = ASSOCIATIVE, //- Number of ways. //localparam int unsigned ICACHE_N_WAY_CLOG2 = $clog2( ICACHE_N_WAY ), @@ -50,12 +46,9 @@ module sargantana_top_icache localparam int unsigned TAG_ADDR_WIDHT = $clog2( TAG_DEPTH ), //- localparam int unsigned WAY_WIDHT = SET_WIDHT, //- - localparam int unsigned ICACHE_OFFSET_WIDTH = $clog2(SET_WIDHT/8), // align to 64bytes - localparam int unsigned ICACHE_INDEX_WIDTH = $clog2(ICACHE_DEPTH) + ICACHE_OFFSET_WIDTH, - //localparam int unsigned BLOCK_ADDR_SIZE = ADDR_SIZE - ICACHE_OFFSET_WIDTH, - localparam int unsigned PPN_BIT_SIZE = ADDR_SIZE - ICACHE_INDEX_WIDTH, - localparam int unsigned TAG_WIDHT = ADDR_SIZE - ICACHE_INDEX_WIDTH, //- Tag size. + localparam int unsigned PPN_BIT_SIZE = ADDR_SIZE - IDX_BITS_SIZE, + localparam int unsigned TAG_WIDHT = ADDR_SIZE - IDX_BITS_SIZE, //- Tag size. localparam int unsigned ICACHE_TAG_WIDTH = TAG_WIDHT, localparam int unsigned ICACHE_IDX_WIDTH = ADDR_WIDHT @@ -99,7 +92,7 @@ module sargantana_top_icache input logic ifill_resp_ack_i , // IFILL request was received input logic [SET_WIDHT-1:0] ifill_resp_data_i , // Full cache line input logic ifill_resp_inv_valid_i , //- valid invalidation and - input logic [ICACHE_INDEX_WIDTH-1:0] ifill_resp_inv_paddr_i , //- index to invalidate + input logic [IDX_BITS_SIZE-1:0] ifill_resp_inv_paddr_i , //- index to invalidate output logic icache_ifill_req_valid_o , // valid request //output logic [$clog2(ICACHE_N_WAY)-1:0] icache_ifill_req_way_o , // way to replace @@ -241,7 +234,7 @@ endgenerate //- Split virtual address into index and offset to address cache arrays. assign vaddr_index = valid_inv ? ifill_resp_inv_paddr_i[ICACHE_IDX_WIDTH:1] : - idx_d[ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH]; + idx_d[IDX_BITS_SIZE-1:ICACHE_OFFSET_WIDTH]; //vaddr_in[ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH]; assign cline_tag_d = mmu_tresp_ppn ; @@ -262,7 +255,7 @@ end //--------------------------------------------------------------------- //------------------------------------------------------ IFILL request. -assign icache_ifill_req_paddr_o = {cline_tag_d,idx_q[11:ICACHE_OFFSET_WIDTH],{{ICACHE_OFFSET_WIDTH}{1'b0}}}; +assign icache_ifill_req_paddr_o = {cline_tag_d,idx_q[IDX_BITS_SIZE-1:ICACHE_OFFSET_WIDTH],{{ICACHE_OFFSET_WIDTH}{1'b0}}}; assign icache_ifill_req_valid_o = ifill_req_valid && !ireq_kill_d ; diff --git a/rtl/wrapper_sargantana_top_icache.sv b/rtl/wrapper_sargantana_top_icache.sv index aaaa08a..58605ae 100644 --- a/rtl/wrapper_sargantana_top_icache.sv +++ b/rtl/wrapper_sargantana_top_icache.sv @@ -51,11 +51,12 @@ sargantana_top_icache #( .KILL_RESP (KILL_RESP), .LINES_256 (LINES_256), - .ICACHE_MEM_BLOCK (ICACHE_MEM_BLOCK), + .ICACHE_SIZE (ICACHE_SIZE), + .ICACHE_MEM_BLOCK (ICACHELINE_SIZE), + .ASSOCIATIVE (ICACHE_ASSOC), + .PADDR_SIZE (drac_pkg::PHY_ADDR_SIZE), .ADDR_SIZE (drac_pkg::PHY_ADDR_SIZE), - .IDX_BITS_SIZE ($bits(drac_pkg::icache_idx_t)), - .VPN_BITS_SIZE ($bits(drac_pkg::icache_vpn_t)), .FETCH_WIDHT (FETCH_WIDHT) ) icache ( `ifdef INTEL_PHYSICAL_MEM_CTRL