Fix index_int verilog prim

... for non-var vecs

Author: leonschoorl

clash-lib/src/Clash/Primitives/Sized/Vector.hs

@@ -32,6 +32,7 @@ import           GHC.Stack                          (HasCallStack)
 
 import           Clash.Backend
   (Backend, hdlTypeErrValue, expr, blockDecl)
+import           Clash.Core.TermInfo                (isVar)
 import           Clash.Core.Type
   (Type(LitTy), LitTy(NumTy), coreView)
 import           Clash.Netlist.BlackBox             (isLiteral)
@@ -241,21 +242,21 @@ foldTF' args =
   error $ "Unexpected number of arguments: " ++ show (length (bbInputs args))
 
 indexIntVerilog ::  BlackBoxFunction
-indexIntVerilog _isD _primName args _ty = return ((meta,) <$> bb)
+indexIntVerilog _isD _primName args _ty = return bb
  where
-  meta = emptyBlackBoxMeta{bbKind=bbKi}
-
-  bbKi = case args of
-    [_nTy,_aTy,_kn,_v,Left ix]
-      | isLiteral ix -> TExpr
-    _ -> TDecl
+  meta bbKi = emptyBlackBoxMeta{bbKind=bbKi}
 
   bb = case args of
+    [_nTy,_aTy,_kn,Left v,Left ix] | isLiteral ix && isVar v ->
+      Right (meta TExpr, BBFunction "Clash.Primitives.Sized.Vector.indexIntVerilogTF" 0 indexIntVerilogTF)
     [_nTy,_aTy,_kn,_v,Left ix] | isLiteral ix ->
-      Right (BBFunction "Clash.Primitives.Sized.Vector.indexIntVerilogTF" 0 indexIntVerilogTF)
+      case runParse (pack (I.unindent bbTextLitIx)) of
+        Success t -> Right (meta TDecl, BBTemplate t)
+        _         -> Left "internal error: parse fail"
+
     _ ->
-      BBTemplate <$> case runParse (pack (I.unindent bbText)) of
-        Success t -> Right t
+      case runParse (pack (I.unindent bbText)) of
+        Success t -> Right (meta TDecl, BBTemplate t)
         _         -> Left "internal error: parse fail"
 
   bbText = [I.i|
@@ -270,6 +271,12 @@ indexIntVerilog _isD _primName args _ty = return ((meta,) <$> bb)
     assign ~RESULT = ~SYM[0][~ARG[2]];~ELSEassign ~RESULT = ~ERRORO;~FI
     // index end|]
 
+  bbTextLitIx = [I.i|
+    // index lit begin
+    ~IF~SIZE[~TYP[1]]~THENassign ~RESULT = ~VAR[vec][1][~SIZE[~TYP[1]]-1-~LIT[2]*~SIZE[~TYPO] -: ~SIZE[~TYPO]];~ELSEassign ~RESULT = ~ERRORO;~FI
+    // index lit end|]
+
+
 indexIntVerilogTF :: TemplateFunction
 indexIntVerilogTF = TemplateFunction used valid indexIntVerilogTemplate
  where

tests/shouldwork/Vector/IndexInt2.hs

@@ -13,11 +13,11 @@ import Clash.Explicit.Testbench
 
 import Clash.Netlist.Types
 
-topEntity :: Vec 4 Bool -> Signed 8 -> (Bool,Bool,Bool)
+topEntity :: Vec 4 (Unsigned 4) -> Signed 8 -> (Unsigned 4,Unsigned 4,Unsigned 4)
 topEntity xs ix0 =
   ( xs !! ix0    -- non-constant index
-  , xs !! ix1    -- constant index, vec is a var
-  , (tail xs :< False) !! ix1 -- constant index, vec is not a var
+  , xs !! ix1    -- constant index, vec is a Var
+  , (tail xs :< 0xe) !! ix1 -- constant index, vec is an expression
   )
   where
     ix1 :: Signed 8
@@ -27,9 +27,9 @@ topEntity xs ix0 =
 testBench :: Signal System Bool
 testBench = done
  where
-  testVecs       = stimuliGenerator clk rst (map unpack $ 0b0010 :> 0b0100 :> 0b1000 :> Nil)
+  testVecs       = stimuliGenerator clk rst (map unpack $ 0x0010 :> 0x0100 :> 0x1000 :> Nil)
   testIxs        = stimuliGenerator clk rst (2 :> 1 :> 0 :> Nil)
-  output         = map unpack $ 0b101 :> 0b110 :> 0b100 :> Nil
+  output         = map unpack $ 0x101 :> 0x110 :> 0x100 :> Nil
   expectedOutput = outputVerifier' clk rst output
   done           = expectedOutput (topEntity <$> testVecs <*> testIxs)
   clk            = tbSystemClockGen (not <$> done)