Passing User Arguments to Verilog Code

This repository demonstrates how to pass runtime arguments (plusargs) from the simulator command line into a Verilog testbench using the $value$plusargs system task.

Plusargs allow you to change simulation parameters without modifying the source code, making testbenches more flexible and reusable.

---

📁 Files in This Repository

File	Description
user_args.v	Verilog testbench that demonstrates reading integer and real arguments using $value$plusargs.
run.do (optional)	ModelSim/Questa simulation script to compile, simulate, add waves, and run.

---