Update MWDT clock management

Author: bugadani

esp-hal/src/soc/esp32c2/clocks.rs

@@ -643,3 +643,20 @@ fn configure_timg0_calibration_clock_impl(
         })
     });
 }
+
+// TIMG0_WDT_CLOCK
+
+fn enable_timg0_wdt_clock_impl(_clocks: &mut ClockTree, _en: bool) {
+    // No separate clock control enable bit.
+}
+
+fn configure_timg0_wdt_clock_impl(
+    _clocks: &mut ClockTree,
+    _old_selector: Option<Timg0WdtClockConfig>,
+    new_selector: Timg0WdtClockConfig,
+) {
+    TIMG0::regs().wdtconfig0().modify(|_, w| {
+        w.wdt_use_xtal()
+            .bit(new_selector == Timg0WdtClockConfig::XtalClk)
+    });
+}

esp-hal/src/soc/esp32c3/clocks.rs

@@ -571,6 +571,23 @@ fn configure_timg0_calibration_clock_impl(
     });
 }
 
+// TIMG0_WDT_CLOCK
+
+fn enable_timg0_wdt_clock_impl(_clocks: &mut ClockTree, _en: bool) {
+    // No separate clock control enable bit.
+}
+
+fn configure_timg0_wdt_clock_impl(
+    _clocks: &mut ClockTree,
+    _old_selector: Option<Timg0WdtClockConfig>,
+    new_selector: Timg0WdtClockConfig,
+) {
+    TIMG0::regs().wdtconfig0().modify(|_, w| {
+        w.wdt_use_xtal()
+            .bit(new_selector == Timg0WdtClockConfig::XtalClk)
+    });
+}
+
 // TIMG1_FUNCTION_CLOCK
 
 fn enable_timg1_function_clock_impl(_clocks: &mut ClockTree, en: bool) {
@@ -611,3 +628,20 @@ fn configure_timg1_calibration_clock_impl(
         })
     });
 }
+
+// TIMG1_WDT_CLOCK
+
+fn enable_timg1_wdt_clock_impl(_clocks: &mut ClockTree, _en: bool) {
+    // No separate clock control enable bit.
+}
+
+fn configure_timg1_wdt_clock_impl(
+    _clocks: &mut ClockTree,
+    _old_selector: Option<Timg0WdtClockConfig>,
+    new_selector: Timg0WdtClockConfig,
+) {
+    TIMG1::regs().wdtconfig0().modify(|_, w| {
+        w.wdt_use_xtal()
+            .bit(new_selector == Timg0WdtClockConfig::XtalClk)
+    });
+}

esp-hal/src/soc/esp32c6/clocks.rs

@@ -587,6 +587,30 @@ fn configure_timg0_calibration_clock_impl(
     });
 }
 
+// TIMG0_WDT_CLOCK
+
+fn enable_timg0_wdt_clock_impl(_clocks: &mut ClockTree, en: bool) {
+    PCR::regs()
+        .timergroup0_wdt_clk_conf()
+        .modify(|_, w| w.tg0_wdt_clk_en().bit(en));
+}
+
+fn configure_timg0_wdt_clock_impl(
+    _clocks: &mut ClockTree,
+    _old_selector: Option<Timg0WdtClockConfig>,
+    new_selector: Timg0WdtClockConfig,
+) {
+    PCR::regs()
+        .timergroup0_wdt_clk_conf()
+        .modify(|_, w| unsafe {
+            w.tg0_wdt_clk_sel().bits(match new_selector {
+                Timg0WdtClockConfig::XtalClk => 0,
+                Timg0WdtClockConfig::PllF80m => 1,
+                Timg0WdtClockConfig::RcFastClk => 2,
+            })
+        });
+}
+
 // TIMG1_FUNCTION_CLOCK
 
 fn enable_timg1_function_clock_impl(_clocks: &mut ClockTree, en: bool) {
@@ -632,3 +656,27 @@ fn configure_timg1_calibration_clock_impl(
         })
     });
 }
+
+// TIMG1_WDT_CLOCK
+
+fn enable_timg1_wdt_clock_impl(_clocks: &mut ClockTree, en: bool) {
+    PCR::regs()
+        .timergroup1_wdt_clk_conf()
+        .modify(|_, w| w.tg1_wdt_clk_en().bit(en));
+}
+
+fn configure_timg1_wdt_clock_impl(
+    _clocks: &mut ClockTree,
+    _old_selector: Option<Timg0WdtClockConfig>,
+    new_selector: Timg0WdtClockConfig,
+) {
+    PCR::regs()
+        .timergroup1_wdt_clk_conf()
+        .modify(|_, w| unsafe {
+            w.tg1_wdt_clk_sel().bits(match new_selector {
+                Timg0WdtClockConfig::XtalClk => 0,
+                Timg0WdtClockConfig::PllF80m => 1,
+                Timg0WdtClockConfig::RcFastClk => 2,
+            })
+        });
+}

esp-hal/src/soc/esp32h2/clocks.rs

@@ -430,6 +430,30 @@ fn configure_timg0_calibration_clock_impl(
     });
 }
 
+// TIMG0_WDT_CLOCK
+
+fn enable_timg0_wdt_clock_impl(_clocks: &mut ClockTree, en: bool) {
+    PCR::regs()
+        .timergroup0_wdt_clk_conf()
+        .modify(|_, w| w.tg0_wdt_clk_en().bit(en));
+}
+
+fn configure_timg0_wdt_clock_impl(
+    _clocks: &mut ClockTree,
+    _old_selector: Option<Timg0WdtClockConfig>,
+    new_selector: Timg0WdtClockConfig,
+) {
+    PCR::regs()
+        .timergroup0_wdt_clk_conf()
+        .modify(|_, w| unsafe {
+            w.tg0_wdt_clk_sel().bits(match new_selector {
+                Timg0WdtClockConfig::XtalClk => 0,
+                Timg0WdtClockConfig::RcFastClk => 1,
+                Timg0WdtClockConfig::PllF48m => 2,
+            })
+        });
+}
+
 // TIMG1_FUNCTION_CLOCK
 
 fn enable_timg1_function_clock_impl(_clocks: &mut ClockTree, en: bool) {
@@ -475,3 +499,27 @@ fn configure_timg1_calibration_clock_impl(
         })
     });
 }
+
+// TIMG1_WDT_CLOCK
+
+fn enable_timg1_wdt_clock_impl(_clocks: &mut ClockTree, en: bool) {
+    PCR::regs()
+        .timergroup1_wdt_clk_conf()
+        .modify(|_, w| w.tg1_wdt_clk_en().bit(en));
+}
+
+fn configure_timg1_wdt_clock_impl(
+    _clocks: &mut ClockTree,
+    _old_selector: Option<Timg0WdtClockConfig>,
+    new_selector: Timg0WdtClockConfig,
+) {
+    PCR::regs()
+        .timergroup1_wdt_clk_conf()
+        .modify(|_, w| unsafe {
+            w.tg1_wdt_clk_sel().bits(match new_selector {
+                Timg0WdtClockConfig::XtalClk => 0,
+                Timg0WdtClockConfig::RcFastClk => 1,
+                Timg0WdtClockConfig::PllF48m => 2,
+            })
+        });
+}