Support for Ethernet peripheral (ESP32 / ESP32-P4)

[stef-steos-engineering]

Motivations

For some projects on ESP32 I am now stuck with esp-idf-{sys,hal,svc} for Ethernet support. I would like to know if there are plans (or if there ever were plans, but they were discarded) to support the Ethernet peripheral. Since the P4 will have Ethernet again and the IP is similar, maybe there will be renewed interest for Ethernet functionality?

Solution

An Ethernet driver for the ESP32 (and future P4) in the ESP-HAL.

Alternatives

Sticking to esp-idf-svc

[mithilP007]

Implementation Approach for Ethernet/RMII Support

I'm proposing to implement Ethernet peripheral support for ESP32 and ESP32-P4 chips. Here's a comprehensive approach:

Architecture Overview

Module Structure:

esp-hal/src/ethernet/
├── mod.rs           # Main ethernet module
├── rmii.rs          # RMII interface implementation  
├── emac.rs          # Ethernet MAC controller
└── descriptors.rs   # DMA descriptor management

Key Components

1. RMII Interface (rmii.rs)

• Pin configuration for RMII signals (TXD[0:1], RXD[0:1], TX_EN, RX_DV, REF_CLK, MDC, MDIO)
• Clock configuration (50MHz REF_CLK)
• PHY management via MDIO/MDC

2. Ethernet MAC (emac.rs)

• MAC address configuration
• Frame transmission/reception
• Flow control
• CRC handling

3. DMA Descriptor Management (descriptors.rs)

• TX/RX descriptor ring buffers
• Buffer management
• Scatter-gather DMA support

Implementation Plan

Phase 1: Basic RMII Interface

pub struct Rmii<'d> {
    _peripheral: PeripheralRef<'d, EMAC>,
    tx_en: Output<'d>,
    txd0: Output<'d>,
    txd1: Output<'d>,
    // ... other pins
}

impl<'d> Rmii<'d> {
    pub fn new(
        peripheral: impl Peripheral<P = EMAC> + 'd,
        ref_clk: impl Peripheral<P = impl OutputPin> + 'd,
        tx_en: impl Peripheral<P = impl OutputPin> + 'd,
        // ... other pins
    ) -> Self {
        // Pin configuration
        // Clock setup
        // Initialize EMAC peripheral
    }
}

Phase 2: MAC Layer

pub struct EthernetMAC<'d, DM: DriverMode> {
    rmii: Rmii<'d>,
    mac_addr: [u8; 6],
    _mode: PhantomData<DM>,
}

impl<'d> EthernetMAC<'d, Blocking> {
    pub fn new(rmii: Rmii<'d>, mac_addr: [u8; 6]) -> Self;
    pub fn send_frame(&mut self, data: &[u8]) -> Result<(), Error>;
    pub fn receive_frame(&mut self, buffer: &mut [u8]) -> Result<usize, Error>;
}

Phase 3: DMA Integration

• Implement descriptor chains for efficient packet handling
• Support for scatter-gather operations
• Interrupt-driven async support

Register Configuration

Based on ESP32 TRM and ESP-IDF implementation:

• EMAC control registers
• DMA configuration
• PHY management registers
• Clock and reset control

Chip Support

ESP32:

• Internal EMAC controller
• Supports RMII interface
• Requires external PHY (LAN8720, RTL8201, etc.)

ESP32-P4:

• Similar EMAC architecture
• Updated register layout (to be verified)

Testing Strategy

1. Unit tests: Register configuration, descriptor management
2. Integration tests: Loopback testing, frame transmission
3. Hardware tests: Actual PHY communication (by maintainers/users)

Dependencies & References

• ESP32 Technical Reference Manual (EMAC chapter)
• ESP-IDF EMAC HAL: https://github.com/espressif/esp-idf/tree/master/components/esp_eth
• IEEE 802.3 RMII specification

Example Usage

let peripherals = esp_hal::init(Config::default());
let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);

// Configure RMII pins
let rmii = Rmii::new(
    peripherals.EMAC,
    io.pins.gpio0,  // REF_CLK
    io.pins.gpio21, // TX_EN
    io.pins.gpio19, // TXD0
    io.pins.gpio22, // TXD1
    io.pins.gpio25, // RXD0
    io.pins.gpio26, // RXD1
    io.pins.gpio27, // RX_DV
    io.pins.gpio23, // MDC
    io.pins.gpio18, // MDIO
);

let mut eth = EthernetMAC::new(rmii, [0x02, 0x00, 0x00, 0x12, 0x34, 0x56]);
eth.init_phy(PhyAddress::Addr1)?;
eth.send_frame(&frame_data)?;

Current Status

I'll be submitting a PR with the initial implementation focusing on:

1. Basic RMII pin configuration
2. EMAC register definitions
3. Blocking mode MAC operations
4. DMA descriptor management

Async support and advanced features can be added in subsequent PRs.

Open Questions

1. Should we support both internal and external MAC (SPI Ethernet modules)?
2. PHY driver abstraction - should it be generic or specific?
3. Integration with smoltcp or other network stacks?

I'll start working on this implementation and welcome feedback from maintainers. @MabezDev @jessebraham - would this approach align with esp-hal's architecture?

[Dominaezzz]

Does anyone on the team have something like this to run a QA test? Because I can't imagine HIL testing this with the current setup.

[bugadani]

I have ESP32 Ethernet Devkit and P4 Function EV board only.

[owenthewizard]

@Dominaezzz I have a WT32-ETH01 (along with a couple fake versions) and a LilyGO T-ETH Lite.

I'd be happy to run any tests.