Merge tag 'intel-media-24.4.4' into fancybits-intel-media-24.4.4

Author: tmm1

CMakeLists.txt

@@ -20,7 +20,7 @@
 
 cmake_minimum_required(VERSION 3.5)
 project(IntelMediaDriver)
-set(MEDIA_VERSION "24.4.2${MEDIA_VERSION_EXTRA}" CACHE STRING "" FORCE)
+set(MEDIA_VERSION "24.4.4${MEDIA_VERSION_EXTRA}" CACHE STRING "" FORCE)
 
 
 

README.md

@@ -98,7 +98,7 @@ Media driver supports below two builds
 - **Full Feature Build** is ***default*** driver build, which supports all feature by hardware accelerator and close source shaders(media kernel binaries). Most of OSVs(like RHEL/SUSE/fedora) are using this build.
 - **Free Kernel Build**, enables fully open source shaders(media kernels) and hardware features but the features would be limited.
 
-About Ubuntu/Debian OSV, they provide [intel-media-va-driver-non-free](https://packages.ubuntu.com/disco/intel-media-va-driver-non-free) (Full feature build) and [intel-media-va-driver](https://packages.ubuntu.com/disco/intel-media-va-driver) (Free kernel build) two packages. ***Free*** here means open source kernel but not related to fee need to pay. You could refer to [build options](https://github.com/intel/media-driver?tab=readme-ov-file#build-options) for more detail.
+About Ubuntu/Debian OSV, they provide [intel-media-va-driver-non-free](https://packages.ubuntu.com/search?keywords=intel-media-driver-non-free&searchon=sourcenames) (Full feature build) and [intel-media-va-driver](https://packages.ubuntu.com/search?keywords=intel-media-driver&searchon=sourcenames) (Free kernel build) two packages. ***Free*** here means open source kernel but not related to fee need to pay. You could refer to [build options](https://github.com/intel/media-driver?tab=readme-ov-file#build-options) for more detail.
 
 If you are looking forward to have a big table to share media component features on these two builds, below tables are good referene for your information.
 

cmrtlib/linux/hardware/cm_device_os.cpp

@@ -483,18 +483,20 @@ CmDevice_RT::CmDevice_RT(
     m_deviceInUmd(nullptr),
     m_cmCreated(true),
     m_vaDisplay(vaDisplay),
+    m_drmIndex(0),
+    m_fvaCmExtSendReqMsg(nullptr),
 #ifdef ANDROID
     m_display(nullptr),
 #endif
-    m_drmIndex(0),
-    m_fvaCmExtSendReqMsg(nullptr),
     m_gtpinEnabled(false),
     m_gtpinBufferUP0(nullptr),
     m_gtpinBufferUP1(nullptr),
     m_gtpinBufferUP2(nullptr),
     m_createOption(createOption),
-    m_driverStoreEnabled(0),
-    m_driFileDescriptor(0)
+#if !defined(ANDROID)
+    m_driFileDescriptor(0),
+#endif
+    m_driverStoreEnabled(0)
 {
 
     // New Surface Manager

media_common/agnostic/common/hw/mhw_mi.h

@@ -281,11 +281,13 @@ typedef struct _MHW_MI_ATOMIC_PARAMS
 typedef struct _MHW_MI_SEMAPHORE_WAIT_PARAMS
 {
     PMOS_RESOURCE               presSemaphoreMem;        // Semaphore memory Resource
+    uint64_t                    gpuVirtualAddress;       // Semaphore memory Resource
     uint32_t                    dwResourceOffset;
     bool                        bRegisterPollMode;
     bool                        bPollingWaitMode;
     uint32_t                    dwCompareOperation;
     uint32_t                    dwSemaphoreData;
+    bool                        b64bComparEnableWithGPR;
     MHW_COMMON_MI_SEMAPHORE_COMPARE_OPERATION       CompareOperation;
 }MHW_MI_SEMAPHORE_WAIT_PARAMS, *PMHW_MI_SEMAPHORE_WAIT_PARAMS;
 

media_common/agnostic/common/hw/mhw_state_heap.h

@@ -253,6 +253,7 @@ typedef struct _MHW_KERNEL_PARAM
     void    *pExtra;                         //!< Kernel parameter
     uint8_t *pBinary;                        //!< Pointer to kernel binary
     int32_t iSize;                          //!< Kernel size
+    int32_t iPaddingSize;                   //!< Padding size  
     int32_t iGrfCount;                      //!< Number of registers
     int32_t iBTCount;                       //!< Number of BT entries
     int32_t iThreadCount;                   //!< Number of threads (max)

media_common/agnostic/common/os/mos_os.h

@@ -50,6 +50,7 @@
 #include "mos_oca_interface.h"
 #include "mos_cache_manager.h"
 
+class MhwInterfacesNext;
 #define MOS_NAL_UNIT_LENGTH                 4
 #define MOS_NAL_UNIT_STARTCODE_LENGTH       3
 #define MOS_MAX_PATH_LENGTH                 256
@@ -254,12 +255,15 @@ typedef int32_t MOS_SUBMISSION_TYPE;
 #define EXTRA_PADDING_NEEDED                            4096
 #define MEDIA_CMF_UNCOMPRESSED_WRITE                    0xC
 
+struct _MHW_BATCH_BUFFER;
+typedef struct _MHW_BATCH_BUFFER MHW_BATCH_BUFFER, * PMHW_BATCH_BUFFER;
 //!
 //! \brief Structure to command buffer
 //!
 typedef struct _MOS_COMMAND_BUFFER
 {
     MOS_RESOURCE        OsResource;                 //!< OS Resource
+    PMHW_BATCH_BUFFER   syncMhwBatchBuffer;         //!< Pointer to sync mhw batch buffer
 
     // Common fields
     uint32_t            *pCmdBase;                   //!< Base    address (CPU)
@@ -573,7 +577,7 @@ struct MosStreamState
     uint32_t dwEnableMediaSoloFrameNum          = 0;        //!< The frame number at which MediaSolo will be enabled, 0 is not valid.
     int32_t  bSoloInUse                         = 0;        //!< Flag to indicate if MediaSolo is enabled
 #endif  // MOS_MEDIASOLO_SUPPORTED
-
+     MhwInterfacesNext  *mhwInterface           = nullptr;
 };
 
 // OS agnostic MOS objects
@@ -2056,6 +2060,8 @@ typedef struct _MOS_INTERFACE
 
     bool (*pfnGetCacheSetting)(MOS_COMPONENT id, uint32_t feature, bool bOut, ENGINE_TYPE engineType, MOS_CACHE_ELEMENT &element, bool isHeapSurf);
 
+    bool (* pfnIsGpuSyncByCmd) (PMOS_INTERFACE osInterface);
+
     // Virtual Engine related
     int32_t                         bSupportVirtualEngine;                        //!< Enable virtual engine flag
     int32_t                         bUseHwSemaForResSyncInVE;                     //!< Flag to indicate if UMD need to send HW sema cmd under this OS when there is a resource sync need with Virtual Engine interface 
@@ -2094,6 +2100,7 @@ typedef struct _MOS_INTERFACE
 
     //!< os interface extension
     void                            *pOsExt;
+    MhwInterfacesNext               *mhwInterface;
 } MOS_INTERFACE;
 
 #ifdef __cplusplus

media_common/agnostic/common/os/user_setting/media_user_setting_configure.h

@@ -28,6 +28,7 @@
 #define __MEDIA_USER_SETTING_CONFIGURE__H__
 
 #include <string>
+#include <set>
 #include "media_user_setting_definition.h"
 #include "mos_utilities.h"
 
@@ -229,6 +230,7 @@ class Configure
     std::string                                 m_statedReportPath = "";
 #if (_DEBUG || _RELEASE_INTERNAL)
     std::string                                 m_pidPath = "";
+    static std::set<std::string>                m_nonPidRegPaths;    // Record non-pid reg path which does not have inner pid path
 #endif
 };
 }

media_common/agnostic/common/vp/hal/vp_common_defs.h

@@ -190,14 +190,15 @@ enum VpKernelID
     kernelOclFc444PL3Output,
     kernelOclFc420PL3Input,
     kernelOclFc420PL3Output,
+    kernelOclFc422HVInput,
     baseKernelMaxNumID
 };
 
 enum VpKernelIDNext
 {
     vpKernelIDNextBase = 0x200,
     kernelHdr3DLutCalc = vpKernelIDNextBase,
-    kernelHdr3DLutCalcL0,
+    kernelHdr3DLutCalcOcl,
     kernelHVSCalc,
     vpKernelIDNextMax
 };
@@ -1074,6 +1075,8 @@ struct VPHAL_RENDER_PARAMS
 
     bool bForceToRender = false;  // Force to render to perform scaling.
 
+    HANDLE gpuAppTaskEvent;  //!< GPU App task event
+
     VPHAL_RENDER_PARAMS() : uSrcCount(0),
                             pSrc(),
                             uDstCount(0),
@@ -1096,7 +1099,8 @@ struct VPHAL_RENDER_PARAMS
                             pExtensionData(nullptr),
                             bPathKernel(false),
                             bUseVEHdrSfc(false),
-                            bNonFirstFrame(false)
+                            bNonFirstFrame(false),
+                            gpuAppTaskEvent(nullptr)
     {
     }
 };

media_common/agnostic/common/vp/kdll/hal_kerneldll_next.h

@@ -636,6 +636,7 @@ typedef struct tagKdll_CacheEntry
     // Kernel binary
     uint8_t *pBinary;  // kernel binary
     int      iSize;    // kernel size
+    int      iPaddingSize; //kernel padding size
 
     // Component kernel information
     int            iKUID;   // kernel unique id (static kernel)

media_driver/agnostic/common/codec/hal/codechal_encode_avc_base.cpp

@@ -3270,6 +3270,11 @@ MOS_STATUS CodechalEncodeAvcBase::SetSliceStructs()
         {
             for (uint8_t i = 0; i < (slcParams->num_ref_idx_l0_active_minus1 + 1); i++)
             {
+                if (slcParams->RefPicList[0][i].FrameIdx >= CODEC_AVC_MAX_NUM_REF_FRAME)
+                {
+                    CODECHAL_ENCODE_ASSERTMESSAGE("Invalid slice parameters.");
+                    return MOS_STATUS_INVALID_PARAMETER;
+                }
                 slcParams->PicOrder[0][i].Picture.FrameIdx =
                     m_picIdx[slcParams->RefPicList[0][i].FrameIdx].ucPicIdx;
                 slcParams->PicOrder[0][i].Picture.PicFlags =
@@ -3280,6 +3285,11 @@ MOS_STATUS CodechalEncodeAvcBase::SetSliceStructs()
         {
             for (uint8_t i = 0; i < (slcParams->num_ref_idx_l1_active_minus1 + 1); i++)
             {
+                if (slcParams->RefPicList[1][i].FrameIdx >= CODEC_AVC_MAX_NUM_REF_FRAME)
+                {
+                    CODECHAL_ENCODE_ASSERTMESSAGE("Invalid slice parameters.");
+                    return MOS_STATUS_INVALID_PARAMETER;
+                }
                 slcParams->PicOrder[1][i].Picture.FrameIdx =
                     m_picIdx[slcParams->RefPicList[1][i].FrameIdx].ucPicIdx;
                 slcParams->PicOrder[1][i].Picture.PicFlags =