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Merging r326393:
------------------------------------------------------------------------ r326393 | ctopper | 2018-03-01 01:08:38 +0100 (Thu, 01 Mar 2018) | 5 lines [X86] Make sure we don't combine (fneg (fma X, Y, Z)) to a target specific node when there are no FMA instructions. This would cause a 'cannot select' error at isel when we should have emitted a lib call and an xor. Fixes PR36553. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@326423 91177308-0d34-0410-b5e6-96231b3b80d8
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lib/Target/X86/X86ISelLowering.cpp

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@@ -35520,7 +35520,7 @@ static SDValue combineFneg(SDNode *N, SelectionDAG &DAG,
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// If we're negating an FMA node, then we can adjust the
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// instruction to include the extra negation.
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unsigned NewOpcode = 0;
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if (Arg.hasOneUse()) {
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if (Arg.hasOneUse() && Subtarget.hasAnyFMA()) {
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switch (Arg.getOpcode()) {
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case ISD::FMA: NewOpcode = X86ISD::FNMSUB; break;
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case X86ISD::FMSUB: NewOpcode = X86ISD::FNMADD; break;

test/CodeGen/X86/pr36553.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
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; Make sure we don't crash because we negated an fma when we didn't have any fma instructions.
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define float @pr36553(float %a, float %b, float %c) nounwind {
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; CHECK-LABEL: pr36553:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: callq _fmaf
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; CHECK-NEXT: xorps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: popq %rax
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; CHECK-NEXT: retq
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entry:
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%0 = tail call float @llvm.fma.f32(float %a, float %b, float %c)
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%sub = fsub float -0.000000e+00, %0
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ret float %sub
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}
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declare float @llvm.fma.f32(float, float, float)

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