Merge pull request #52 from schweitzpgi/release_70

merge up LLVM changes [Release 70 branch]

Author: sscalpone

lib/Target/X86/X86DomainReassignment.cpp

@@ -217,6 +217,27 @@ class InstrCOPYReplacer : public InstrReplacer {
   InstrCOPYReplacer(unsigned SrcOpcode, RegDomain DstDomain, unsigned DstOpcode)
       : InstrReplacer(SrcOpcode, DstOpcode), DstDomain(DstDomain) {}
 
+  bool isLegal(const MachineInstr *MI,
+               const TargetInstrInfo *TII) const override {
+    if (!InstrConverterBase::isLegal(MI, TII))
+      return false;
+
+    // Don't allow copies to/flow GR8/GR16 physical registers.
+    // FIXME: Is there some better way to support this?
+    unsigned DstReg = MI->getOperand(0).getReg();
+    if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
+        (X86::GR8RegClass.contains(DstReg) ||
+         X86::GR16RegClass.contains(DstReg)))
+      return false;
+    unsigned SrcReg = MI->getOperand(1).getReg();
+    if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
+        (X86::GR8RegClass.contains(SrcReg) ||
+         X86::GR16RegClass.contains(SrcReg)))
+      return false;
+
+    return true;
+  }
+
   double getExtraCost(const MachineInstr *MI,
                       MachineRegisterInfo *MRI) const override {
     assert(MI->getOpcode() == TargetOpcode::COPY && "Expected a COPY");

lib/Target/X86/X86ISelLowering.cpp

@@ -23312,15 +23312,14 @@ static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
   }
 
   // Check cases (mainly 32-bit) where i64 is expanded into high and low parts.
-  if (VT == MVT::v2i64  && Amt.getOpcode() == ISD::BITCAST &&
+  if (VT == MVT::v2i64 && Amt.getOpcode() == ISD::BITCAST &&
       Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
     Amt = Amt.getOperand(0);
-    unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
-                     VT.getVectorNumElements();
+    unsigned Ratio = 64 / Amt.getScalarValueSizeInBits();
     std::vector<SDValue> Vals(Ratio);
     for (unsigned i = 0; i != Ratio; ++i)
       Vals[i] = Amt.getOperand(i);
-    for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
+    for (unsigned i = Ratio, e = Amt.getNumOperands(); i != e; i += Ratio) {
       for (unsigned j = 0; j != Ratio; ++j)
         if (Vals[j] != Amt.getOperand(i + j))
           return SDValue();

lib/Target/X86/X86InstrInfo.cpp

@@ -3109,7 +3109,7 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
 
   LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
                     << RI.getName(DestReg) << '\n');
-  llvm_unreachable("Cannot emit physreg copy instruction");
+  report_fatal_error("Cannot emit physreg copy instruction");
 }
 
 bool X86InstrInfo::isCopyInstr(const MachineInstr &MI,

test/CodeGen/X86/known-signbits-vector.ll

@@ -381,19 +381,26 @@ define <4 x float> @signbits_ashr_sext_select_shuffle_sitofp(<4 x i64> %a0, <4 x
 ; X32-NEXT:    movl %esp, %ebp
 ; X32-NEXT:    andl $-16, %esp
 ; X32-NEXT:    subl $16, %esp
+; X32-NEXT:    vmovdqa {{.*#+}} xmm3 = [33,0,63,0]
+; X32-NEXT:    vmovdqa {{.*#+}} xmm4 = [0,2147483648,0,2147483648]
+; X32-NEXT:    vpsrlq %xmm3, %xmm4, %xmm5
+; X32-NEXT:    vpshufd {{.*#+}} xmm6 = xmm3[2,3,0,1]
+; X32-NEXT:    vpsrlq %xmm6, %xmm4, %xmm4
+; X32-NEXT:    vpblendw {{.*#+}} xmm4 = xmm5[0,1,2,3],xmm4[4,5,6,7]
+; X32-NEXT:    vextractf128 $1, %ymm2, %xmm5
+; X32-NEXT:    vpsrlq %xmm6, %xmm5, %xmm7
+; X32-NEXT:    vpsrlq %xmm3, %xmm5, %xmm5
+; X32-NEXT:    vpblendw {{.*#+}} xmm5 = xmm5[0,1,2,3],xmm7[4,5,6,7]
+; X32-NEXT:    vpsrlq %xmm6, %xmm2, %xmm6
+; X32-NEXT:    vpsrlq %xmm3, %xmm2, %xmm2
+; X32-NEXT:    vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm6[4,5,6,7]
 ; X32-NEXT:    vpmovsxdq 16(%ebp), %xmm3
+; X32-NEXT:    vpxor %xmm4, %xmm5, %xmm5
+; X32-NEXT:    vpsubq %xmm4, %xmm5, %xmm5
+; X32-NEXT:    vpxor %xmm4, %xmm2, %xmm2
+; X32-NEXT:    vpsubq %xmm4, %xmm2, %xmm2
 ; X32-NEXT:    vpmovsxdq 8(%ebp), %xmm4
-; X32-NEXT:    vmovdqa {{.*#+}} xmm5 = [33,0,63,0]
-; X32-NEXT:    vmovdqa {{.*#+}} xmm6 = [0,2147483648,0,2147483648]
-; X32-NEXT:    vpsrlq %xmm5, %xmm6, %xmm6
-; X32-NEXT:    vextractf128 $1, %ymm2, %xmm7
-; X32-NEXT:    vpsrlq %xmm5, %xmm7, %xmm7
-; X32-NEXT:    vpxor %xmm6, %xmm7, %xmm7
-; X32-NEXT:    vpsubq %xmm6, %xmm7, %xmm7
-; X32-NEXT:    vpsrlq %xmm5, %xmm2, %xmm2
-; X32-NEXT:    vpxor %xmm6, %xmm2, %xmm2
-; X32-NEXT:    vpsubq %xmm6, %xmm2, %xmm2
-; X32-NEXT:    vinsertf128 $1, %xmm7, %ymm2, %ymm2
+; X32-NEXT:    vinsertf128 $1, %xmm5, %ymm2, %ymm2
 ; X32-NEXT:    vinsertf128 $1, %xmm3, %ymm4, %ymm3
 ; X32-NEXT:    vextractf128 $1, %ymm1, %xmm4
 ; X32-NEXT:    vextractf128 $1, %ymm0, %xmm5

test/CodeGen/X86/pr38803.ll

@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mcpu=skylake-avx512 -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+@b = local_unnamed_addr global i32 0, align 4
+@c = local_unnamed_addr global i32 0, align 4
+@d = local_unnamed_addr global float 0.000000e+00, align 4
+
+define float @_Z3fn2v() {
+; CHECK-LABEL: _Z3fn2v:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    callq _Z1av
+; CHECK-NEXT:    # kill: def $al killed $al def $eax
+; CHECK-NEXT:    kmovd %eax, %k1
+; CHECK-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:    vmovss %xmm0, %xmm0, %xmm0 {%k1} {z}
+; CHECK-NEXT:    cmpl $0, {{.*}}(%rip)
+; CHECK-NEXT:    je .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %if.then
+; CHECK-NEXT:    vcvtsi2ssl {{.*}}(%rip), %xmm1, %xmm1
+; CHECK-NEXT:    kmovd %eax, %k1
+; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vmovss %xmm2, %xmm0, %xmm1 {%k1}
+; CHECK-NEXT:    vmovss %xmm1, {{.*}}(%rip)
+; CHECK-NEXT:  .LBB0_2: # %if.end
+; CHECK-NEXT:    popq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    retq
+entry:
+  %call = tail call zeroext i1 @_Z1av()
+  %cond = select i1 %call, float 7.500000e-01, float 0.000000e+00
+  %0 = load i32, i32* @c, align 4
+  %tobool2 = icmp eq i32 %0, 0
+  br i1 %tobool2, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry
+  %1 = load i32, i32* @b, align 4
+  %2 = sitofp i32 %1 to float
+  %conv5 = select i1 %call, float 0.000000e+00, float %2
+  store float %conv5, float* @d, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %entry, %if.then
+  ret float %cond
+}
+
+declare zeroext i1 @_Z1av()

tools/llvm-xray/xray-account.cpp

@@ -358,8 +358,11 @@ void LatencyAccountant::exportStats(const XRayFileHeader &Header, F Fn) const {
     break;
   }
 
-  if (AccountTop > 0)
-    Results.erase(Results.begin() + AccountTop.getValue(), Results.end());
+  if (AccountTop > 0) {
+    auto MaxTop =
+        std::min(AccountTop.getValue(), static_cast<int>(Results.size()));
+    Results.erase(Results.begin() + MaxTop, Results.end());
+  }
 
   for (const auto &R : Results)
     Fn(std::get<0>(R), std::get<1>(R), std::get<2>(R));