Commit 8f5f7f9
committed
Merging r324645:
------------------------------------------------------------------------
r324645 | dwmw2 | 2018-02-08 12:06:05 -0800 (Thu, 08 Feb 2018) | 5 lines
[X86] Support 'V' register operand modifier
This allows the register name to be printed without the leading '%'.
This can be used for emitting calls to the retpoline thunks from inline
asm.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@325089 91177308-0d34-0410-b5e6-96231b3b80d81 parent 4e5fddc commit 8f5f7f9
File tree
2 files changed
+24
-1
lines changed- lib/Target/X86
- test/CodeGen/X86
2 files changed
+24
-1
lines changed| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
| |||
344 | 344 | | |
345 | 345 | | |
346 | 346 | | |
| 347 | + | |
| 348 | + | |
347 | 349 | | |
348 | 350 | | |
349 | 351 | | |
| |||
358 | 360 | | |
359 | 361 | | |
360 | 362 | | |
| 363 | + | |
| 364 | + | |
| 365 | + | |
361 | 366 | | |
362 | 367 | | |
363 | 368 | | |
364 | 369 | | |
365 | 370 | | |
366 | 371 | | |
367 | 372 | | |
368 | | - | |
| 373 | + | |
| 374 | + | |
| 375 | + | |
| 376 | + | |
369 | 377 | | |
370 | 378 | | |
371 | 379 | | |
| |||
438 | 446 | | |
439 | 447 | | |
440 | 448 | | |
| 449 | + | |
441 | 450 | | |
442 | 451 | | |
443 | 452 | | |
| |||
| Original file line number | Diff line number | Diff line change | |
|---|---|---|---|
| |||
| 1 | + | |
| 2 | + | |
| 3 | + | |
| 4 | + | |
| 5 | + | |
| 6 | + | |
| 7 | + | |
| 8 | + | |
| 9 | + | |
| 10 | + | |
| 11 | + | |
| 12 | + | |
| 13 | + | |
| 14 | + | |
0 commit comments