Skip to content

Commit 2195068

Browse files
committed
fix: issue on address
1 parent a1f6221 commit 2195068

File tree

1 file changed

+6
-5
lines changed

1 file changed

+6
-5
lines changed

gpio_expander.py

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -62,9 +62,10 @@ def _get_registry_params(value, x):
6262
_reg_address_multiplier = 1
6363
_idx = x % 8
6464
_adder = 0
65+
if x > 7:
66+
_adder = 1
6567
if value > 8:
6668
_reg_address_multiplier = 2
67-
_adder = 1
6869
# datasheet bit field's name has underscore in place of dot for 16 bit expander
6970
if x >= 8:
7071
_name = "1_"
@@ -86,10 +87,10 @@ def __new__(mcs, clsname, bases, dct, *args, **kwargs): # pylint: disable=unuse
8687
# call to get only interesting data
8788
_, _width, _, _ = _get_registry_params(value, 1)
8889
# entire registries
89-
_result_dct['input_ports'] = ROBits(8 * _width, _INPUT_PORT, 0, register_width=_width)
90-
_result_dct['output_ports'] = RWBits(8 * _width, _OUTPUT_PORT, 0, register_width=_width)
91-
_result_dct['polarity_inversions'] = RWBits(8 * _width, _POLARITY_REGISTER, 0, register_width=_width)
92-
_result_dct['configuration_ports'] = RWBits(8 * _width, _CONFIG_REGISTER, 0, register_width=_width)
90+
_result_dct['input_ports'] = ROBits(8 * _width, _INPUT_PORT * _width, 0, register_width=_width)
91+
_result_dct['output_ports'] = RWBits(8 * _width, _OUTPUT_PORT * _width, 0, register_width=_width)
92+
_result_dct['polarity_inversions'] = RWBits(8 * _width, _POLARITY_REGISTER * _width, 0, register_width=_width)
93+
_result_dct['configuration_ports'] = RWBits(8 * _width, _CONFIG_REGISTER * _width, 0, register_width=_width)
9394

9495
# create single bit registries
9596
for x in range(value):

0 commit comments

Comments
 (0)