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When connecting to a vertex, the final via might cause a violation #15

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@growly

Ponder this:

Image

The rule might need to be:

  • when connecting to a vertex on the same layer as an incoming edge, if the edge we're connecting from is so short that a via at one end would leave a tiny stub at such a distance that a wire there could not be acommodated within min separation, fatten the whole edge; and/or
  • check shapes nearby (i.e. that DRC feature we've been wanting)

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