From 7ea40029136143e447d2ac66e73a607e4b1b2d5c Mon Sep 17 00:00:00 2001 From: Vin Xue Date: Fri, 10 Jul 2020 10:10:04 +0800 Subject: [PATCH] libefiusb: fixed incorrect logical operator for DCTL register Signed-off-by: Vin Xue --- libefiusb/device_mode/XdciDWC.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/libefiusb/device_mode/XdciDWC.c b/libefiusb/device_mode/XdciDWC.c index cac538ab..40fb53fc 100644 --- a/libefiusb/device_mode/XdciDWC.c +++ b/libefiusb/device_mode/XdciDWC.c @@ -1521,9 +1521,9 @@ DwcXdciCoreInit ( UsbRegWrite ( BaseAddr, DWC_XDCI_DCTL_REG, - UsbRegRead (BaseAddr, DWC_XDCI_DCTL_REG) & + (UsbRegRead (BaseAddr, DWC_XDCI_DCTL_REG) & (~DWC_XDCI_DCTL_KEEP_CONNECT_MASK) & - ((~DWC_XDCI_DCTL_STATE_CHANGE_REQ_MASK) | (DWC_XDCI_DCTL_STATE_CHANGE_REQ_RX_DETECT << DWC_XDCI_DCTL_STATE_CHANGE_REQ_BIT_POS)) + (~DWC_XDCI_DCTL_STATE_CHANGE_REQ_MASK)) | (DWC_XDCI_DCTL_STATE_CHANGE_REQ_RX_DETECT << DWC_XDCI_DCTL_STATE_CHANGE_REQ_BIT_POS) ); DEBUG ((DEBUG_INFO, "Device controller Synopsys ID: %x\n", UsbRegRead (BaseAddr, DWC_XDCI_GSNPSID_REG))); @@ -3617,10 +3617,10 @@ UsbXdciCoreReinit ( UsbRegWrite ( BaseAddr, DWC_XDCI_DCTL_REG, - UsbRegRead (BaseAddr, DWC_XDCI_DCTL_REG) & + (UsbRegRead (BaseAddr, DWC_XDCI_DCTL_REG) & (~DWC_XDCI_DCTL_KEEP_CONNECT_MASK) & - ((~DWC_XDCI_DCTL_STATE_CHANGE_REQ_MASK) | - (DWC_XDCI_DCTL_STATE_CHANGE_REQ_RX_DETECT << DWC_XDCI_DCTL_STATE_CHANGE_REQ_BIT_POS)) + (~DWC_XDCI_DCTL_STATE_CHANGE_REQ_MASK)) | + (DWC_XDCI_DCTL_STATE_CHANGE_REQ_RX_DETECT << DWC_XDCI_DCTL_STATE_CHANGE_REQ_BIT_POS) ); DEBUG ((DEBUG_INFO, "Device controller Synopsys ID: %x\n", UsbRegRead (BaseAddr, DWC_XDCI_GSNPSID_REG)));