Smart_tabs not handled by procedure_call_400

[adsclelann]

Environment
VSG 3.33.0 on Fedora 32.

Describe the bug
When in smart_tabs mode, I expect tabs to be used for indentation, and sometimes extra spaces be added for alignment.
It seems that procedure_call_400 has issues in this mode, as shown in the following example.

To Reproduce
Use the following VHDL file (every indentation is a tab):

library ieee;
use ieee.std_logic_1164.all;

architecture rtl of myentity is

begin

	Pfoo: process (all)
		procedure foooooooo (a : natural; b : std_logic_vector(31 downto 0); c : boolean) is
		begin
		end procedure;
	begin
		if toto = '1' then
			foooooooo(
				a => 5,
				b => (others => '0'),
				c => true
			);
		end if;
	end process;

end architecture;

With the following configuration:

rule:
  global:
    indent_size: 2

    disable: true
    fixable: false

    align_left: yes
    align_paren: no
    align_when_keywords: yes
    wrap_at_when: yes
    align_else_keywords: no
    compact_alignment: yes
    blank_line_ends_group: no
    comment_line_ends_group: no
    indent_style: smart_tabs
    separate_generic_port_alignment: no
    if_control_statements_ends_group: yes
    case_control_statements_ends_group: yes
    generate_statements_ends_group: yes
    loop_control_generic_port_alignment: yes
    include_type_is_keyword: yes
    aggregate_parens_ends_group: no
    ignore_single_line_aggregates: yes
    align_to: current_indent

  procedure_call_400:
    disable: false
    fixable: true

VSG reports an error, expecting the parameters of the procedure call to be indented with 1 tab + 2 spaces, instead of 4 tabs.

Expected behavior
I would expect VSG to consider 4 tabs (in this case) to be the correct indentation.

Screenshots

================================================================================
File:  bug_procedure_call_400.vhd
================================================================================
Phase 5 of 7... Reporting
Total Rules Checked: 1
Total Violations:    4
  Error   :     4
  Warning :     0
---------------------+------------+------------+--------------------------------------
  Rule               |  severity  |  line(s)   | Solution
---------------------+------------+------------+--------------------------------------
  procedure_call_400 | Error      |         15 | Indent with 1 tab(s) followed by 2 space(s)
  procedure_call_400 | Error      |         16 | Indent with 1 tab(s) followed by 2 space(s)
  procedure_call_400 | Error      |         17 | Indent with 1 tab(s) followed by 2 space(s)
  procedure_call_400 | Error      |         18 | Indent with 1 tab(s)
---------------------+------------+------------+--------------------------------------

The "fixed" version by VSG:

library ieee;
use ieee.std_logic_1164.all;

architecture rtl of myentity is

begin

	Pfoo: process (all)
		procedure foooooooo (a : natural; b : std_logic_vector(31 downto 0); c : boolean) is
		begin
		end procedure;
	begin
		if toto = '1' then
			foooooooo(
	  a => 5,
	  b => (others => '0'),
	  c => true
	);
		end if;
	end process;

end architecture;

Thank you for your help