Add blank line rule in port_map

docs/configuring_blank_lines.rst

@@ -157,6 +157,7 @@ Rules Enforcing Blank Lines
 * `entity_202 <entity_rules.html#entity-202>`_
 * `entity_203 <entity_rules.html#entity-203>`_
 * `generate_003 <generate_rules.html#generate-003>`_
+* `generic_map_201 <generic_map_rules.html#generic-map-201>`_
 * `if_030 <if_rules.html#if-030>`_
 * `instantiation_019 <instantiation_rules.html#instantiation-019>`_
 * `loop_statement_201 <loop_statement_rules.html#loop-statement-201>`_
@@ -169,6 +170,7 @@ Rules Enforcing Blank Lines
 * `package_instantiation_201 <package_instantiation_rules.html#package-instantiation-201>`_
 * `port_001 <port_rules.html#port-001>`_
 * `port_map_200 <port_map_rules.html#port-map-200>`_
+* `port_map_201 <port_map_rules.html#port-map-201>`_
 * `pragma_401 <pragma_rules.html#pragma-401>`_
 * `pragma_403 <pragma_rules.html#pragma-403>`_
 * `process_011 <process_rules.html#process-011>`_

docs/generic_map_rules.rst

@@ -292,6 +292,46 @@ This rule checks for a single space between the **generic** keyword and the **ma
 
    generic map (
 
+generic_map_201
+###############
+
+|phase_3| |error| |blank_line|
+
+This rule checks for blank lines in a generic map.
+
+|configuring_blank_lines_link|
+
+**Violation**
+
+.. code-block:: vhdl
+
+  generic map (
+    G_GEN_1 => 3,
+    G_GEN_2 => 4,
+
+    G_GEN_3 => 5
+  )
+  port map (
+    PORT_1 => w_port_1,
+    PORT_2 => w_port_2,
+    PORT_3 => w_port_3
+  );
+
+**Fix**
+
+.. code-block:: vhdl
+
+  generic map (
+    G_GEN_1 => 3,
+    G_GEN_2 => 4,
+    G_GEN_3 => 5
+  )
+  port map (
+    PORT_1 => w_port_1,
+    PORT_2 => w_port_2,
+    PORT_3 => w_port_3
+  );
+
 generic_map_300
 ###############
 

docs/port_map_rules.rst

@@ -383,6 +383,47 @@ This rule checks for a blank line below the open parenthesis in a port map.
     OVERFLOW => w_overflow
   );
 
+port_map_201
+############
+
+|phase_3| |error| |blank_line|
+
+This rule checks for blank lines in a port map.
+
+|configuring_blank_lines_link|
+
+**Violation**
+
+.. code-block:: vhdl
+
+  generic map (
+    G_GEN_1 => 3,
+    G_GEN_2 => 4,
+    G_GEN_3 => 5
+  )
+  port map (
+    PORT_1 => w_port_1,
+
+    PORT_2 => w_port_2,
+    PORT_3 => w_port_3
+  );
+
+**Fix**
+
+.. code-block:: vhdl
+
+  generic map (
+    G_GEN_1 => 3,
+    G_GEN_2 => 4,
+    G_GEN_3 => 5
+  )
+  port map (
+    PORT_1 => w_port_1,
+    PORT_2 => w_port_2,
+    PORT_3 => w_port_3
+  );
+
+
 port_map_300
 ############
 

docs/rule_groups/blank_line_rule_group.rst

@@ -41,6 +41,7 @@ Rules Enforcing Blank Line Rule Group
 * `generate_003 <../generate_rules.html#generate-003>`_
 * `generate_004 <../generate_rules.html#generate-004>`_
 * `generic_019 <../generic_rules.html#generic-019>`_
+* `generic_map_201 <../generic_map_rules.html#generic-map-201>`_
 * `if_006 <../if_rules.html#if-006>`_
 * `if_007 <../if_rules.html#if-007>`_
 * `if_008 <../if_rules.html#if-008>`_
@@ -69,6 +70,7 @@ Rules Enforcing Blank Line Rule Group
 * `port_022 <../port_rules.html#port-022>`_
 * `port_024 <../port_rules.html#port-024>`_
 * `port_map_200 <../port_map_rules.html#port-map-200>`_
+* `port_map_201 <../port_map_rules.html#port-map-201>`_
 * `pragma_400 <../pragma_rules.html#pragma-400>`_
 * `pragma_401 <../pragma_rules.html#pragma-401>`_
 * `pragma_402 <../pragma_rules.html#pragma-402>`_

docs/whitespace_rules.rst

@@ -198,7 +198,7 @@ whitespace_011
 
 |phase_2| |error| |whitespace|
 
-This rule checks for at least a single space before and after math operators +, -, /, * and \*\*.
+This rule checks for at least a single space before and after math operators +, -, /, * and **.
 
 **Violation**
 

tests/generic_map/rule_201_test_input.fixed.vhd

@@ -0,0 +1,78 @@
+
+architecture ARCH of ENTITY1 is
+
+begin
+
+  U_INST1 : INST1
+    generic map (
+      G_GEN_1 => 3,
+      G_GEN_2 => 4,
+      G_GEN_3 => 5
+    )
+    port map (
+
+      PORT_1 => w_port_1,
+
+      PORT_2 => w_port_2,
+
+      PORT_3 => w_port_3
+    );
+
+  -- Violations below
+
+  U_INST1 : INST1
+    generic map (
+      G_GEN_1 => 3,
+      G_GEN_2 => 4,
+      G_GEN_3 => 5
+    )
+    port map (
+
+      PORT_1 => w_port_1,
+
+      PORT_2 => w_port_2,
+
+      PORT_3 => w_port_3
+    );
+
+  U_INST1 : INST1
+    generic map (
+      G_GEN_1 => 3,
+      G_GEN_2 => 4,
+      G_GEN_3 => 5
+
+    )
+    port map (
+
+      PORT_1 => w_port_1,
+
+      PORT_2 => w_port_2,
+
+      PORT_3 => w_port_3
+    );
+
+  -- Test with comments
+
+  U_INST1 : INST1
+    generic map (
+
+      -- Comment 1
+      G_GEN_1 => 3,
+      G_GEN_2 => 4,
+
+      -- Comment 2
+      G_GEN_3 => 5
+
+    )
+    port map (
+
+      PORT_1 => w_port_1,
+
+      PORT_2 => w_port_2,
+
+      PORT_3 => w_port_3
+    );
+
+
+
+end architecture ARCH;

tests/generic_map/rule_201_test_input.vhd

@@ -0,0 +1,84 @@
+
+architecture ARCH of ENTITY1 is
+
+begin
+
+  U_INST1 : INST1
+    generic map (
+      G_GEN_1 => 3,
+      G_GEN_2 => 4,
+      G_GEN_3 => 5
+    )
+    port map (
+
+      PORT_1 => w_port_1,
+
+      PORT_2 => w_port_2,
+
+      PORT_3 => w_port_3
+    );
+
+  -- Violations below
+
+  U_INST1 : INST1
+    generic map (
+      G_GEN_1 => 3,
+      G_GEN_2 => 4,
+
+      G_GEN_3 => 5
+    )
+    port map (
+
+      PORT_1 => w_port_1,
+
+      PORT_2 => w_port_2,
+
+      PORT_3 => w_port_3
+    );
+
+  U_INST1 : INST1
+    generic map (
+      G_GEN_1 => 3,
+
+      G_GEN_2 => 4,
+
+      G_GEN_3 => 5
+
+    )
+    port map (
+
+      PORT_1 => w_port_1,
+
+      PORT_2 => w_port_2,
+
+      PORT_3 => w_port_3
+    );
+
+  -- Test with comments
+
+  U_INST1 : INST1
+    generic map (
+
+      -- Comment 1
+
+      G_GEN_1 => 3,
+
+      G_GEN_2 => 4,
+
+      -- Comment 2
+
+      G_GEN_3 => 5
+
+    )
+    port map (
+
+      PORT_1 => w_port_1,
+
+      PORT_2 => w_port_2,
+
+      PORT_3 => w_port_3
+    );
+
+
+
+end architecture ARCH;

tests/generic_map/test_rule_201.py

@@ -0,0 +1,46 @@
+# -*- coding: utf-8 -*-
+
+import os
+import unittest
+
+from tests import utils
+from vsg import vhdlFile
+from vsg.rules import generic_map
+
+sTestDir = os.path.dirname(__file__)
+
+lFile, eError = vhdlFile.utils.read_vhdlfile(os.path.join(sTestDir, "rule_201_test_input.vhd"))
+
+lExpected = []
+lExpected.append("")
+utils.read_file(os.path.join(sTestDir, "rule_201_test_input.fixed.vhd"), lExpected)
+
+
+class test_generic_map_rule(unittest.TestCase):
+    def setUp(self):
+        self.oFile = vhdlFile.vhdlFile(lFile)
+        self.assertIsNone(eError)
+
+    def test_rule_201(self):
+        oRule = generic_map.rule_201()
+        self.assertTrue(oRule)
+        self.assertEqual(oRule.name, "generic_map")
+        self.assertEqual(oRule.identifier, "201")
+        self.assertEqual(oRule.groups, ["blank_line"])
+
+        lExpected = [28, 43, 45, 64, 66, 70]
+
+        oRule.analyze(self.oFile)
+        self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
+
+    def test_fix_rule_201(self):
+        oRule = generic_map.rule_201()
+
+        oRule.fix(self.oFile)
+
+        lActual = self.oFile.get_lines()
+
+        self.assertEqual(lExpected, lActual)
+
+        oRule.analyze(self.oFile)
+        self.assertEqual(oRule.violations, [])