Add blank line rule in port_map

docs/port_map_rules.rst

@@ -383,6 +383,37 @@ This rule checks for a blank line below the open parenthesis in a port map.
     OVERFLOW => w_overflow
   );
 
+port_map_201
+############
+
+|phase_3| |error| |blank_line|
+
+This rule checks for blank lines in a port map.
+
+|configuring_blank_lines_link|
+
+**Violation**
+
+.. code-block:: vhdl
+
+  port map (
+    WR_EN => w_wr_en,
+
+    RD_EN => w_rd_en,
+    OVERFLOW => w_overflow
+  );
+
+**Fix**
+
+.. code-block:: vhdl
+
+  port map (
+    WR_EN => w_wr_en,
+    RD_EN => w_rd_en,
+    OVERFLOW => w_overflow
+  );
+
+
 port_map_300
 ############
 

tests/port_map/rule_201_test_input.fixed.vhd

@@ -0,0 +1,45 @@
+
+architecture ARCH of ENTITY1 is
+
+begin
+
+  U_INST1 : INST1
+    generic map (
+      G_GEN_1 => 3,
+      G_GEN_2 => 4,
+      G_GEN_3 => 5
+    )
+    port map (
+      PORT_1 => w_port_1,
+      PORT_2 => w_port_2,
+      PORT_3 => w_port_3
+    );
+
+  -- Violations below
+
+  U_INST1 : INST1
+    generic map (
+      G_GEN_1 => 3,
+      G_GEN_2 => 4,
+      G_GEN_3 => 5
+    )
+    port map (
+      PORT_1 => w_port_1,
+      PORT_2 => w_port_2,
+      PORT_3 => w_port_3
+    );
+
+  U_INST1 : INST1
+    generic map (
+      G_GEN_1 => 3,
+      G_GEN_2 => 4,
+      G_GEN_3 => 5
+    )
+    port map (
+      PORT_1 => w_port_1,
+      PORT_2 => w_port_2,
+      PORT_3 => w_port_3
+    );
+
+
+end architecture ARCH;

tests/port_map/rule_201_test_input.vhd

@@ -0,0 +1,49 @@
+
+architecture ARCH of ENTITY1 is
+
+begin
+
+  U_INST1 : INST1
+    generic map (
+      G_GEN_1 => 3,
+      G_GEN_2 => 4,
+      G_GEN_3 => 5
+    )
+    port map (
+      PORT_1 => w_port_1,
+      PORT_2 => w_port_2,
+      PORT_3 => w_port_3
+    );
+
+  -- Violations below
+
+  U_INST1 : INST1
+    generic map (
+      G_GEN_1 => 3,
+      G_GEN_2 => 4,
+      G_GEN_3 => 5
+    )
+    port map (
+      PORT_1 => w_port_1,
+
+      PORT_2 => w_port_2,
+      PORT_3 => w_port_3
+    );
+
+  U_INST1 : INST1
+    generic map (
+      G_GEN_1 => 3,
+      G_GEN_2 => 4,
+      G_GEN_3 => 5
+    )
+    port map (
+      PORT_1 => w_port_1,
+
+      PORT_2 => w_port_2,
+
+
+      PORT_3 => w_port_3
+    );
+
+
+end architecture ARCH;

tests/port_map/test_rule_201.py

@@ -0,0 +1,49 @@
+# -*- coding: utf-8 -*-
+
+import os
+import unittest
+
+from tests import utils
+from vsg import vhdlFile
+from vsg.rules import port_map
+
+sTestDir = os.path.dirname(__file__)
+
+lFile, eError = vhdlFile.utils.read_vhdlfile(os.path.join(sTestDir, "rule_201_test_input.vhd"))
+
+lExpected = []
+lExpected.append("")
+utils.read_file(os.path.join(sTestDir, "rule_201_test_input.fixed.vhd"), lExpected)
+
+
+class test_port_map_rule(unittest.TestCase):
+
+    maxDiff = None
+
+    def setUp(self):
+        self.oFile = vhdlFile.vhdlFile(lFile)
+        self.assertIsNone(eError)
+
+    def test_rule_201(self):
+        oRule = port_map.rule_201()
+        self.assertTrue(oRule)
+        self.assertEqual(oRule.name, "port_map")
+        self.assertEqual(oRule.identifier, "201")
+        self.assertEqual(oRule.groups, ["blank_line"])
+
+        lExpected = [28, 41, 43, 44]
+
+        oRule.analyze(self.oFile)
+        self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
+
+    def test_fix_rule_201(self):
+        oRule = port_map.rule_201()
+
+        oRule.fix(self.oFile)
+
+        lActual = self.oFile.get_lines()
+
+        self.assertEqual(lExpected, lActual)
+
+        oRule.analyze(self.oFile)
+        self.assertEqual(oRule.violations, [])

vsg/rules/port_map/rule_201.py

@@ -0,0 +1,38 @@
+# -*- coding: utf-8 -*-
+
+from vsg import token
+from vsg.rules import blank_lines_between_token_pairs as Rule
+
+lTokenPairs = []
+lTokenPairs.append([token.port_map_aspect.open_parenthesis, token.port_map_aspect.close_parenthesis])
+
+class rule_201(Rule):
+    """
+    This rule checks for blank lines in a port map.
+
+    |configuring_blank_lines_link|
+
+    **Violation**
+
+    .. code-block:: vhdl
+
+      port map (
+        PORT_1 => w_port_1,
+
+        PORT_2 => w_port_2,
+        PORT_3 => w_port_3
+    );
+
+    **Fix**
+
+    .. code-block:: vhdl
+
+      port map (
+      PORT_1 => w_port_1,
+      PORT_2 => w_port_2,
+      PORT_3 => w_port_3
+    );
+    """
+
+    def __init__(self):
+        super().__init__(lTokenPairs)