Mask types for AVX-512

[valadaptive]

With #178 cleaning up and consolidating x86 codegen, AVX-512 is the next big work item.

Unlike all the other SIMD levels, AVX-512 masks are not vector-sized bitmasks, where each element is all ones or all zeroes. Instead, they are stored in separate mask registers which contain only one bit per element.

This runs counter to the existing mask vector types, which assume that every mask element is the same bit width as the corresponding vector element.

I believe RISC-V's RVV does something somewhat similar--in their case, the mask vectors are stored in the lower bits of the vector registers themselves, but they are still dense bitmasks. ARM SVE has "predicate registers", which are similarly densely packed.

In order to support AVX-512 (and eventually RVV and maybe SVE?) we will need to make the mask types more opaque, to abstract over their differing architectural representations.