From 9f8bfa9b603cfc0d776f5aadc5442c3ff7c10ac5 Mon Sep 17 00:00:00 2001 From: Dmitry Smirnov Date: Sun, 30 Apr 2017 00:37:24 +0300 Subject: [PATCH 1/7] Add h264 encoder support and make the library usable by several clients - Support for h264 encoder is ported from cedrus264 encoder for ffmpeg) (see https://github.com/alcantor/FFmpeg/tree/sunxi-cedrus) - Library API can now be used by several clients (in the same process) simulteneously. Example is libvdpau-sunxi and ffmpeg/cedrus264. --- cedrus.c | 29 +++++++++++++++++++++++++---- cedrus.h | 2 +- cedrus_regs.h | 31 +++++++++++++++++++++++++++++++ 3 files changed, 57 insertions(+), 5 deletions(-) diff --git a/cedrus.c b/cedrus.c index 5097bd4..9e6a1d6 100644 --- a/cedrus.c +++ b/cedrus.c @@ -34,6 +34,9 @@ #define DEVICE "/dev/cedar_dev" #define EXPORT __attribute__ ((visibility ("default"))) +static pthread_mutex_t open_lock = PTHREAD_MUTEX_INITIALIZER; +static int open_count; + static struct cedrus { int fd; @@ -46,14 +49,20 @@ static struct cedrus EXPORT struct cedrus *cedrus_open(void) { - if (ve.fd != -1) - return NULL; + pthread_mutex_lock(&open_lock); + if (ve.fd != -1) { + open_count++; + pthread_mutex_unlock(&open_lock); + return &ve; + } struct cedarv_env_infomation info; ve.fd = open(DEVICE, O_RDWR); - if (ve.fd == -1) + if (ve.fd == -1) { + pthread_mutex_unlock(&open_lock); return NULL; + } if (ioctl(ve.fd, IOCTL_GET_ENV_INFO, (void *)(&info)) == -1) goto close; @@ -89,6 +98,8 @@ EXPORT struct cedrus *cedrus_open(void) writel(0x00130007, ve.regs + VE_CTRL); + open_count++; + pthread_mutex_unlock(&open_lock); return &ve; unmap: @@ -96,13 +107,22 @@ EXPORT struct cedrus *cedrus_open(void) close: close(ve.fd); ve.fd = -1; + pthread_mutex_unlock(&open_lock); return NULL; } EXPORT void cedrus_close(struct cedrus *dev) { - if (dev->fd == -1) + pthread_mutex_lock(&open_lock); + if (dev->fd == -1) { + pthread_mutex_unlock(&open_lock); return; + } + + if (--open_count) { + pthread_mutex_unlock(&open_lock); + return; + } ioctl(dev->fd, IOCTL_DISABLE_VE + dev->ioctl_offset, 0); ioctl(dev->fd, IOCTL_ENGINE_REL, 0); @@ -114,6 +134,7 @@ EXPORT void cedrus_close(struct cedrus *dev) close(dev->fd); dev->fd = -1; + pthread_mutex_unlock(&open_lock); } EXPORT int cedrus_get_ve_version(struct cedrus *dev) diff --git a/cedrus.h b/cedrus.h index ec8daaf..af3f744 100644 --- a/cedrus.h +++ b/cedrus.h @@ -25,7 +25,7 @@ typedef struct cedrus cedrus_t; -enum cedrus_engine { CEDRUS_ENGINE_MPEG = 0x0, CEDRUS_ENGINE_H264 = 0x1, CEDRUS_ENGINE_HEVC = 0x4 }; +enum cedrus_engine { CEDRUS_ENGINE_MPEG = 0x0, CEDRUS_ENGINE_H264 = 0x1, CEDRUS_ENGINE_HEVC = 0x4, CEDRUS_ENGINE_H264_ENC = 0xb }; cedrus_t *cedrus_open(void); void cedrus_close(cedrus_t *dev); diff --git a/cedrus_regs.h b/cedrus_regs.h index 8c3fb91..2c3f0cb 100644 --- a/cedrus_regs.h +++ b/cedrus_regs.h @@ -62,10 +62,16 @@ static inline uint32_t readl(void *addr) #define VE_MPEG_IQ_MIN_INPUT 0x180 #define VE_MPEG_QP_INPUT 0x184 +#define VE_MPEG_JPEG_SIZE 0x1b8 +#define VE_MPEG_JPEG_RES_INT 0x1c0 + #define VE_MPEG_ROT_LUMA 0x1cc #define VE_MPEG_ROT_CHROMA 0x1d0 #define VE_MPEG_SDROT_CTRL 0x1d4 +#define VE_MPEG_RAM_WRITE_PTR 0x1e0 +#define VE_MPEG_RAM_WRITE_DATA 0x1e4 + #define VE_H264_FRAME_SIZE 0x200 #define VE_H264_PIC_HDR 0x204 #define VE_H264_SLICE_HDR 0x208 @@ -135,4 +141,29 @@ static inline uint32_t readl(void *addr) #define VE_SRAM_HEVC_REF_PIC_LIST0 0xc00 #define VE_SRAM_HEVC_REF_PIC_LIST1 0xc10 +#define VE_ISP_INPUT_SIZE 0xa00 +#define VE_ISP_INPUT_STRIDE 0xa04 +#define VE_ISP_INPUT_LUMA 0xa78 +#define VE_ISP_INPUT_CHROMA 0xa7c + +#define VE_AVC_PARAM 0xb04 +#define VE_AVC_QP 0xb08 +#define VE_AVC_MOTION_EST 0xb10 +#define VE_AVC_CTRL 0xb14 +#define VE_AVC_TRIGGER 0xb18 +#define VE_AVC_STATUS 0xb1c +#define VE_AVC_BASIC_BITS 0xb20 +#define VE_AVC_VLE_ADDR 0xb80 +#define VE_AVC_VLE_END 0xb84 +#define VE_AVC_VLE_OFFSET 0xb88 +#define VE_AVC_VLE_LENGTH 0xb90 +#define VE_AVC_REF_LUMA 0xba0 +#define VE_AVC_REF_CHROMA 0xba4 +#define VE_AVC_REC_LUMA 0xbb0 +#define VE_AVC_REC_CHROMA 0xbb4 +#define VE_AVC_REF_SLUMA 0xbb8 +#define VE_AVC_REC_SLUMA 0xbbc +#define VE_AVC_MB_INFO 0xbc0 + + #endif From a7bb9df420bf3f7d18c31c0039d4d70a33b568c2 Mon Sep 17 00:00:00 2001 From: ubobrov Date: Mon, 11 Nov 2019 17:02:17 +0300 Subject: [PATCH 2/7] improved to work with EN & DE dependent on the engine selected --- cedrus.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/cedrus.c b/cedrus.c index 9e6a1d6..3b45f41 100644 --- a/cedrus.c +++ b/cedrus.c @@ -147,10 +147,18 @@ EXPORT int cedrus_get_ve_version(struct cedrus *dev) EXPORT int cedrus_ve_wait(struct cedrus *dev, int timeout) { + unsigned int engine_wait = IOCTL_WAIT_VE_DE; + unsigned int reg = 0; if (!dev) return -1; - return ioctl(dev->fd, IOCTL_WAIT_VE_DE, timeout); + if (((reg = readl(dev->regs + VE_CTRL)) & CEDRUS_ENGINE_H264_ENC) == CEDRUS_ENGINE_H264_ENC) { + engine_wait = IOCTL_WAIT_VE_DE + dev->ioctl_offset; + } + + //printf("we engine %04X, we wait %d\n", reg, engine_wait); + + return ioctl(dev->fd, engine_wait, timeout); } EXPORT void *cedrus_ve_get(struct cedrus *dev, enum cedrus_engine engine, uint32_t flags) From d0b8a035559ec9538fe43293731d49ae77f08fcb Mon Sep 17 00:00:00 2001 From: ubobrov Date: Mon, 11 Nov 2019 17:05:24 +0300 Subject: [PATCH 3/7] Update README --- README | 3 +++ 1 file changed, 3 insertions(+) diff --git a/README b/README index 351d848..66e3a7a 100644 --- a/README +++ b/README @@ -1,3 +1,6 @@ +## UPD: +Improved to work with EN and DE depended to the value of engine select bits. + libcedrus provides low-level access to the video engine of Allwinner sunxi SoCs. Installation: From 3c587a2903614b8aab4b3221b85e18f2d96b9019 Mon Sep 17 00:00:00 2001 From: ubobrov Date: Thu, 23 Apr 2020 13:13:03 +0300 Subject: [PATCH 4/7] some registers added for H264 decoder --- cedrus.c | 10 ++++++++++ cedrus.h | 1 + cedrus_regs.h | 30 ++++++++++++++++++------------ 3 files changed, 29 insertions(+), 12 deletions(-) diff --git a/cedrus.c b/cedrus.c index 3b45f41..4db5e2d 100644 --- a/cedrus.c +++ b/cedrus.c @@ -243,3 +243,13 @@ EXPORT uint32_t cedrus_mem_get_bus_addr(const struct cedrus_mem *mem) return phys2bus(mem->phys); } + +EXPORT void cedrus_ve_reset(struct cedrus *dev) +{ + if (!dev) + return; + + writel(0x1, dev->regs + VE_RESET); + usleep(1000); + writel(0x0, dev->regs + VE_RESET); +} diff --git a/cedrus.h b/cedrus.h index af3f744..e2801f5 100644 --- a/cedrus.h +++ b/cedrus.h @@ -33,6 +33,7 @@ int cedrus_get_ve_version(cedrus_t *dev); int cedrus_ve_wait(cedrus_t *dev, int timeout); void *cedrus_ve_get(cedrus_t *dev, enum cedrus_engine engine, uint32_t flags); void cedrus_ve_put(cedrus_t *dev); +void cedrus_ve_reset(cedrus_t *dev); typedef struct cedrus_mem cedrus_mem_t; diff --git a/cedrus_regs.h b/cedrus_regs.h index 2c3f0cb..20bc0e7 100644 --- a/cedrus_regs.h +++ b/cedrus_regs.h @@ -32,20 +32,24 @@ static inline uint32_t readl(void *addr) return *((volatile uint32_t *) addr); } -#define VE_CTRL 0x000 -#define VE_EXTRA_OUT_FMT_OFFSET 0x0e8 -#define VE_VERSION 0x0f0 +#define VE_CTRL 0x000 +#define VE_RESET 0x001 +#define VE_OUTPUT_CHROMA_OFFSET 0x0c4 +#define VE_OUTPUT_STRIDE 0x0c8 +#define VE_EXTRA_OUT_FMT_OFFSET 0x0e8 +#define VE_OUTPUT_FORMAT 0x0ec +#define VE_VERSION 0x0f0 #define VE_MPEG_PIC_HDR 0x100 #define VE_MPEG_VOP_HDR 0x104 #define VE_MPEG_SIZE 0x108 #define VE_MPEG_FRAME_SIZE 0x10c -#define VE_MPEG_MBA 0x110 +#define VE_MPEG_MBA 0x110 #define VE_MPEG_CTRL 0x114 #define VE_MPEG_TRIGGER 0x118 #define VE_MPEG_STATUS 0x11c -#define VE_MPEG_TRBTRD_FIELD 0x120 -#define VE_MPEG_TRBTRD_FRAME 0x124 +#define VE_MPEG_TRBTRD_FIELD 0x120 +#define VE_MPEG_TRBTRD_FRAME 0x124 #define VE_MPEG_VLD_ADDR 0x128 #define VE_MPEG_VLD_OFFSET 0x12c #define VE_MPEG_VLD_LEN 0x130 @@ -59,11 +63,11 @@ static inline uint32_t readl(void *addr) #define VE_MPEG_FWD_CHROMA 0x154 #define VE_MPEG_BACK_LUMA 0x158 #define VE_MPEG_BACK_CHROMA 0x15c -#define VE_MPEG_IQ_MIN_INPUT 0x180 +#define VE_MPEG_IQ_MIN_INPUT 0x180 #define VE_MPEG_QP_INPUT 0x184 #define VE_MPEG_JPEG_SIZE 0x1b8 -#define VE_MPEG_JPEG_RES_INT 0x1c0 +#define VE_MPEG_JPEG_RES_INT 0x1c0 #define VE_MPEG_ROT_LUMA 0x1cc #define VE_MPEG_ROT_CHROMA 0x1d0 @@ -92,7 +96,9 @@ static inline uint32_t readl(void *addr) #define VE_H264_OUTPUT_FRAME_IDX 0x24c #define VE_H264_EXTRA_BUFFER1 0x250 #define VE_H264_EXTRA_BUFFER2 0x254 -#define VE_H264_BASIC_BITS 0x2dc +#define VE_H264_MB_ADDR 0x260 +#define VE_H264_ERROR 0x2b8 +#define VE_H264_BASIC_BITS 0x2dc #define VE_H264_RAM_WRITE_PTR 0x2e0 #define VE_H264_RAM_WRITE_DATA 0x2e4 @@ -103,7 +109,7 @@ static inline uint32_t readl(void *addr) #define VE_SRAM_H264_SCALING_LISTS 0x800 #define VE_HEVC_NAL_HDR 0x500 -#define VE_HEVC_SPS 0x504 +#define VE_HEVC_SPS 0x504 #define VE_HEVC_PIC_SIZE 0x508 #define VE_HEVC_PCM_HDR 0x50c #define VE_HEVC_PPS0 0x510 @@ -147,9 +153,9 @@ static inline uint32_t readl(void *addr) #define VE_ISP_INPUT_CHROMA 0xa7c #define VE_AVC_PARAM 0xb04 -#define VE_AVC_QP 0xb08 +#define VE_AVC_QP 0xb08 #define VE_AVC_MOTION_EST 0xb10 -#define VE_AVC_CTRL 0xb14 +#define VE_AVC_CTRL 0xb14 #define VE_AVC_TRIGGER 0xb18 #define VE_AVC_STATUS 0xb1c #define VE_AVC_BASIC_BITS 0xb20 From bd28b5ee76e38ccb0bb61fcfc0f1cf3f3ab39904 Mon Sep 17 00:00:00 2001 From: ubobrov Date: Thu, 10 Sep 2020 11:38:20 +0300 Subject: [PATCH 5/7] reset reg offset fixed --- cedrus_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cedrus_regs.h b/cedrus_regs.h index 20bc0e7..aad4f35 100644 --- a/cedrus_regs.h +++ b/cedrus_regs.h @@ -33,7 +33,7 @@ static inline uint32_t readl(void *addr) } #define VE_CTRL 0x000 -#define VE_RESET 0x001 +#define VE_RESET 0x004 #define VE_OUTPUT_CHROMA_OFFSET 0x0c4 #define VE_OUTPUT_STRIDE 0x0c8 #define VE_EXTRA_OUT_FMT_OFFSET 0x0e8 From 985e9147fbd3bf83ef7652bebb1f562c0b37d2b2 Mon Sep 17 00:00:00 2001 From: agustinov Date: Wed, 15 Oct 2025 02:28:27 +0600 Subject: [PATCH 6/7] Align cedrus regs --- cedrus_regs.h | 276 +++++++++++++++++++++++++------------------------- 1 file changed, 138 insertions(+), 138 deletions(-) diff --git a/cedrus_regs.h b/cedrus_regs.h index aad4f35..8a1dff0 100644 --- a/cedrus_regs.h +++ b/cedrus_regs.h @@ -32,144 +32,144 @@ static inline uint32_t readl(void *addr) return *((volatile uint32_t *) addr); } -#define VE_CTRL 0x000 -#define VE_RESET 0x004 -#define VE_OUTPUT_CHROMA_OFFSET 0x0c4 -#define VE_OUTPUT_STRIDE 0x0c8 -#define VE_EXTRA_OUT_FMT_OFFSET 0x0e8 -#define VE_OUTPUT_FORMAT 0x0ec -#define VE_VERSION 0x0f0 - -#define VE_MPEG_PIC_HDR 0x100 -#define VE_MPEG_VOP_HDR 0x104 -#define VE_MPEG_SIZE 0x108 -#define VE_MPEG_FRAME_SIZE 0x10c -#define VE_MPEG_MBA 0x110 -#define VE_MPEG_CTRL 0x114 -#define VE_MPEG_TRIGGER 0x118 -#define VE_MPEG_STATUS 0x11c -#define VE_MPEG_TRBTRD_FIELD 0x120 -#define VE_MPEG_TRBTRD_FRAME 0x124 -#define VE_MPEG_VLD_ADDR 0x128 -#define VE_MPEG_VLD_OFFSET 0x12c -#define VE_MPEG_VLD_LEN 0x130 -#define VE_MPEG_VLD_END 0x134 -#define VE_MPEG_MBH_ADDR 0x138 -#define VE_MPEG_DCAC_ADDR 0x13c -#define VE_MPEG_NCF_ADDR 0x144 -#define VE_MPEG_REC_LUMA 0x148 -#define VE_MPEG_REC_CHROMA 0x14c -#define VE_MPEG_FWD_LUMA 0x150 -#define VE_MPEG_FWD_CHROMA 0x154 -#define VE_MPEG_BACK_LUMA 0x158 -#define VE_MPEG_BACK_CHROMA 0x15c -#define VE_MPEG_IQ_MIN_INPUT 0x180 -#define VE_MPEG_QP_INPUT 0x184 - -#define VE_MPEG_JPEG_SIZE 0x1b8 -#define VE_MPEG_JPEG_RES_INT 0x1c0 - -#define VE_MPEG_ROT_LUMA 0x1cc -#define VE_MPEG_ROT_CHROMA 0x1d0 -#define VE_MPEG_SDROT_CTRL 0x1d4 - -#define VE_MPEG_RAM_WRITE_PTR 0x1e0 -#define VE_MPEG_RAM_WRITE_DATA 0x1e4 - -#define VE_H264_FRAME_SIZE 0x200 -#define VE_H264_PIC_HDR 0x204 -#define VE_H264_SLICE_HDR 0x208 -#define VE_H264_SLICE_HDR2 0x20c -#define VE_H264_PRED_WEIGHT 0x210 -#define VE_H264_QP_PARAM 0x21c -#define VE_H264_CTRL 0x220 -#define VE_H264_TRIGGER 0x224 -#define VE_H264_STATUS 0x228 -#define VE_H264_CUR_MB_NUM 0x22c -#define VE_H264_VLD_ADDR 0x230 -#define VE_H264_VLD_OFFSET 0x234 -#define VE_H264_VLD_LEN 0x238 -#define VE_H264_VLD_END 0x23c -#define VE_H264_SDROT_CTRL 0x240 -#define VE_H264_SDROT_LUMA 0x244 -#define VE_H264_SDROT_CHROMA 0x248 -#define VE_H264_OUTPUT_FRAME_IDX 0x24c -#define VE_H264_EXTRA_BUFFER1 0x250 -#define VE_H264_EXTRA_BUFFER2 0x254 -#define VE_H264_MB_ADDR 0x260 -#define VE_H264_ERROR 0x2b8 -#define VE_H264_BASIC_BITS 0x2dc -#define VE_H264_RAM_WRITE_PTR 0x2e0 -#define VE_H264_RAM_WRITE_DATA 0x2e4 - -#define VE_SRAM_H264_PRED_WEIGHT_TABLE 0x000 -#define VE_SRAM_H264_FRAMEBUFFER_LIST 0x400 -#define VE_SRAM_H264_REF_LIST0 0x640 -#define VE_SRAM_H264_REF_LIST1 0x664 -#define VE_SRAM_H264_SCALING_LISTS 0x800 - -#define VE_HEVC_NAL_HDR 0x500 -#define VE_HEVC_SPS 0x504 -#define VE_HEVC_PIC_SIZE 0x508 -#define VE_HEVC_PCM_HDR 0x50c -#define VE_HEVC_PPS0 0x510 -#define VE_HEVC_PPS1 0x514 -#define VE_HEVC_SCALING_LIST_CTRL 0x518 -#define VE_HEVC_SLICE_HDR0 0x520 -#define VE_HEVC_SLICE_HDR1 0x524 -#define VE_HEVC_SLICE_HDR2 0x528 -#define VE_HEVC_CTB_ADDR 0x52c -#define VE_HEVC_CTRL 0x530 -#define VE_HEVC_TRIG 0x534 -#define VE_HEVC_STATUS 0x538 -#define VE_HEVC_CTU_NUM 0x53c -#define VE_HEVC_BITS_ADDR 0x540 -#define VE_HEVC_BITS_OFFSET 0x544 -#define VE_HEVC_BITS_LEN 0x548 -#define VE_HEVC_BITS_END_ADDR 0x54c -#define VE_HEVC_REC_BUF_IDX 0x55c -#define VE_HEVC_NEIGHBOR_INFO_ADDR 0x560 -#define VE_HEVC_TILE_LIST_ADDR 0x564 -#define VE_HEVC_TILE_START_CTB 0x568 -#define VE_HEVC_TILE_END_CTB 0x56c -#define VE_HEVC_SCALING_LIST_DC_COEF0 0x578 -#define VE_HEVC_SCALING_LIST_DC_COEF1 0x57c -#define VE_HEVC_BITS_DATA 0x5dc -#define VE_HEVC_SRAM_ADDR 0x5e0 -#define VE_HEVC_SRAM_DATA 0x5e4 - -#define VE_SRAM_HEVC_PRED_WEIGHT_LUMA_L0 0x000 -#define VE_SRAM_HEVC_PRED_WEIGHT_CHROMA_L0 0x020 -#define VE_SRAM_HEVC_PRED_WEIGHT_LUMA_L1 0x060 -#define VE_SRAM_HEVC_PRED_WEIGHT_CHROMA_L1 0x080 -#define VE_SRAM_HEVC_PIC_LIST 0x400 -#define VE_SRAM_HEVC_SCALING_LISTS 0x800 -#define VE_SRAM_HEVC_REF_PIC_LIST0 0xc00 -#define VE_SRAM_HEVC_REF_PIC_LIST1 0xc10 - -#define VE_ISP_INPUT_SIZE 0xa00 -#define VE_ISP_INPUT_STRIDE 0xa04 -#define VE_ISP_INPUT_LUMA 0xa78 -#define VE_ISP_INPUT_CHROMA 0xa7c - -#define VE_AVC_PARAM 0xb04 -#define VE_AVC_QP 0xb08 -#define VE_AVC_MOTION_EST 0xb10 -#define VE_AVC_CTRL 0xb14 -#define VE_AVC_TRIGGER 0xb18 -#define VE_AVC_STATUS 0xb1c -#define VE_AVC_BASIC_BITS 0xb20 -#define VE_AVC_VLE_ADDR 0xb80 -#define VE_AVC_VLE_END 0xb84 -#define VE_AVC_VLE_OFFSET 0xb88 -#define VE_AVC_VLE_LENGTH 0xb90 -#define VE_AVC_REF_LUMA 0xba0 -#define VE_AVC_REF_CHROMA 0xba4 -#define VE_AVC_REC_LUMA 0xbb0 -#define VE_AVC_REC_CHROMA 0xbb4 -#define VE_AVC_REF_SLUMA 0xbb8 -#define VE_AVC_REC_SLUMA 0xbbc -#define VE_AVC_MB_INFO 0xbc0 +#define VE_CTRL 0x000 +#define VE_RESET 0x004 +#define VE_OUTPUT_CHROMA_OFFSET 0x0c4 +#define VE_OUTPUT_STRIDE 0x0c8 +#define VE_EXTRA_OUT_FMT_OFFSET 0x0e8 +#define VE_OUTPUT_FORMAT 0x0ec +#define VE_VERSION 0x0f0 + +#define VE_MPEG_PIC_HDR 0x100 +#define VE_MPEG_VOP_HDR 0x104 +#define VE_MPEG_SIZE 0x108 +#define VE_MPEG_FRAME_SIZE 0x10c +#define VE_MPEG_MBA 0x110 +#define VE_MPEG_CTRL 0x114 +#define VE_MPEG_TRIGGER 0x118 +#define VE_MPEG_STATUS 0x11c +#define VE_MPEG_TRBTRD_FIELD 0x120 +#define VE_MPEG_TRBTRD_FRAME 0x124 +#define VE_MPEG_VLD_ADDR 0x128 +#define VE_MPEG_VLD_OFFSET 0x12c +#define VE_MPEG_VLD_LEN 0x130 +#define VE_MPEG_VLD_END 0x134 +#define VE_MPEG_MBH_ADDR 0x138 +#define VE_MPEG_DCAC_ADDR 0x13c +#define VE_MPEG_NCF_ADDR 0x144 +#define VE_MPEG_REC_LUMA 0x148 +#define VE_MPEG_REC_CHROMA 0x14c +#define VE_MPEG_FWD_LUMA 0x150 +#define VE_MPEG_FWD_CHROMA 0x154 +#define VE_MPEG_BACK_LUMA 0x158 +#define VE_MPEG_BACK_CHROMA 0x15c +#define VE_MPEG_IQ_MIN_INPUT 0x180 +#define VE_MPEG_QP_INPUT 0x184 + +#define VE_MPEG_JPEG_SIZE 0x1b8 +#define VE_MPEG_JPEG_RES_INT 0x1c0 + +#define VE_MPEG_ROT_LUMA 0x1cc +#define VE_MPEG_ROT_CHROMA 0x1d0 +#define VE_MPEG_SDROT_CTRL 0x1d4 + +#define VE_MPEG_RAM_WRITE_PTR 0x1e0 +#define VE_MPEG_RAM_WRITE_DATA 0x1e4 + +#define VE_H264_FRAME_SIZE 0x200 +#define VE_H264_PIC_HDR 0x204 +#define VE_H264_SLICE_HDR 0x208 +#define VE_H264_SLICE_HDR2 0x20c +#define VE_H264_PRED_WEIGHT 0x210 +#define VE_H264_QP_PARAM 0x21c +#define VE_H264_CTRL 0x220 +#define VE_H264_TRIGGER 0x224 +#define VE_H264_STATUS 0x228 +#define VE_H264_CUR_MB_NUM 0x22c +#define VE_H264_VLD_ADDR 0x230 +#define VE_H264_VLD_OFFSET 0x234 +#define VE_H264_VLD_LEN 0x238 +#define VE_H264_VLD_END 0x23c +#define VE_H264_SDROT_CTRL 0x240 +#define VE_H264_SDROT_LUMA 0x244 +#define VE_H264_SDROT_CHROMA 0x248 +#define VE_H264_OUTPUT_FRAME_IDX 0x24c +#define VE_H264_EXTRA_BUFFER1 0x250 +#define VE_H264_EXTRA_BUFFER2 0x254 +#define VE_H264_MB_ADDR 0x260 +#define VE_H264_ERROR 0x2b8 +#define VE_H264_BASIC_BITS 0x2dc +#define VE_H264_RAM_WRITE_PTR 0x2e0 +#define VE_H264_RAM_WRITE_DATA 0x2e4 + +#define VE_SRAM_H264_PRED_WEIGHT_TABLE 0x000 +#define VE_SRAM_H264_FRAMEBUFFER_LIST 0x400 +#define VE_SRAM_H264_REF_LIST0 0x640 +#define VE_SRAM_H264_REF_LIST1 0x664 +#define VE_SRAM_H264_SCALING_LISTS 0x800 + +#define VE_HEVC_NAL_HDR 0x500 +#define VE_HEVC_SPS 0x504 +#define VE_HEVC_PIC_SIZE 0x508 +#define VE_HEVC_PCM_HDR 0x50c +#define VE_HEVC_PPS0 0x510 +#define VE_HEVC_PPS1 0x514 +#define VE_HEVC_SCALING_LIST_CTRL 0x518 +#define VE_HEVC_SLICE_HDR0 0x520 +#define VE_HEVC_SLICE_HDR1 0x524 +#define VE_HEVC_SLICE_HDR2 0x528 +#define VE_HEVC_CTB_ADDR 0x52c +#define VE_HEVC_CTRL 0x530 +#define VE_HEVC_TRIG 0x534 +#define VE_HEVC_STATUS 0x538 +#define VE_HEVC_CTU_NUM 0x53c +#define VE_HEVC_BITS_ADDR 0x540 +#define VE_HEVC_BITS_OFFSET 0x544 +#define VE_HEVC_BITS_LEN 0x548 +#define VE_HEVC_BITS_END_ADDR 0x54c +#define VE_HEVC_REC_BUF_IDX 0x55c +#define VE_HEVC_NEIGHBOR_INFO_ADDR 0x560 +#define VE_HEVC_TILE_LIST_ADDR 0x564 +#define VE_HEVC_TILE_START_CTB 0x568 +#define VE_HEVC_TILE_END_CTB 0x56c +#define VE_HEVC_SCALING_LIST_DC_COEF0 0x578 +#define VE_HEVC_SCALING_LIST_DC_COEF1 0x57c +#define VE_HEVC_BITS_DATA 0x5dc +#define VE_HEVC_SRAM_ADDR 0x5e0 +#define VE_HEVC_SRAM_DATA 0x5e4 + +#define VE_SRAM_HEVC_PRED_WEIGHT_LUMA_L0 0x000 +#define VE_SRAM_HEVC_PRED_WEIGHT_CHROMA_L0 0x020 +#define VE_SRAM_HEVC_PRED_WEIGHT_LUMA_L1 0x060 +#define VE_SRAM_HEVC_PRED_WEIGHT_CHROMA_L1 0x080 +#define VE_SRAM_HEVC_PIC_LIST 0x400 +#define VE_SRAM_HEVC_SCALING_LISTS 0x800 +#define VE_SRAM_HEVC_REF_PIC_LIST0 0xc00 +#define VE_SRAM_HEVC_REF_PIC_LIST1 0xc10 + +#define VE_ISP_INPUT_SIZE 0xa00 +#define VE_ISP_INPUT_STRIDE 0xa04 +#define VE_ISP_INPUT_LUMA 0xa78 +#define VE_ISP_INPUT_CHROMA 0xa7c + +#define VE_AVC_PARAM 0xb04 +#define VE_AVC_QP 0xb08 +#define VE_AVC_MOTION_EST 0xb10 +#define VE_AVC_CTRL 0xb14 +#define VE_AVC_TRIGGER 0xb18 +#define VE_AVC_STATUS 0xb1c +#define VE_AVC_BASIC_BITS 0xb20 +#define VE_AVC_VLE_ADDR 0xb80 +#define VE_AVC_VLE_END 0xb84 +#define VE_AVC_VLE_OFFSET 0xb88 +#define VE_AVC_VLE_LENGTH 0xb90 +#define VE_AVC_REF_LUMA 0xba0 +#define VE_AVC_REF_CHROMA 0xba4 +#define VE_AVC_REC_LUMA 0xbb0 +#define VE_AVC_REC_CHROMA 0xbb4 +#define VE_AVC_REF_SLUMA 0xbb8 +#define VE_AVC_REC_SLUMA 0xbbc +#define VE_AVC_MB_INFO 0xbc0 #endif From 4d87b87a17445fcee539880d16b8e4c3232c45b0 Mon Sep 17 00:00:00 2001 From: agustinov Date: Mon, 15 Dec 2025 11:38:00 +0600 Subject: [PATCH 7/7] Add some cedrus regs --- cedrus.c | 14 ++++++----- cedrus.h | 8 +++++- cedrus_regs.h | 68 +++++++++++++++++++++++++++++++++++---------------- 3 files changed, 62 insertions(+), 28 deletions(-) diff --git a/cedrus.c b/cedrus.c index 4db5e2d..3e9bb94 100644 --- a/cedrus.c +++ b/cedrus.c @@ -47,7 +47,7 @@ static struct cedrus pthread_mutex_t device_lock; } ve = { .fd = -1, .device_lock = PTHREAD_MUTEX_INITIALIZER }; -EXPORT struct cedrus *cedrus_open(void) +EXPORT cedrus_t *cedrus_open(void) { pthread_mutex_lock(&open_lock); if (ve.fd != -1) { @@ -96,14 +96,16 @@ EXPORT struct cedrus *cedrus_open(void) ioctl(ve.fd, IOCTL_SET_VE_FREQ + ve.ioctl_offset, 320); ioctl(ve.fd, IOCTL_RESET_VE + ve.ioctl_offset, 0); - writel(0x00130007, ve.regs + VE_CTRL); + writel(0x00130000 | VE_CTRL_ENGINE_RESET, ve.regs + VE_CTRL); + //printf("[libcedrus SUNXI] VE version 0x%04x opened\n", ve.version); open_count++; pthread_mutex_unlock(&open_lock); return &ve; unmap: munmap(ve.regs, 0x800); + close: close(ve.fd); ve.fd = -1; @@ -152,11 +154,11 @@ EXPORT int cedrus_ve_wait(struct cedrus *dev, int timeout) if (!dev) return -1; - if (((reg = readl(dev->regs + VE_CTRL)) & CEDRUS_ENGINE_H264_ENC) == CEDRUS_ENGINE_H264_ENC) { + if (((reg = readl(dev->regs + VE_CTRL)) & VE_CTRL_ENGINE_FIELD) == VE_CTRL_ENGINE_AVC) { engine_wait = IOCTL_WAIT_VE_DE + dev->ioctl_offset; } - //printf("we engine %04X, we wait %d\n", reg, engine_wait); + //printf("ve engine %04X, ve wait %d\n", reg, engine_wait); return ioctl(dev->fd, engine_wait, timeout); } @@ -166,7 +168,7 @@ EXPORT void *cedrus_ve_get(struct cedrus *dev, enum cedrus_engine engine, uint32 if (!dev || pthread_mutex_lock(&dev->device_lock)) return NULL; - writel(0x00130000 | (engine & 0xf) | (flags & ~0xf), dev->regs + VE_CTRL); + writel(0x00130000 | (engine & VE_CTRL_ENGINE_FIELD) | (flags & ~VE_CTRL_ENGINE_FIELD), dev->regs + VE_CTRL); return dev->regs; } @@ -176,7 +178,7 @@ EXPORT void cedrus_ve_put(struct cedrus *dev) if (!dev) return; - writel(0x00130007, dev->regs + VE_CTRL); + writel(0x00130000 | VE_CTRL_ENGINE_RESET, dev->regs + VE_CTRL); pthread_mutex_unlock(&dev->device_lock); } diff --git a/cedrus.h b/cedrus.h index e2801f5..bcc22cc 100644 --- a/cedrus.h +++ b/cedrus.h @@ -22,10 +22,16 @@ #include #include +#include "cedrus_regs.h" typedef struct cedrus cedrus_t; -enum cedrus_engine { CEDRUS_ENGINE_MPEG = 0x0, CEDRUS_ENGINE_H264 = 0x1, CEDRUS_ENGINE_HEVC = 0x4, CEDRUS_ENGINE_H264_ENC = 0xb }; +enum cedrus_engine { + CEDRUS_ENGINE_MPEG = VE_CTRL_ENGINE_MPEG, + CEDRUS_ENGINE_H264 = VE_CTRL_ENGINE_H264, + CEDRUS_ENGINE_HEVC = VE_CTRL_ENGINE_HEVC, + CEDRUS_ENGINE_AVC = VE_CTRL_ENGINE_AVC +}; cedrus_t *cedrus_open(void); void cedrus_close(cedrus_t *dev); diff --git a/cedrus_regs.h b/cedrus_regs.h index 8a1dff0..95e19f3 100644 --- a/cedrus_regs.h +++ b/cedrus_regs.h @@ -32,6 +32,7 @@ static inline uint32_t readl(void *addr) return *((volatile uint32_t *) addr); } +// VE general registers #define VE_CTRL 0x000 #define VE_RESET 0x004 #define VE_OUTPUT_CHROMA_OFFSET 0x0c4 @@ -40,6 +41,25 @@ static inline uint32_t readl(void *addr) #define VE_OUTPUT_FORMAT 0x0ec #define VE_VERSION 0x0f0 +// VE_CTRL register values +#define VE_CTRL_ENGINE_MPEG 0x00 +#define VE_CTRL_ENGINE_H264 0x01 +#define VE_CTRL_ENGINE_HEVC 0x04 +#define VE_CTRL_ENGINE_RESET 0x07 +#define VE_CTRL_ENGINE_AVC 0x0b +#define VE_CTRL_ENGINE_FIELD 0x0f +#define VE_CTRL_ENABLE_ISP 0x40 +#define VE_CTRL_ENABLE_AVC 0x80 + +// VE_OUTPUT_FORMAT register values +#define VE_OUTPUT_FORMAT_TILE32x32 0x00 +#define VE_OUTPUT_FORMAT_TILE128x32 0x10 +#define VE_OUTPUT_FORMAT_I420 0x20 +#define VE_OUTPUT_FORMAT_YV12 0x30 +#define VE_OUTPUT_FORMAT_NV12 0x40 +#define VE_OUTPUT_FORMAT_NV21 0x50 + +// VE MPEG engine registers #define VE_MPEG_PIC_HDR 0x100 #define VE_MPEG_VOP_HDR 0x104 #define VE_MPEG_SIZE 0x108 @@ -65,17 +85,15 @@ static inline uint32_t readl(void *addr) #define VE_MPEG_BACK_CHROMA 0x15c #define VE_MPEG_IQ_MIN_INPUT 0x180 #define VE_MPEG_QP_INPUT 0x184 - #define VE_MPEG_JPEG_SIZE 0x1b8 #define VE_MPEG_JPEG_RES_INT 0x1c0 - #define VE_MPEG_ROT_LUMA 0x1cc #define VE_MPEG_ROT_CHROMA 0x1d0 #define VE_MPEG_SDROT_CTRL 0x1d4 +#define VE_MPEG_SRAM_ADDR 0x1e0 +#define VE_MPEG_SRAM_DATA 0x1e4 -#define VE_MPEG_RAM_WRITE_PTR 0x1e0 -#define VE_MPEG_RAM_WRITE_DATA 0x1e4 - +// VE H264 engine registers #define VE_H264_FRAME_SIZE 0x200 #define VE_H264_PIC_HDR 0x204 #define VE_H264_SLICE_HDR 0x208 @@ -99,15 +117,17 @@ static inline uint32_t readl(void *addr) #define VE_H264_MB_ADDR 0x260 #define VE_H264_ERROR 0x2b8 #define VE_H264_BASIC_BITS 0x2dc -#define VE_H264_RAM_WRITE_PTR 0x2e0 -#define VE_H264_RAM_WRITE_DATA 0x2e4 +#define VE_H264_SRAM_ADDR 0x2e0 +#define VE_H264_SRAM_DATA 0x2e4 -#define VE_SRAM_H264_PRED_WEIGHT_TABLE 0x000 -#define VE_SRAM_H264_FRAMEBUFFER_LIST 0x400 -#define VE_SRAM_H264_REF_LIST0 0x640 -#define VE_SRAM_H264_REF_LIST1 0x664 -#define VE_SRAM_H264_SCALING_LISTS 0x800 +// VE_H264_SRAM_ADDR register values +#define VE_H264_SRAM_PRED_WEIGHT_TABLE 0x000 +#define VE_H264_SRAM_FRAMEBUFFER_LIST 0x400 +#define VE_H264_SRAM_REF_LIST0 0x640 +#define VE_H264_SRAM_REF_LIST1 0x664 +#define VE_H264_SRAM_SCALING_LISTS 0x800 +// VE HEVC engine registers #define VE_HEVC_NAL_HDR 0x500 #define VE_HEVC_SPS 0x504 #define VE_HEVC_PIC_SIZE 0x508 @@ -138,20 +158,24 @@ static inline uint32_t readl(void *addr) #define VE_HEVC_SRAM_ADDR 0x5e0 #define VE_HEVC_SRAM_DATA 0x5e4 -#define VE_SRAM_HEVC_PRED_WEIGHT_LUMA_L0 0x000 -#define VE_SRAM_HEVC_PRED_WEIGHT_CHROMA_L0 0x020 -#define VE_SRAM_HEVC_PRED_WEIGHT_LUMA_L1 0x060 -#define VE_SRAM_HEVC_PRED_WEIGHT_CHROMA_L1 0x080 -#define VE_SRAM_HEVC_PIC_LIST 0x400 -#define VE_SRAM_HEVC_SCALING_LISTS 0x800 -#define VE_SRAM_HEVC_REF_PIC_LIST0 0xc00 -#define VE_SRAM_HEVC_REF_PIC_LIST1 0xc10 - +// VE_HEVC_SRAM_ADDR register values +#define VE_HEVC_SRAM_PRED_WEIGHT_LUMA_L0 0x000 +#define VE_HEVC_SRAM_PRED_WEIGHT_CHROMA_L0 0x020 +#define VE_HEVC_SRAM_PRED_WEIGHT_LUMA_L1 0x060 +#define VE_HEVC_SRAM_PRED_WEIGHT_CHROMA_L1 0x080 +#define VE_HEVC_SRAM_PIC_LIST 0x400 +#define VE_HEVC_SRAM_SCALING_LISTS 0x800 +#define VE_HEVC_SRAM_REF_PIC_LIST0 0xc00 +#define VE_HEVC_SRAM_REF_PIC_LIST1 0xc10 + +// VE ISP engine registers #define VE_ISP_INPUT_SIZE 0xa00 #define VE_ISP_INPUT_STRIDE 0xa04 +#define VE_ISP_CTRL 0xa08 #define VE_ISP_INPUT_LUMA 0xa78 #define VE_ISP_INPUT_CHROMA 0xa7c +// VE AVC engine registers #define VE_AVC_PARAM 0xb04 #define VE_AVC_QP 0xb08 #define VE_AVC_MOTION_EST 0xb10 @@ -159,9 +183,11 @@ static inline uint32_t readl(void *addr) #define VE_AVC_TRIGGER 0xb18 #define VE_AVC_STATUS 0xb1c #define VE_AVC_BASIC_BITS 0xb20 +#define VE_AVC_UNK_BUF 0xb60 #define VE_AVC_VLE_ADDR 0xb80 #define VE_AVC_VLE_END 0xb84 #define VE_AVC_VLE_OFFSET 0xb88 +#define VE_AVC_VLE_MAX 0xb8c #define VE_AVC_VLE_LENGTH 0xb90 #define VE_AVC_REF_LUMA 0xba0 #define VE_AVC_REF_CHROMA 0xba4