driver:dram: fix some dram configuration issues

Fix ZPROG[7:0] Impedance Divide Ratio, the value is 13 for 34Ohms.
Fix DDR3 driver impedance value in KCONFIG, it support 34 and 40 ohms
 only.
To be on the safe side, the AS4C256M16D3LC-10BIN should be configured
as an 1866M, even though the 1600K works, but the risk is that there
is a difference in tRP and tRCD timing between the 1600K and the 1866M.
Set the speed bin to 1866 instead of 1333 for MT52L256M32D1PF_107 for
performace.

Signed-off-by: Li Bin <bin.li@microchip.com>
Signed-off-by: Hari Prasath Gujulan Elango <hari.prasathge@microchip.com>

Author: LiBinSHA

Kconfig

@@ -577,10 +577,10 @@ config DDR_DRIVER_IMPEDANCE
 	default 40 if DDR_MT47H128M16RT_25E_C
 	default 48 if DDR_IS43LD16128B_25BLI
 	default 48 if DDR_MT52L256M32D1PF_107
-	default 48 if DDR_MT41K128M16JT_125
-	default 48 if DDR_W631GU6NB
-	default 48 if DDR_W632GU6NB12I
-	default 48 if DDR_AS4C512M16D3LA_10BIN
+	default 40 if DDR_MT41K128M16JT_125
+	default 40 if DDR_W631GU6NB
+	default 40 if DDR_W632GU6NB12I
+	default 40 if DDR_AS4C512M16D3LA_10BIN
 	default 40 if DDR_AS4C128M16D2A_25BAN
 	default 40 if DDR_EM68D16CBQC_18IH
 	default 48 if DDR_W97AH6NBVA1K
@@ -602,7 +602,7 @@ config DDR_ODT_IMPEDANCE
 	default 50 if DDR_EM68D16CBQC_18IH
 	default 0 if DDR_IS43LD16128B_25BLI
 	default 0 if DDR_W97AH6NBVA1K
-	default 120 if DDR_MT52L256M32D1PF_107
+	default 60 if DDR_MT52L256M32D1PF_107
 	default 0 if DDR_SET_BY_JEDEC || DDR_SET_BY_TIMING
 	depends on UMCTL2
 	help

driver/driver_cpp.mk

@@ -91,7 +91,7 @@ ifeq ($(CONFIG_DDR_AS4C256M16D3LC_12BCNTR), y)
 CPPFLAGS += -DCONFIG_DDR3 -DCONFIG_DDR3_SPEED_BIN_1600K -DCONFIG_DDR_4_GBIT -DCONFIG_DBW_16
 endif
 ifeq ($(CONFIG_DDR_AS4C512M16D3LA_10BIN), y)
-CPPFLAGS += -DCONFIG_DDR3 -DCONFIG_DDR3_SPEED_BIN_1600K -DCONFIG_DDR_8_GBIT -DCONFIG_DBW_16
+CPPFLAGS += -DCONFIG_DDR3 -DCONFIG_DDR3_SPEED_BIN_1866M -DCONFIG_DDR_8_GBIT -DCONFIG_DBW_16
 endif
 ifeq ($(CONFIG_DDR_W632GU6NB12I), y)
 CPPFLAGS += -DCONFIG_DDR3 -DCONFIG_DDR3_SPEED_BIN_1600K -DCONFIG_DDR_2_GBIT
@@ -106,7 +106,7 @@ ifeq ($(CONFIG_DDR_IS43LD16128B_25BLI), y)
 CPPFLAGS += -DCONFIG_LPDDR2 -DCONFIG_LPDDR2_S4 -DCONFIG_LPDDR2_SPEED_800 -DCONFIG_DDR_2_GBIT -DCONFIG_DBW_16
 endif
 ifeq ($(CONFIG_DDR_MT52L256M32D1PF_107), y)
-CPPFLAGS += -DCONFIG_LPDDR3 -DCONFIG_LPDDR3_SPEED_1333 -DCONFIG_DDR_8_GBIT -DCONFIG_DBW_32
+CPPFLAGS += -DCONFIG_LPDDR3 -DCONFIG_LPDDR3_SPEED_1866 -DCONFIG_DDR_8_GBIT -DCONFIG_DBW_32
 endif
 ifeq ($(CONFIG_DDR_EDB5432BEBH_1DAAT_F_D),y)
 CPPFLAGS += -DCONFIG_LPDDR2 -DCONFIG_LPDDR2_S4 -DCONFIG_LPDDR2_SPEED_800 -DCONFIG_DDR_512_MBIT -DCONFIG_DBW_16

include/dram_helpers.h

@@ -253,7 +253,7 @@
 #define T_ZQ_RESET_NOP		0
 #define WLTPHY			WL
 #define RLTPHY			RL
-#define ZPROG_OUTPUT	((CONFIG_DDR_DRIVER_IMPEDANCE == 40) ? 11 : 12)
+#define ZPROG_OUTPUT	((CONFIG_DDR_DRIVER_IMPEDANCE == 40) ? 11 : 13)
 #define ZPROG_ODT		((CONFIG_DDR_ODT_IMPEDANCE == 120) ? 2 : (CONFIG_DDR_ODT_IMPEDANCE == 60) ? 6 : 9)
 
 #elif defined(CONFIG_LPDDR2)