Skip to content

Commit 4355ecf

Browse files
LiBinSHAHari Prasath Gujulan Elango
LiBinSHA
authored and
Hari Prasath Gujulan Elango
committed
driver:ddram:add new ddram support for sam9x7
New DDR3L W631GU6NG(8M x 8BANKS X 16 BIT DDR3L SDRAM 1 Gbit) configs and timing. New DDR2 W9751G6NB(8M x 4BANKS x 16 BIT DDR2 SDRAM 512 Mbits) configs and timing. Signed-off-by: Li Bin <bin.li@microchip.com> Signed-off-by: Hari Prasath Gujulan Elango <hari.prasathge@microchip.com>
1 parent ef0ddab commit 4355ecf

File tree

4 files changed

+136
-1
lines changed

4 files changed

+136
-1
lines changed

‎driver/Config.in.dram‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -83,10 +83,20 @@ config DDR_W971GG6SB
8383
help
8484
DDR2 W971GG6SB 1 Gbit
8585
config DDR_W632GU6NG
86-
bool "DDR3L W632GU6NG (SAM9X75D2G SiP)"
86+
bool "DDR3L W632GU6NG (SAM9X75-2G SiP)"
8787
depends on DDRC
8888
help
8989
DDR3L W632GU6NG 2 Gbit
90+
config DDR_W631GU6NG
91+
bool "DDR3L W631GU6NG (SAM9X75-1G SiP)"
92+
depends on DDRC
93+
help
94+
DDR3L W631GU6NG 2 Gbit
95+
config DDR_W9751G6NB
96+
bool "DDR3L W9751G6NB (SAM9X75-512M SiP)"
97+
depends on DDRC
98+
help
99+
DDR3L W9751G6NB 512M bit
90100
config DDR_AD220032D
91101
bool "LPDDR2 AD220032D(SAMA5D2-WLSOM-EK)"
92102
depends on DDRC

‎driver/ddramc.c‎

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -104,6 +104,45 @@ static void ddram_reg_config(struct ddramc_register *ddramc_config)
104104
*/
105105
ddramc_config->cal_mr4r = AT91C_DDRC2_COUNT_CAL(0xC852);
106106
ddramc_config->tim_calr = AT91C_DDRC2_ZQCS(64);
107+
108+
#elif defined(CONFIG_DDR_W631GU6NG)
109+
/* DDR3L(W631GU6NG = 8 Mbit x 16 x 8 banks), total 1Gbit on SAM9X75 SIP */
110+
type = AT91C_DDRC2_MD_DDR3_SDRAM;
111+
dbw = AT91C_DDRC2_DBW_16_BITS;
112+
col = AT91C_DDRC2_NC_DDR10_SDR9;
113+
row = AT91C_DDRC2_NR_13;
114+
cas = AT91C_DDRC2_CAS_5;
115+
bank = AT91C_DDRC2_NB_BANKS_8;
116+
#if defined(CONFIG_BUS_SPEED_200MHZ)
117+
/* Refresh Timer is (64ms / 8k) * 116MHz = 1562(0x61a) */
118+
ddramc_config->rtr = 0x61a;
119+
#elif defined(CONFIG_BUS_SPEED_266MHZ)
120+
/* Refresh Timer is (64ms / 8k) * 116MHz = 2078(0x81e) */
121+
ddramc_config->rtr = 0x81e;
122+
#else
123+
#error "No CLK setting defined"
124+
#endif
125+
ddramc_config->cal_mr4r = AT91C_DDRC2_COUNT_CAL(0xC852);
126+
ddramc_config->tim_calr = AT91C_DDRC2_ZQCS(64);
127+
#elif defined(CONFIG_DDR_W9751G6NB)
128+
/* DDR2(W9751G6NB = 8 Mbit x 16 x 4 banks), total 512M bit on SAM9X75 SIP */
129+
type = AT91C_DDRC2_MD_DDR2_SDRAM;
130+
dbw = AT91C_DDRC2_DBW_16_BITS;
131+
col = AT91C_DDRC2_NC_DDR10_SDR9;
132+
row = AT91C_DDRC2_NR_13;
133+
cas = AT91C_DDRC2_CAS_3;
134+
bank = AT91C_DDRC2_NB_BANKS_4;
135+
#if defined(CONFIG_BUS_SPEED_200MHZ)
136+
/* Refresh Timer is (64ms / 8k) * 116MHz = 1562(0x61a) */
137+
ddramc_config->rtr = 0x61a;
138+
#elif defined(CONFIG_BUS_SPEED_266MHZ)
139+
/* Refresh Timer is (64ms / 8k) * 116MHz = 2078(0x81e) */
140+
ddramc_config->rtr = 0x81e;
141+
#else
142+
#error "No CLK setting defined"
143+
#endif
144+
ddramc_config->cal_mr4r = AT91C_DDRC2_COUNT_CAL(0xC852);
145+
ddramc_config->tim_calr = AT91C_DDRC2_ZQCS(64);
107146
#elif defined(CONFIG_DDR_W632GU6MB)
108147
/* Two DDR3L(W632GU6MB-12 = 16 Mbit x 16 x 8 banks), total 4 Gbit on SAMA5D2 ICP*/
109148
type = AT91C_DDRC2_MD_DDR3_SDRAM;

‎driver/driver_cpp.mk‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,12 @@ endif
3030
ifeq ($(CONFIG_DDR_W632GU6NG),y)
3131
CPPFLAGS += -DCONFIG_DDR3 -DCONFIG_DDR_2_GBIT
3232
endif
33+
ifeq ($(CONFIG_DDR_W631GU6NG),y)
34+
CPPFLAGS += -DCONFIG_DDR3 -DCONFIG_DDR_1_GBIT
35+
endif
36+
ifeq ($(CONFIG_DDR_W9751G6NB),y)
37+
CPPFLAGS += -DCONFIG_DDR2 -DCONFIG_DDR_512_MBIT
38+
endif
3339
ifeq ($(CONFIG_DDR_W632GU6MB),y)
3440
CPPFLAGS += -DCONFIG_DDR3 -DCONFIG_DDR_4_GBIT
3541
endif

‎include/ddr_device.h‎

Lines changed: 80 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -139,6 +139,86 @@ static const struct ddram_timings ddr_ddram_timings = {
139139
#error "No CLK setting defined"
140140
#endif /* Endif of CONFIG_BUS_SPEED_200MHZ */
141141

142+
#elif defined(CONFIG_DDR_W631GU6NG)
143+
/* DDR3L (W631GU6NG = 8 Mbit x 16 x 8 banks), total 1Gbit on SAM9X75-SIP */
144+
#if defined(CONFIG_BUS_SPEED_200MHZ)
145+
.tras = 7,
146+
.trcd = 3,
147+
.twr = 3,
148+
.trc = 10,
149+
.trp = 3,
150+
.trrd = 4,
151+
.twtr = 4,
152+
.tmrd = 4,
153+
.trfc = 22,
154+
.txsnr = 33,
155+
.txsrd = 0,
156+
.txp = 10,
157+
.txard = 0,
158+
.txards = 0,
159+
.trpa = 0,
160+
.trtp = 4,
161+
.tfaw = 8,
162+
#elif defined(CONFIG_BUS_SPEED_266MHZ)
163+
.tras = 10,
164+
.trcd = 4,
165+
.twr = 4,
166+
.trc = 13,
167+
.trp = 4,
168+
.trrd = 4,
169+
.twtr = 4,
170+
.tmrd = 4,
171+
.trfc = 30,
172+
.txsnr = 46,
173+
.txsrd = 0,
174+
.txp = 10,
175+
.txard = 0,
176+
.txards = 0,
177+
.trpa = 0,
178+
.trtp = 4,
179+
.tfaw = 11,
180+
#else
181+
#error "No CLK setting defined"
182+
#endif /* Endif of CONFIG_BUS_SPEED_200MHZ */
183+
#elif defined(CONFIG_DDR_W9751G6NB)
184+
/* DDR2 (W9751G6NB 512Mbits = 8 Mbits x 16 x 8 banks), total 512 Mbits on the SAM9X70-SIP */
185+
#if defined(CONFIG_BUS_SPEED_200MHZ)
186+
.tras = 9,
187+
.trcd = 3,
188+
.twr = 3,
189+
.trc = 12,
190+
.trp = 3,
191+
.trrd = 2,
192+
.twtr = 2,
193+
.tmrd = 2,
194+
.trfc = 21,
195+
.txsnr = 31,
196+
.txsrd = 200,
197+
.txp = 2,
198+
.txard = 2,
199+
.txards = 6,
200+
.trpa = 3,
201+
.trtp = 2,
202+
.tfaw = 8,
203+
#elif defined(CONFIG_BUS_SPEED_266MHZ)
204+
.tras = 12,
205+
.trcd = 3,
206+
.twr = 4,
207+
.trc = 15,
208+
.trp = 3,
209+
.trrd = 3,
210+
.twtr = 2,
211+
.tmrd = 2,
212+
.trfc = 28,
213+
.txsnr = 38,
214+
.txsrd = 200,
215+
.txp = 2,
216+
.txard = 2,
217+
.txards = 6,
218+
.trpa = 3,
219+
.trtp = 2,
220+
.tfaw = 10,
221+
#endif
142222
#elif defined(CONFIG_DDR_W632GU6MB)
143223
/* Two DDR3L(W632GU6MB-12 = 16 Mbit x 16 x 8 banks), total 4 Gbit on SAMA5D2 ICP*/
144224
#if defined(CONFIG_BUS_SPEED_166MHZ)

0 commit comments

Comments
 (0)