InputBus.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:03:07 05/20/2018 
-- Design Name: 
-- Module Name:    InputBus - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity InputBus is
port ( 
dataIn : in std_logic_vector (7 downto 0 );
CS ,RD : in std_logic;
dataOut : in std_logic_vector (7 downto 0 )
);
end InputBus;

architecture Behavioral of InputBus is

begin


end Behavioral;