Using the MTVAL register to store AHB errors

[andrenemat]

SW team is asking how they can handle errors on the AHB Lite bus.
If they try accessing an invalid AHB address for example, they are getting a trap. But they are wondering how they can get more information about the failed access (which address, etc.).
Is this information captured in one of the RISC-V registers?

[TommyMurphyTM1234]

Whenever investigating traps, it generally makes sense to check the following registers:

• mcause
• mepc
• mtval

which are documented in the The RISC-V Instruction Set Manual
Volume II: Privileged Architecture:

• https://riscv.org/technical/specifications/

I don't know what "Using the MTVAL register to store AHB errors" means.

[andrenemat]

Sorry for the Title, originally the question was asked in a different way.

Thanks for the suggestion of the mcause and mepc registers, we had only reviewed the MTVAL.

[TommyMurphyTM1234]

You should probably read this so:

• https://mi-v-ecosystem.github.io/SoftConsole-Documentation/SoftConsole-v2022.2-RISC-V/troubleshooting/riscv_trap.html

[andrenemat]

Thanks a lot. This is a very detailed document.